2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "util/disk_cache.h"
40 #include "brw_defines.h"
41 #include "brw_state.h"
42 #include "compiler/nir/nir.h"
45 #include "util/disk_cache.h"
46 #include "util/xmlpool.h"
48 #include "common/gen_defines.h"
50 static const __DRIconfigOptionsExtension brw_config_options
= {
51 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
54 DRI_CONF_SECTION_PERFORMANCE
55 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
56 * DRI_CONF_BO_REUSE_ALL
58 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
59 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
60 DRI_CONF_ENUM(0, "Disable buffer object reuse")
61 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
64 DRI_CONF_MESA_NO_ERROR("false")
67 DRI_CONF_SECTION_QUALITY
68 DRI_CONF_PRECISE_TRIG("false")
70 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
71 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
72 "given integer. If negative, then do not clamp.")
76 DRI_CONF_SECTION_DEBUG
77 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
78 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
79 DRI_CONF_DISABLE_THROTTLING("false")
80 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
81 DRI_CONF_FORCE_GLSL_VERSION(0)
82 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
83 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
84 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
85 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
86 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
87 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
88 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
89 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
91 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
92 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
96 DRI_CONF_SECTION_MISCELLANEOUS
97 DRI_CONF_GLSL_ZERO_INIT("false")
98 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
103 #include "intel_batchbuffer.h"
104 #include "intel_buffers.h"
105 #include "brw_bufmgr.h"
106 #include "intel_fbo.h"
107 #include "intel_mipmap_tree.h"
108 #include "intel_screen.h"
109 #include "intel_tex.h"
110 #include "intel_image.h"
112 #include "brw_context.h"
114 #include "i915_drm.h"
117 * For debugging purposes, this returns a time in seconds.
124 clock_gettime(CLOCK_MONOTONIC
, &tp
);
126 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
129 static const __DRItexBufferExtension intelTexBufferExtension
= {
130 .base
= { __DRI_TEX_BUFFER
, 3 },
132 .setTexBuffer
= intelSetTexBuffer
,
133 .setTexBuffer2
= intelSetTexBuffer2
,
134 .releaseTexBuffer
= intelReleaseTexBuffer
,
138 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
139 __DRIdrawable
*dPriv
,
141 enum __DRI2throttleReason reason
)
143 struct brw_context
*brw
= cPriv
->driverPrivate
;
148 struct gl_context
*ctx
= &brw
->ctx
;
150 FLUSH_VERTICES(ctx
, 0);
152 if (flags
& __DRI2_FLUSH_DRAWABLE
)
153 intel_resolve_for_dri2_flush(brw
, dPriv
);
155 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
156 brw
->need_swap_throttle
= true;
157 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
158 brw
->need_flush_throttle
= true;
160 intel_batchbuffer_flush(brw
);
164 * Provides compatibility with loaders that only support the older (version
165 * 1-3) flush interface.
167 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
170 intel_dri2_flush(__DRIdrawable
*drawable
)
172 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
173 __DRI2_FLUSH_DRAWABLE
,
174 __DRI2_THROTTLE_SWAPBUFFER
);
177 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
178 .base
= { __DRI2_FLUSH
, 4 },
180 .flush
= intel_dri2_flush
,
181 .invalidate
= dri2InvalidateDrawable
,
182 .flush_with_flags
= intel_dri2_flush_with_flags
,
185 static const struct intel_image_format intel_image_formats
[] = {
186 { __DRI_IMAGE_FOURCC_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
187 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
189 { __DRI_IMAGE_FOURCC_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
190 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
192 { __DRI_IMAGE_FOURCC_ABGR2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
193 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010
, 4 } } },
195 { __DRI_IMAGE_FOURCC_XBGR2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010
, 4 } } },
198 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
201 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
204 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
207 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
210 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
213 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
216 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
219 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
222 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
225 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
226 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
228 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
229 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
231 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
233 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
234 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
236 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
241 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
246 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
251 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
256 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
261 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
266 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
267 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
271 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
272 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
273 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
276 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
279 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
281 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
282 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
283 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
285 { __DRI_IMAGE_FOURCC_P010
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
286 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
287 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } , 65535.0f
/1023.0f
},
289 { __DRI_IMAGE_FOURCC_P012
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
290 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
291 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } , 65535.0f
/4095.0f
},
293 { __DRI_IMAGE_FOURCC_P016
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
294 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
295 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
297 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
298 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
299 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
301 { __DRI_IMAGE_FOURCC_AYUV
, __DRI_IMAGE_COMPONENTS_AYUV
, 1,
302 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
304 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
305 * and treat them as planar buffers in the compositors.
306 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
307 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
308 * clusters and places pairs and places U into the G component and
309 * V into A. This lets the texture sampler interpolate the Y
310 * components correctly when sampling from plane 0, and interpolate
311 * U and V correctly when sampling from plane 1. */
312 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
313 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
314 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
315 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
316 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
317 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
320 static const struct {
323 } supported_modifiers
[] = {
324 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
325 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
326 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
327 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
331 modifier_is_supported(const struct gen_device_info
*devinfo
,
332 const struct intel_image_format
*fmt
, int dri_format
,
335 const struct isl_drm_modifier_info
*modinfo
=
336 isl_drm_modifier_get_info(modifier
);
339 /* ISL had better know about the modifier */
343 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
344 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
345 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
348 /* CCS_E is not supported for planar images */
349 if (fmt
&& fmt
->nplanes
> 1)
353 assert(dri_format
== 0);
354 dri_format
= fmt
->planes
[0].dri_format
;
357 mesa_format format
= driImageFormatToGLFormat(dri_format
);
358 /* Whether or not we support compression is based on the RGBA non-sRGB
359 * version of the format.
361 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
362 format
= _mesa_get_srgb_format_linear(format
);
363 if (!isl_format_supports_ccs_e(devinfo
,
364 brw_isl_format_for_mesa_format(format
)))
368 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
369 if (supported_modifiers
[i
].modifier
!= modifier
)
372 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
379 tiling_to_modifier(uint32_t tiling
)
381 static const uint64_t map
[] = {
382 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
383 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
384 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
387 assert(tiling
< ARRAY_SIZE(map
));
393 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
395 uint32_t tiling
, swizzle
;
396 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
398 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
399 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
400 func
, image
->offset
);
404 static const struct intel_image_format
*
405 intel_image_format_lookup(int fourcc
)
407 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
408 if (intel_image_formats
[i
].fourcc
== fourcc
)
409 return &intel_image_formats
[i
];
416 intel_image_get_fourcc(__DRIimage
*image
, int *fourcc
)
418 if (image
->planar_format
) {
419 *fourcc
= image
->planar_format
->fourcc
;
423 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
424 if (intel_image_formats
[i
].planes
[0].dri_format
== image
->dri_format
) {
425 *fourcc
= intel_image_formats
[i
].fourcc
;
433 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
438 image
= calloc(1, sizeof *image
);
442 image
->screen
= screen
;
443 image
->dri_format
= dri_format
;
446 image
->format
= driImageFormatToGLFormat(dri_format
);
447 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
448 image
->format
== MESA_FORMAT_NONE
) {
453 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
454 image
->data
= loaderPrivate
;
460 * Sets up a DRIImage structure to point to a slice out of a miptree.
463 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
464 struct intel_mipmap_tree
*mt
, GLuint level
,
467 intel_miptree_make_shareable(brw
, mt
);
469 intel_miptree_check_level_layer(mt
, level
, zoffset
);
471 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
472 level
- mt
->first_level
);
473 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
474 level
- mt
->first_level
);
475 image
->pitch
= mt
->surf
.row_pitch_B
;
477 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
481 brw_bo_unreference(image
->bo
);
483 brw_bo_reference(mt
->bo
);
487 intel_create_image_from_name(__DRIscreen
*dri_screen
,
488 int width
, int height
, int format
,
489 int name
, int pitch
, void *loaderPrivate
)
491 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
495 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
499 if (image
->format
== MESA_FORMAT_NONE
)
502 cpp
= _mesa_get_format_bytes(image
->format
);
504 image
->width
= width
;
505 image
->height
= height
;
506 image
->pitch
= pitch
* cpp
;
507 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
513 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
519 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
520 int renderbuffer
, void *loaderPrivate
)
523 struct brw_context
*brw
= context
->driverPrivate
;
524 struct gl_context
*ctx
= &brw
->ctx
;
525 struct gl_renderbuffer
*rb
;
526 struct intel_renderbuffer
*irb
;
528 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
530 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
534 irb
= intel_renderbuffer(rb
);
535 intel_miptree_make_shareable(brw
, irb
->mt
);
536 image
= calloc(1, sizeof *image
);
540 image
->internal_format
= rb
->InternalFormat
;
541 image
->format
= rb
->Format
;
542 image
->modifier
= tiling_to_modifier(
543 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
545 image
->data
= loaderPrivate
;
546 brw_bo_unreference(image
->bo
);
547 image
->bo
= irb
->mt
->bo
;
548 brw_bo_reference(irb
->mt
->bo
);
549 image
->width
= rb
->Width
;
550 image
->height
= rb
->Height
;
551 image
->pitch
= irb
->mt
->surf
.row_pitch_B
;
552 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
553 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
555 rb
->NeedsFinishRenderTexture
= true;
560 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
561 unsigned texture
, int zoffset
,
567 struct brw_context
*brw
= context
->driverPrivate
;
568 struct gl_texture_object
*obj
;
569 struct intel_texture_object
*iobj
;
572 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
573 if (!obj
|| obj
->Target
!= target
) {
574 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
578 if (target
== GL_TEXTURE_CUBE_MAP
)
581 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
582 iobj
= intel_texture_object(obj
);
583 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
584 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
588 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
589 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
593 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
594 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
597 image
= calloc(1, sizeof *image
);
599 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
603 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
604 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
605 image
->modifier
= tiling_to_modifier(
606 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
607 image
->data
= loaderPrivate
;
608 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
609 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
610 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
611 image
->planar_format
= iobj
->planar_format
;
612 if (image
->dri_format
== __DRI_IMAGE_FORMAT_NONE
) {
613 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
618 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
623 intel_destroy_image(__DRIimage
*image
)
625 brw_bo_unreference(image
->bo
);
629 enum modifier_priority
{
630 MODIFIER_PRIORITY_INVALID
= 0,
631 MODIFIER_PRIORITY_LINEAR
,
634 MODIFIER_PRIORITY_Y_CCS
,
637 const uint64_t priority_to_modifier
[] = {
638 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
639 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
640 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
641 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
642 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
646 select_best_modifier(struct gen_device_info
*devinfo
,
648 const uint64_t *modifiers
,
649 const unsigned count
)
651 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
653 for (int i
= 0; i
< count
; i
++) {
654 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
657 switch (modifiers
[i
]) {
658 case I915_FORMAT_MOD_Y_TILED_CCS
:
659 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
661 case I915_FORMAT_MOD_Y_TILED
:
662 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
664 case I915_FORMAT_MOD_X_TILED
:
665 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
667 case DRM_FORMAT_MOD_LINEAR
:
668 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
670 case DRM_FORMAT_MOD_INVALID
:
676 return priority_to_modifier
[prio
];
680 intel_create_image_common(__DRIscreen
*dri_screen
,
681 int width
, int height
, int format
,
683 const uint64_t *modifiers
,
688 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
689 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
692 /* Callers of this may specify a modifier, or a dri usage, but not both. The
693 * newer modifier interface deprecates the older usage flags newer modifier
694 * interface deprecates the older usage flags.
696 assert(!(use
&& count
));
698 if (use
& __DRI_IMAGE_USE_CURSOR
) {
699 if (width
!= 64 || height
!= 64)
701 modifier
= DRM_FORMAT_MOD_LINEAR
;
704 if (use
& __DRI_IMAGE_USE_LINEAR
)
705 modifier
= DRM_FORMAT_MOD_LINEAR
;
707 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
709 /* User requested specific modifiers */
710 modifier
= select_best_modifier(&screen
->devinfo
, format
,
712 if (modifier
== DRM_FORMAT_MOD_INVALID
)
715 /* Historically, X-tiled was the default, and so lack of modifier means
718 modifier
= I915_FORMAT_MOD_X_TILED
;
722 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
726 const struct isl_drm_modifier_info
*mod_info
=
727 isl_drm_modifier_get_info(modifier
);
729 struct isl_surf surf
;
730 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
731 .dim
= ISL_SURF_DIM_2D
,
732 .format
= brw_isl_format_for_mesa_format(image
->format
),
739 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
740 ISL_SURF_USAGE_TEXTURE_BIT
|
741 ISL_SURF_USAGE_STORAGE_BIT
,
742 .tiling_flags
= (1 << mod_info
->tiling
));
749 struct isl_surf aux_surf
;
750 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
751 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, 0);
757 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
761 /* We request that the bufmgr zero the buffer for us for two reasons:
763 * 1) If a buffer gets re-used from the pool, we don't want to leak random
764 * garbage from our process to some other.
766 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
767 * a valid state. A CCS value of 0 indicates that the given block is
768 * in the pass-through state which is what we want.
770 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
771 surf
.size_B
+ aux_surf
.size_B
,
773 isl_tiling_to_i915_tiling(mod_info
->tiling
),
774 surf
.row_pitch_B
, BO_ALLOC_ZEROED
);
775 if (image
->bo
== NULL
) {
779 image
->width
= width
;
780 image
->height
= height
;
781 image
->pitch
= surf
.row_pitch_B
;
782 image
->modifier
= modifier
;
784 if (aux_surf
.size_B
) {
785 image
->aux_offset
= surf
.size_B
;
786 image
->aux_pitch
= aux_surf
.row_pitch_B
;
787 image
->aux_size
= aux_surf
.size_B
;
794 intel_create_image(__DRIscreen
*dri_screen
,
795 int width
, int height
, int format
,
799 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
804 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
805 int x0
, int y0
, int width
, int height
,
806 unsigned int flags
, int *stride
, void **map_info
)
808 struct brw_context
*brw
= NULL
;
809 struct brw_bo
*bo
= NULL
;
810 void *raw_data
= NULL
;
815 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
818 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
821 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
824 if (flags
& MAP_INTERNAL_MASK
)
827 brw
= context
->driverPrivate
;
833 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
834 raw_data
= brw_bo_map(brw
, bo
, flags
);
838 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
839 pix_bytes
= _mesa_get_format_bytes(image
->format
);
843 assert(pix_bytes
> 0);
845 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
847 brw_bo_reference(bo
);
849 *stride
= image
->pitch
;
856 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
858 struct brw_bo
*bo
= map_info
;
861 brw_bo_unreference(bo
);
865 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
866 int width
, int height
, int format
,
867 const uint64_t *modifiers
,
868 const unsigned count
,
871 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
872 modifiers
, count
, loaderPrivate
);
876 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
879 case __DRI_IMAGE_ATTRIB_STRIDE
:
880 *value
= image
->pitch
;
882 case __DRI_IMAGE_ATTRIB_HANDLE
:
883 *value
= brw_bo_export_gem_handle(image
->bo
);
885 case __DRI_IMAGE_ATTRIB_NAME
:
886 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
887 case __DRI_IMAGE_ATTRIB_FORMAT
:
888 *value
= image
->dri_format
;
890 case __DRI_IMAGE_ATTRIB_WIDTH
:
891 *value
= image
->width
;
893 case __DRI_IMAGE_ATTRIB_HEIGHT
:
894 *value
= image
->height
;
896 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
897 if (image
->planar_format
== NULL
)
899 *value
= image
->planar_format
->components
;
901 case __DRI_IMAGE_ATTRIB_FD
:
902 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
903 case __DRI_IMAGE_ATTRIB_FOURCC
:
904 return intel_image_get_fourcc(image
, value
);
905 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
906 if (isl_drm_modifier_has_aux(image
->modifier
)) {
907 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
909 } else if (image
->planar_format
) {
910 *value
= image
->planar_format
->nplanes
;
915 case __DRI_IMAGE_ATTRIB_OFFSET
:
916 *value
= image
->offset
;
918 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
919 *value
= (image
->modifier
& 0xffffffff);
921 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
922 *value
= ((image
->modifier
>> 32) & 0xffffffff);
931 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
932 uint32_t fourcc
, uint64_t modifier
,
933 int attrib
, uint64_t *value
)
935 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
936 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
938 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
942 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
943 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
952 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
956 image
= calloc(1, sizeof *image
);
960 brw_bo_reference(orig_image
->bo
);
961 image
->bo
= orig_image
->bo
;
962 image
->internal_format
= orig_image
->internal_format
;
963 image
->planar_format
= orig_image
->planar_format
;
964 image
->dri_format
= orig_image
->dri_format
;
965 image
->format
= orig_image
->format
;
966 image
->modifier
= orig_image
->modifier
;
967 image
->offset
= orig_image
->offset
;
968 image
->width
= orig_image
->width
;
969 image
->height
= orig_image
->height
;
970 image
->pitch
= orig_image
->pitch
;
971 image
->tile_x
= orig_image
->tile_x
;
972 image
->tile_y
= orig_image
->tile_y
;
973 image
->has_depthstencil
= orig_image
->has_depthstencil
;
974 image
->data
= loaderPrivate
;
975 image
->aux_offset
= orig_image
->aux_offset
;
976 image
->aux_pitch
= orig_image
->aux_pitch
;
978 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
979 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
985 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
987 if (use
& __DRI_IMAGE_USE_CURSOR
) {
988 if (image
->width
!= 64 || image
->height
!= 64)
996 intel_create_image_from_names(__DRIscreen
*dri_screen
,
997 int width
, int height
, int fourcc
,
998 int *names
, int num_names
,
999 int *strides
, int *offsets
,
1000 void *loaderPrivate
)
1002 const struct intel_image_format
*f
= NULL
;
1006 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
1009 f
= intel_image_format_lookup(fourcc
);
1013 image
= intel_create_image_from_name(dri_screen
, width
, height
,
1014 __DRI_IMAGE_FORMAT_NONE
,
1015 names
[0], strides
[0],
1021 image
->planar_format
= f
;
1022 for (i
= 0; i
< f
->nplanes
; i
++) {
1023 index
= f
->planes
[i
].buffer_index
;
1024 image
->offsets
[index
] = offsets
[index
];
1025 image
->strides
[index
] = strides
[index
];
1032 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1033 int width
, int height
, int fourcc
,
1034 uint64_t modifier
, int *fds
, int num_fds
,
1035 int *strides
, int *offsets
,
1036 void *loaderPrivate
)
1038 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1039 const struct intel_image_format
*f
;
1044 if (fds
== NULL
|| num_fds
< 1)
1047 f
= intel_image_format_lookup(fourcc
);
1051 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1052 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1055 if (f
->nplanes
== 1)
1056 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1059 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1065 image
->width
= width
;
1066 image
->height
= height
;
1067 image
->pitch
= strides
[0];
1069 image
->planar_format
= f
;
1071 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1072 const struct isl_drm_modifier_info
*mod_info
=
1073 isl_drm_modifier_get_info(modifier
);
1074 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1075 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1076 tiling
, strides
[0]);
1078 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1081 if (image
->bo
== NULL
) {
1086 /* We only support all planes from the same bo.
1087 * brw_bo_gem_create_from_prime() should return the same pointer for all
1088 * fds received here */
1089 for (i
= 1; i
< num_fds
; i
++) {
1090 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1091 brw_bo_unreference(aux
);
1092 if (aux
!= image
->bo
) {
1093 brw_bo_unreference(image
->bo
);
1099 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1100 image
->modifier
= modifier
;
1102 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1104 const struct isl_drm_modifier_info
*mod_info
=
1105 isl_drm_modifier_get_info(image
->modifier
);
1108 struct isl_surf surf
;
1109 for (i
= 0; i
< f
->nplanes
; i
++) {
1110 index
= f
->planes
[i
].buffer_index
;
1111 image
->offsets
[index
] = offsets
[index
];
1112 image
->strides
[index
] = strides
[index
];
1114 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1115 /* The images we will create are actually based on the RGBA non-sRGB
1116 * version of the format.
1118 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1119 format
= _mesa_get_srgb_format_linear(format
);
1121 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1122 .dim
= ISL_SURF_DIM_2D
,
1123 .format
= brw_isl_format_for_mesa_format(format
),
1124 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1125 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1130 .row_pitch_B
= strides
[index
],
1131 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1132 ISL_SURF_USAGE_TEXTURE_BIT
|
1133 ISL_SURF_USAGE_STORAGE_BIT
,
1134 .tiling_flags
= (1 << mod_info
->tiling
));
1136 brw_bo_unreference(image
->bo
);
1141 const int end
= offsets
[index
] + surf
.size_B
;
1146 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1147 /* Even though we initialize surf in the loop above, we know that
1148 * anything with CCS_E will have exactly one plane so surf is properly
1149 * initialized when we get here.
1151 assert(f
->nplanes
== 1);
1153 image
->aux_offset
= offsets
[1];
1154 image
->aux_pitch
= strides
[1];
1156 /* Scanout hardware requires that the CCS be placed after the main
1157 * surface in memory. We consider any CCS that is placed any earlier in
1158 * memory to be invalid and reject it.
1160 * At some point in the future, this restriction may be relaxed if the
1161 * hardware becomes less strict but we may need a new modifier for that.
1164 if (image
->aux_offset
< size
) {
1165 brw_bo_unreference(image
->bo
);
1170 struct isl_surf aux_surf
;
1171 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
,
1174 brw_bo_unreference(image
->bo
);
1179 image
->aux_size
= aux_surf
.size_B
;
1181 const int end
= image
->aux_offset
+ aux_surf
.size_B
;
1185 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1188 /* Check that the requested image actually fits within the BO. 'size'
1189 * is already relative to the offsets, so we don't need to add that. */
1190 if (image
->bo
->size
== 0) {
1191 image
->bo
->size
= size
;
1192 } else if (size
> image
->bo
->size
) {
1193 brw_bo_unreference(image
->bo
);
1198 if (f
->nplanes
== 1) {
1199 image
->offset
= image
->offsets
[0];
1200 intel_image_warn_if_unaligned(image
, __func__
);
1207 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1208 int width
, int height
, int fourcc
,
1209 int *fds
, int num_fds
, int *strides
, int *offsets
,
1210 void *loaderPrivate
)
1212 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1213 DRM_FORMAT_MOD_INVALID
,
1214 fds
, num_fds
, strides
, offsets
,
1219 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1220 int width
, int height
,
1221 int fourcc
, uint64_t modifier
,
1222 int *fds
, int num_fds
,
1223 int *strides
, int *offsets
,
1224 enum __DRIYUVColorSpace yuv_color_space
,
1225 enum __DRISampleRange sample_range
,
1226 enum __DRIChromaSiting horizontal_siting
,
1227 enum __DRIChromaSiting vertical_siting
,
1229 void *loaderPrivate
)
1232 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1235 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1239 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1241 fds
, num_fds
, strides
, offsets
,
1245 * Invalid parameters and any inconsistencies between are assumed to be
1246 * checked by the caller. Therefore besides unsupported formats one can fail
1247 * only in allocation.
1250 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1254 image
->yuv_color_space
= yuv_color_space
;
1255 image
->sample_range
= sample_range
;
1256 image
->horizontal_siting
= horizontal_siting
;
1257 image
->vertical_siting
= vertical_siting
;
1259 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1264 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1265 int width
, int height
, int fourcc
,
1266 int *fds
, int num_fds
,
1267 int *strides
, int *offsets
,
1268 enum __DRIYUVColorSpace yuv_color_space
,
1269 enum __DRISampleRange sample_range
,
1270 enum __DRIChromaSiting horizontal_siting
,
1271 enum __DRIChromaSiting vertical_siting
,
1273 void *loaderPrivate
)
1275 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1276 fourcc
, DRM_FORMAT_MOD_INVALID
,
1277 fds
, num_fds
, strides
, offsets
,
1287 intel_image_format_is_supported(const struct gen_device_info
*devinfo
,
1288 const struct intel_image_format
*fmt
)
1290 /* Currently, all formats with an intel_image_format are available on all
1291 * platforms so there's really nothing to check there.
1295 if (fmt
->nplanes
== 1) {
1296 mesa_format format
= driImageFormatToGLFormat(fmt
->planes
[0].dri_format
);
1297 /* The images we will create are actually based on the RGBA non-sRGB
1298 * version of the format.
1300 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1301 format
= _mesa_get_srgb_format_linear(format
);
1302 enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
1303 assert(isl_format_supports_rendering(devinfo
, isl_format
));
1311 intel_query_dma_buf_formats(__DRIscreen
*_screen
, int max
,
1312 int *formats
, int *count
)
1314 struct intel_screen
*screen
= _screen
->driverPrivate
;
1315 int num_formats
= 0, i
;
1317 for (i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
1318 /* These two formats are valid DRI formats but do not exist in
1319 * drm_fourcc.h in the Linux kernel. We don't want to accidentally
1320 * advertise them through the EGL layer.
1322 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
||
1323 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SABGR8888
)
1326 if (!intel_image_format_is_supported(&screen
->devinfo
,
1327 &intel_image_formats
[i
]))
1334 formats
[num_formats
- 1] = intel_image_formats
[i
].fourcc
;
1335 if (num_formats
>= max
)
1339 *count
= num_formats
;
1344 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1345 uint64_t *modifiers
,
1346 unsigned int *external_only
,
1349 struct intel_screen
*screen
= _screen
->driverPrivate
;
1350 const struct intel_image_format
*f
;
1351 int num_mods
= 0, i
;
1353 f
= intel_image_format_lookup(fourcc
);
1357 if (!intel_image_format_is_supported(&screen
->devinfo
, f
))
1360 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1361 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1362 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1369 modifiers
[num_mods
- 1] = modifier
;
1370 if (num_mods
>= max
)
1374 if (external_only
!= NULL
) {
1375 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1376 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1377 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1378 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1379 external_only
[i
] = GL_TRUE
;
1382 external_only
[i
] = GL_FALSE
;
1392 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1394 int width
, height
, offset
, stride
, size
, dri_format
;
1400 width
= parent
->width
;
1401 height
= parent
->height
;
1403 const struct intel_image_format
*f
= parent
->planar_format
;
1405 if (f
&& plane
< f
->nplanes
) {
1406 /* Use the planar format definition. */
1407 width
>>= f
->planes
[plane
].width_shift
;
1408 height
>>= f
->planes
[plane
].height_shift
;
1409 dri_format
= f
->planes
[plane
].dri_format
;
1410 int index
= f
->planes
[plane
].buffer_index
;
1411 offset
= parent
->offsets
[index
];
1412 stride
= parent
->strides
[index
];
1413 size
= height
* stride
;
1414 } else if (plane
== 0) {
1415 /* The only plane of a non-planar image: copy the parent definition
1417 dri_format
= parent
->dri_format
;
1418 offset
= parent
->offset
;
1419 stride
= parent
->pitch
;
1420 size
= height
* stride
;
1421 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1422 isl_drm_modifier_has_aux(parent
->modifier
)) {
1423 /* Auxiliary plane */
1424 dri_format
= parent
->dri_format
;
1425 offset
= parent
->aux_offset
;
1426 stride
= parent
->aux_pitch
;
1427 size
= parent
->aux_size
;
1432 if (offset
+ size
> parent
->bo
->size
) {
1433 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1437 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1441 image
->bo
= parent
->bo
;
1442 brw_bo_reference(parent
->bo
);
1443 image
->modifier
= parent
->modifier
;
1445 image
->width
= width
;
1446 image
->height
= height
;
1447 image
->pitch
= stride
;
1448 image
->offset
= offset
;
1450 intel_image_warn_if_unaligned(image
, __func__
);
1455 static const __DRIimageExtension intelImageExtension
= {
1456 .base
= { __DRI_IMAGE
, 16 },
1458 .createImageFromName
= intel_create_image_from_name
,
1459 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1460 .destroyImage
= intel_destroy_image
,
1461 .createImage
= intel_create_image
,
1462 .queryImage
= intel_query_image
,
1463 .dupImage
= intel_dup_image
,
1464 .validateUsage
= intel_validate_usage
,
1465 .createImageFromNames
= intel_create_image_from_names
,
1466 .fromPlanar
= intel_from_planar
,
1467 .createImageFromTexture
= intel_create_image_from_texture
,
1468 .createImageFromFds
= intel_create_image_from_fds
,
1469 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1471 .getCapabilities
= NULL
,
1472 .mapImage
= intel_map_image
,
1473 .unmapImage
= intel_unmap_image
,
1474 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1475 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1476 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1477 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1478 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1482 get_aperture_size(int fd
)
1484 struct drm_i915_gem_get_aperture aperture
;
1486 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1489 return aperture
.aper_size
;
1493 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1494 int param
, unsigned int *value
)
1496 const struct intel_screen
*const screen
=
1497 (struct intel_screen
*) dri_screen
->driverPrivate
;
1500 case __DRI2_RENDERER_VENDOR_ID
:
1503 case __DRI2_RENDERER_DEVICE_ID
:
1504 value
[0] = screen
->deviceID
;
1506 case __DRI2_RENDERER_ACCELERATED
:
1509 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1510 /* Once a batch uses more than 75% of the maximum mappable size, we
1511 * assume that there's some fragmentation, and we start doing extra
1512 * flushing, etc. That's the big cliff apps will care about.
1514 const unsigned gpu_mappable_megabytes
=
1515 screen
->aperture_threshold
/ (1024 * 1024);
1517 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1518 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1520 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1523 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1524 * (uint64_t) system_page_size
;
1526 const unsigned system_memory_megabytes
=
1527 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1529 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1532 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1535 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1538 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1540 if (brw_hw_context_set_priority(screen
->bufmgr
,
1541 0, GEN_CONTEXT_HIGH_PRIORITY
) == 0)
1542 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1543 if (brw_hw_context_set_priority(screen
->bufmgr
,
1544 0, GEN_CONTEXT_LOW_PRIORITY
) == 0)
1545 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1546 /* reset to default last, just in case */
1547 if (brw_hw_context_set_priority(screen
->bufmgr
,
1548 0, GEN_CONTEXT_MEDIUM_PRIORITY
) == 0)
1549 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1551 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1555 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1562 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1563 int param
, const char **value
)
1565 const struct intel_screen
*screen
=
1566 (struct intel_screen
*) dri_screen
->driverPrivate
;
1569 case __DRI2_RENDERER_VENDOR_ID
:
1570 value
[0] = brw_vendor_string
;
1572 case __DRI2_RENDERER_DEVICE_ID
:
1573 value
[0] = brw_get_renderer_string(screen
);
1583 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1584 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1586 const struct intel_screen
*const screen
=
1587 (struct intel_screen
*) dri_screen
->driverPrivate
;
1589 if (!screen
->disk_cache
)
1592 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1595 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1596 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1598 .queryInteger
= brw_query_renderer_integer
,
1599 .queryString
= brw_query_renderer_string
1602 static const __DRIrobustnessExtension dri2Robustness
= {
1603 .base
= { __DRI2_ROBUSTNESS
, 1 }
1606 static const __DRI2blobExtension intelBlobExtension
= {
1607 .base
= { __DRI2_BLOB
, 1 },
1608 .set_cache_funcs
= brw_set_cache_funcs
1611 static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension
= {
1612 .base
= { __DRI_MUTABLE_RENDER_BUFFER_DRIVER
, 1 },
1615 static const __DRIextension
*screenExtensions
[] = {
1616 &intelTexBufferExtension
.base
,
1617 &intelFenceExtension
.base
,
1618 &intelFlushExtension
.base
,
1619 &intelImageExtension
.base
,
1620 &intelRendererQueryExtension
.base
,
1621 &intelMutableRenderBufferExtension
.base
,
1622 &dri2ConfigQueryExtension
.base
,
1623 &dri2NoErrorExtension
.base
,
1624 &intelBlobExtension
.base
,
1628 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1629 &intelTexBufferExtension
.base
,
1630 &intelFenceExtension
.base
,
1631 &intelFlushExtension
.base
,
1632 &intelImageExtension
.base
,
1633 &intelRendererQueryExtension
.base
,
1634 &intelMutableRenderBufferExtension
.base
,
1635 &dri2ConfigQueryExtension
.base
,
1636 &dri2Robustness
.base
,
1637 &dri2NoErrorExtension
.base
,
1638 &intelBlobExtension
.base
,
1643 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1646 struct drm_i915_getparam gp
;
1648 memset(&gp
, 0, sizeof(gp
));
1652 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1655 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1662 intel_get_boolean(struct intel_screen
*screen
, int param
)
1665 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1669 intel_get_integer(struct intel_screen
*screen
, int param
)
1673 if (intel_get_param(screen
, param
, &value
) == 0)
1680 intelDestroyScreen(__DRIscreen
* sPriv
)
1682 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1684 brw_bufmgr_destroy(screen
->bufmgr
);
1685 driDestroyOptionInfo(&screen
->optionCache
);
1687 disk_cache_destroy(screen
->disk_cache
);
1689 ralloc_free(screen
);
1690 sPriv
->driverPrivate
= NULL
;
1695 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1697 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1698 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1699 * this does not allocate GPU memory.
1702 intelCreateBuffer(__DRIscreen
*dri_screen
,
1703 __DRIdrawable
* driDrawPriv
,
1704 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1706 struct intel_renderbuffer
*rb
;
1707 struct intel_screen
*screen
= (struct intel_screen
*)
1708 dri_screen
->driverPrivate
;
1709 mesa_format rgbFormat
;
1710 unsigned num_samples
=
1711 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1716 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1720 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1722 if (screen
->winsys_msaa_samples_override
!= -1) {
1723 num_samples
= screen
->winsys_msaa_samples_override
;
1724 fb
->Visual
.samples
= num_samples
;
1727 if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1728 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1729 : MESA_FORMAT_R10G10B10A2_UNORM
;
1730 } else if (mesaVis
->redBits
== 10) {
1731 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1732 : MESA_FORMAT_R10G10B10X2_UNORM
;
1733 } else if (mesaVis
->redBits
== 5) {
1734 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1735 : MESA_FORMAT_B5G6R5_UNORM
;
1736 } else if (mesaVis
->sRGBCapable
) {
1737 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1738 : MESA_FORMAT_B8G8R8A8_SRGB
;
1739 } else if (mesaVis
->alphaBits
== 0) {
1740 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1741 : MESA_FORMAT_B8G8R8X8_UNORM
;
1743 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1744 : MESA_FORMAT_B8G8R8A8_SRGB
;
1745 fb
->Visual
.sRGBCapable
= true;
1748 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1749 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1751 /* setup the hardware-based renderbuffers */
1752 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1753 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1754 rb
->need_srgb
= srgb_cap_set
;
1756 if (mesaVis
->doubleBufferMode
) {
1757 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1758 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1759 rb
->need_srgb
= srgb_cap_set
;
1763 * Assert here that the gl_config has an expected depth/stencil bit
1764 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1765 * which constructs the advertised configs.)
1767 if (mesaVis
->depthBits
== 24) {
1768 assert(mesaVis
->stencilBits
== 8);
1770 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1771 rb
= intel_create_private_renderbuffer(screen
,
1772 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1774 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1775 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1777 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1780 * Use combined depth/stencil. Note that the renderbuffer is
1781 * attached to two attachment points.
1783 rb
= intel_create_private_renderbuffer(screen
,
1784 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1786 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1787 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1790 else if (mesaVis
->depthBits
== 16) {
1791 assert(mesaVis
->stencilBits
== 0);
1792 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1794 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1797 assert(mesaVis
->depthBits
== 0);
1798 assert(mesaVis
->stencilBits
== 0);
1801 /* now add any/all software-based renderbuffers we may need */
1802 _swrast_add_soft_renderbuffers(fb
,
1803 false, /* never sw color */
1804 false, /* never sw depth */
1805 false, /* never sw stencil */
1806 mesaVis
->accumRedBits
> 0,
1807 false, /* never sw alpha */
1808 false /* never sw aux */ );
1809 driDrawPriv
->driverPrivate
= fb
;
1815 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1817 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1819 _mesa_reference_framebuffer(&fb
, NULL
);
1823 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1825 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1826 * gen10, PCI-id is enough to figure it out.
1828 assert(screen
->devinfo
.gen
>= 10);
1832 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1836 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1840 screen
->devinfo
.timestamp_frequency
= freq
;
1844 intel_detect_sseu(struct intel_screen
*screen
)
1846 assert(screen
->devinfo
.gen
>= 8);
1849 screen
->subslice_total
= -1;
1850 screen
->eu_total
= -1;
1852 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1853 &screen
->subslice_total
);
1854 if (ret
< 0 && ret
!= -EINVAL
)
1857 ret
= intel_get_param(screen
,
1858 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1859 if (ret
< 0 && ret
!= -EINVAL
)
1862 /* Without this information, we cannot get the right Braswell brandstrings,
1863 * and we have to use conservative numbers for GPGPU on many platforms, but
1864 * otherwise, things will just work.
1866 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1868 "Kernel 4.1 required to properly query GPU properties.\n");
1873 screen
->subslice_total
= -1;
1874 screen
->eu_total
= -1;
1875 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1879 intel_init_bufmgr(struct intel_screen
*screen
)
1881 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1883 if (getenv("INTEL_NO_HW") != NULL
)
1884 screen
->no_hw
= true;
1886 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
);
1887 if (screen
->bufmgr
== NULL
) {
1888 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1889 __func__
, __LINE__
);
1893 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1894 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1902 intel_detect_swizzling(struct intel_screen
*screen
)
1904 /* Broadwell PRM says:
1906 * "Before Gen8, there was a historical configuration control field to
1907 * swizzle address bit[6] for in X/Y tiling modes. This was set in three
1908 * different places: TILECTL[1:0], ARB_MODE[5:4], and
1909 * DISP_ARB_CTL[14:13].
1911 * For Gen8 and subsequent generations, the swizzle fields are all
1912 * reserved, and the CPU's memory controller performs all address
1913 * swizzling modifications."
1915 if (screen
->devinfo
.gen
>= 8)
1918 uint32_t tiling
= I915_TILING_X
;
1919 uint32_t swizzle_mode
= 0;
1920 struct brw_bo
*buffer
=
1921 brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test", 32768,
1922 BRW_MEMZONE_OTHER
, tiling
, 512, 0);
1926 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1927 brw_bo_unreference(buffer
);
1929 return swizzle_mode
!= I915_BIT_6_SWIZZLE_NONE
;
1933 intel_detect_timestamp(struct intel_screen
*screen
)
1935 uint64_t dummy
= 0, last
= 0;
1936 int upper
, lower
, loops
;
1938 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1939 * TIMESTAMP register being shifted and the low 32bits always zero.
1941 * More recent kernels offer an interface to read the full 36bits
1944 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1947 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1948 * upper 32bits for a rapidly changing timestamp.
1950 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1954 for (loops
= 0; loops
< 10; loops
++) {
1955 /* The TIMESTAMP should change every 80ns, so several round trips
1956 * through the kernel should be enough to advance it.
1958 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1961 upper
+= (dummy
>> 32) != (last
>> 32);
1962 if (upper
> 1) /* beware 32bit counter overflow */
1963 return 2; /* upper dword holds the low 32bits of the timestamp */
1965 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1967 return 1; /* timestamp is unshifted */
1972 /* No advancement? No timestamp! */
1977 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1979 * Some combinations of hardware and kernel versions allow this feature,
1980 * while others don't. Instead of trying to enumerate every case, just
1981 * try and write a register and see if works.
1984 intel_detect_pipelined_register(struct intel_screen
*screen
,
1985 int reg
, uint32_t expected_value
, bool reset
)
1990 struct brw_bo
*results
, *bo
;
1992 uint32_t offset
= 0;
1994 bool success
= false;
1996 /* Create a zero'ed temporary buffer for reading our results */
1997 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, BRW_MEMZONE_OTHER
);
1998 if (results
== NULL
)
2001 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, BRW_MEMZONE_OTHER
);
2005 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
2011 /* Write the register. */
2012 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2014 *batch
++ = expected_value
;
2016 /* Save the register's value back to the buffer. */
2017 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
2019 struct drm_i915_gem_relocation_entry reloc
= {
2020 .offset
= (char *) batch
- (char *) map
,
2021 .delta
= offset
* sizeof(uint32_t),
2022 .target_handle
= results
->gem_handle
,
2023 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
2024 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
2026 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
2028 /* And afterwards clear the register */
2030 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2035 *batch
++ = MI_BATCH_BUFFER_END
;
2037 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
2039 .handle
= results
->gem_handle
,
2042 .handle
= bo
->gem_handle
,
2043 .relocation_count
= 1,
2044 .relocs_ptr
= (uintptr_t) &reloc
,
2048 struct drm_i915_gem_execbuffer2 execbuf
= {
2049 .buffers_ptr
= (uintptr_t) exec_objects
,
2051 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
2052 .flags
= I915_EXEC_RENDER
,
2055 /* Don't bother with error checking - if the execbuf fails, the
2056 * value won't be written and we'll just report that there's no access.
2058 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2059 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
2061 /* Check whether the value got written. */
2062 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
2064 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
2065 brw_bo_unmap(results
);
2069 brw_bo_unreference(bo
);
2071 brw_bo_unreference(results
);
2077 intel_detect_pipelined_so(struct intel_screen
*screen
)
2079 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2081 /* Supposedly, Broadwell just works. */
2082 if (devinfo
->gen
>= 8)
2085 if (devinfo
->gen
<= 6)
2088 /* See the big explanation about command parser versions below */
2089 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2092 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2093 * statistics registers), and we already reset it to zero before using it.
2095 return intel_detect_pipelined_register(screen
,
2096 GEN7_SO_WRITE_OFFSET(0),
2102 * Return array of MSAA modes supported by the hardware. The array is
2103 * zero-terminated and sorted in decreasing order.
2106 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2108 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2109 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2110 static const int gen7_modes
[] = {8, 4, 0, -1};
2111 static const int gen6_modes
[] = {4, 0, -1};
2112 static const int gen4_modes
[] = {0, -1};
2114 if (screen
->devinfo
.gen
>= 9) {
2116 } else if (screen
->devinfo
.gen
>= 8) {
2118 } else if (screen
->devinfo
.gen
>= 7) {
2120 } else if (screen
->devinfo
.gen
== 6) {
2128 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2130 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2131 dri_screen
->dri2
.loader
->getCapability
)
2132 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2134 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2135 dri_screen
->image
.loader
->getCapability
)
2136 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2141 static __DRIconfig
**
2142 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2144 static const mesa_format formats
[] = {
2145 MESA_FORMAT_B5G6R5_UNORM
,
2146 MESA_FORMAT_B8G8R8A8_UNORM
,
2147 MESA_FORMAT_B8G8R8X8_UNORM
,
2149 MESA_FORMAT_B8G8R8A8_SRGB
,
2151 /* For 10 bpc, 30 bit depth framebuffers. */
2152 MESA_FORMAT_B10G10R10A2_UNORM
,
2153 MESA_FORMAT_B10G10R10X2_UNORM
,
2155 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2156 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2157 * server may disagree on which format the GLXFBConfig represents,
2158 * resulting in swapped color channels.
2160 * The problem, as of 2017-05-30:
2161 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2162 * order and chooses the first __DRIconfig with the expected channel
2163 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2164 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2166 * EGL does not suffer from this problem. It correctly compares the
2167 * channel masks when matching EGLConfig to __DRIconfig.
2170 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2171 MESA_FORMAT_R8G8B8A8_UNORM
,
2173 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2174 MESA_FORMAT_R8G8B8X8_UNORM
,
2176 MESA_FORMAT_R8G8B8A8_SRGB
,
2179 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
2180 static const GLenum back_buffer_modes
[] = {
2181 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2184 static const uint8_t singlesample_samples
[1] = {0};
2186 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2187 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2188 uint8_t depth_bits
[4], stencil_bits
[4];
2189 __DRIconfig
**configs
= NULL
;
2191 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2192 unsigned num_formats
;
2193 if (intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
))
2194 num_formats
= ARRAY_SIZE(formats
);
2196 num_formats
= ARRAY_SIZE(formats
) - 3; /* all - RGBA_ORDERING formats */
2198 /* Shall we expose 10 bpc formats? */
2199 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2200 "allow_rgb10_configs");
2202 /* Generate singlesample configs, each without accumulation buffer
2203 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
2205 for (unsigned i
= 0; i
< num_formats
; i
++) {
2206 __DRIconfig
**new_configs
;
2207 int num_depth_stencil_bits
= 2;
2209 if (!allow_rgb10_configs
&&
2210 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2211 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2214 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2215 * buffer that has a different number of bits per pixel than the color
2216 * buffer, gen >= 6 supports this.
2219 stencil_bits
[0] = 0;
2221 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2223 stencil_bits
[1] = 0;
2224 if (devinfo
->gen
>= 6) {
2226 stencil_bits
[2] = 8;
2227 num_depth_stencil_bits
= 3;
2231 stencil_bits
[1] = 8;
2234 new_configs
= driCreateConfigs(formats
[i
],
2237 num_depth_stencil_bits
,
2238 back_buffer_modes
, 2,
2239 singlesample_samples
, 1,
2241 /*mutable_render_buffer*/ true);
2242 configs
= driConcatConfigs(configs
, new_configs
);
2245 /* Generate the minimum possible set of configs that include an
2246 * accumulation buffer.
2248 for (unsigned i
= 0; i
< num_formats
; i
++) {
2249 __DRIconfig
**new_configs
;
2251 if (!allow_rgb10_configs
&&
2252 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2253 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2256 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2258 stencil_bits
[0] = 0;
2261 stencil_bits
[0] = 8;
2264 new_configs
= driCreateConfigs(formats
[i
],
2265 depth_bits
, stencil_bits
, 1,
2266 back_buffer_modes
, 1,
2267 singlesample_samples
, 1,
2268 true, false, false);
2269 configs
= driConcatConfigs(configs
, new_configs
);
2272 /* Generate multisample configs.
2274 * This loop breaks early, and hence is a no-op, on gen < 6.
2276 * Multisample configs must follow the singlesample configs in order to
2277 * work around an X server bug present in 1.12. The X server chooses to
2278 * associate the first listed RGBA888-Z24S8 config, regardless of its
2279 * sample count, with the 32-bit depth visual used for compositing.
2281 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2282 * supported. Singlebuffer configs are not supported because no one wants
2285 for (unsigned i
= 0; i
< num_formats
; i
++) {
2286 if (devinfo
->gen
< 6)
2289 if (!allow_rgb10_configs
&&
2290 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2291 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2294 __DRIconfig
**new_configs
;
2295 const int num_depth_stencil_bits
= 2;
2296 int num_msaa_modes
= 0;
2297 const uint8_t *multisample_samples
= NULL
;
2300 stencil_bits
[0] = 0;
2302 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2304 stencil_bits
[1] = 0;
2307 stencil_bits
[1] = 8;
2310 if (devinfo
->gen
>= 9) {
2311 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2312 multisample_samples
= multisample_samples_gen9
;
2313 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2314 } else if (devinfo
->gen
== 8) {
2315 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2316 multisample_samples
= multisample_samples_gen8
;
2317 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2318 } else if (devinfo
->gen
== 7) {
2319 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2320 multisample_samples
= multisample_samples_gen7
;
2321 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2322 } else if (devinfo
->gen
== 6) {
2323 static const uint8_t multisample_samples_gen6
[] = {4};
2324 multisample_samples
= multisample_samples_gen6
;
2325 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2328 new_configs
= driCreateConfigs(formats
[i
],
2331 num_depth_stencil_bits
,
2332 back_buffer_modes
, 1,
2333 multisample_samples
,
2335 false, false, false);
2336 configs
= driConcatConfigs(configs
, new_configs
);
2339 if (configs
== NULL
) {
2340 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2349 set_max_gl_versions(struct intel_screen
*screen
)
2351 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2352 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2354 switch (screen
->devinfo
.gen
) {
2359 dri_screen
->max_gl_core_version
= 45;
2360 dri_screen
->max_gl_compat_version
= 30;
2361 dri_screen
->max_gl_es1_version
= 11;
2362 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2365 dri_screen
->max_gl_core_version
= 33;
2366 if (can_do_pipelined_register_writes(screen
)) {
2367 dri_screen
->max_gl_core_version
= 42;
2368 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2369 dri_screen
->max_gl_core_version
= 43;
2370 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2371 dri_screen
->max_gl_core_version
= 45;
2373 dri_screen
->max_gl_compat_version
= 30;
2374 dri_screen
->max_gl_es1_version
= 11;
2375 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2378 dri_screen
->max_gl_core_version
= 33;
2379 dri_screen
->max_gl_compat_version
= 30;
2380 dri_screen
->max_gl_es1_version
= 11;
2381 dri_screen
->max_gl_es2_version
= 30;
2385 dri_screen
->max_gl_core_version
= 0;
2386 dri_screen
->max_gl_compat_version
= 21;
2387 dri_screen
->max_gl_es1_version
= 11;
2388 dri_screen
->max_gl_es2_version
= 20;
2391 unreachable("unrecognized intel_screen::gen");
2396 * Return the revision (generally the revid field of the PCI header) of the
2400 intel_device_get_revision(int fd
)
2402 struct drm_i915_getparam gp
;
2406 memset(&gp
, 0, sizeof(gp
));
2407 gp
.param
= I915_PARAM_REVISION
;
2408 gp
.value
= &revision
;
2410 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
2418 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2420 struct brw_context
*brw
= (struct brw_context
*)data
;
2423 va_start(args
, fmt
);
2425 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2426 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2427 MESA_DEBUG_TYPE_OTHER
,
2428 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2433 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2435 struct brw_context
*brw
= (struct brw_context
*)data
;
2438 va_start(args
, fmt
);
2440 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2442 va_copy(args_copy
, args
);
2443 vfprintf(stderr
, fmt
, args_copy
);
2447 if (brw
->perf_debug
) {
2449 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2450 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2451 MESA_DEBUG_TYPE_PERFORMANCE
,
2452 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2458 * This is the driver specific part of the createNewScreen entry point.
2459 * Called when using DRI2.
2461 * \return the struct gl_config supported by this driver
2464 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2466 struct intel_screen
*screen
;
2468 if (dri_screen
->image
.loader
) {
2469 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2470 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2472 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2473 "support required\n");
2477 /* Allocate the private area */
2478 screen
= rzalloc(NULL
, struct intel_screen
);
2480 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2483 /* parse information in __driConfigOptions */
2484 driOptionCache options
;
2485 memset(&options
, 0, sizeof(options
));
2487 driParseOptionInfo(&options
, brw_config_options
.xml
);
2488 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
,
2490 driDestroyOptionCache(&options
);
2492 screen
->driScrnPriv
= dri_screen
;
2493 dri_screen
->driverPrivate
= (void *) screen
;
2495 screen
->deviceID
= gen_get_pci_device_id_override();
2496 if (screen
->deviceID
< 0)
2497 screen
->deviceID
= intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2499 screen
->no_hw
= true;
2501 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2504 if (!intel_init_bufmgr(screen
))
2507 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2509 brw_process_intel_debug_variable();
2511 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2513 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2514 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2517 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2518 /* Theorectically unlimited! At least for individual objects...
2520 * Currently the entire (global) address space for all GTT maps is
2521 * limited to 64bits. That is all objects on the system that are
2522 * setup for GTT mmapping must fit within 64bits. An attempt to use
2523 * one that exceeds the limit with fail in brw_bo_map_gtt().
2525 * Long before we hit that limit, we will be practically limited by
2526 * that any single object must fit in physical memory (RAM). The upper
2527 * limit on the CPU's address space is currently 48bits (Skylake), of
2528 * which only 39bits can be physical memory. (The GPU itself also has
2529 * a 48bit addressable virtual space.) We can fit over 32 million
2530 * objects of the current maximum allocable size before running out
2533 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2535 /* Estimate the size of the mappable aperture into the GTT. There's an
2536 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2537 * It turns out it's basically always 256MB, though some ancient hardware
2540 uint32_t gtt_size
= 256 * 1024 * 1024;
2542 /* We don't want to map two objects such that a memcpy between them would
2543 * just fault one mapping in and then the other over and over forever. So
2544 * we would need to divide the GTT size by 2. Additionally, some GTT is
2545 * taken up by things like the framebuffer and the ringbuffer and such, so
2546 * be more conservative.
2548 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2551 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2553 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2554 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2556 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2557 screen
->hw_has_swizzling
);
2559 if (devinfo
->gen
>= 10)
2560 intel_cs_timestamp_frequency(screen
);
2562 /* GENs prior to 8 do not support EU/Subslice info */
2563 if (devinfo
->gen
>= 8) {
2564 intel_detect_sseu(screen
);
2565 } else if (devinfo
->gen
== 7) {
2566 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2569 /* Gen7-7.5 kernel requirements / command parser saga:
2572 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2574 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2575 * all batches secure, allowing them to use any feature with no checking.
2576 * This is effectively equivalent to a command parser version of
2577 * \infinity - everything is possible.
2579 * The command parser does not exist, and querying the version will
2583 * The kernel enables the command parser by default, for systems with
2584 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2585 * hardware checker is still enabled, so Haswell and Baytrail cannot
2588 * Ivybridge goes from "everything is possible" to "only what the
2589 * command parser allows" (if the user boots with i915.cmd_parser=0,
2590 * then everything is possible again). We can only safely use features
2591 * allowed by the supported command parser version.
2593 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2594 * implemented by the kernel, even if it's turned off. So, checking
2595 * for version > 0 does not mean that you can write registers. We have
2596 * to try it and see. The version does, however, indicate the age of
2599 * Instead of matching the hardware checker's behavior of converting
2600 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2601 * -EINVAL, making it dangerous to try and use privileged features.
2603 * Effective command parser versions:
2604 * - Haswell: 0 (reporting 1, writes don't work)
2605 * - Baytrail: 0 (reporting 1, writes don't work)
2606 * - Ivybridge: 1 (enabled) or infinite (disabled)
2609 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2610 * effectively version 1 (enabled) or infinite (disabled).
2612 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2613 * Command parser v2 supports predicate writes.
2615 * - Haswell: 0 (reporting 1, writes don't work)
2616 * - Baytrail: 2 (enabled) or infinite (disabled)
2617 * - Ivybridge: 2 (enabled) or infinite (disabled)
2619 * So version >= 2 is enough to know that Ivybridge and Baytrail
2620 * will work. Haswell still can't do anything.
2622 * - v4.0: Version 3 happened. Largely not relevant.
2624 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2625 * L3 config registers are properly saved and restored as part
2626 * of the hardware context. We can approximately detect this point
2627 * in time by checking if I915_PARAM_REVISION is recognized - it
2628 * landed in a later commit, but in the same release cycle.
2630 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2631 * Command parser finally gains secure batch promotion. On Haswell,
2632 * the hardware checker gets disabled, which finally allows it to do
2633 * privileged commands.
2635 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2636 * - Haswell: 3 (enabled) or 0 (disabled)
2637 * - Baytrail: 3 (enabled) or infinite (disabled)
2638 * - Ivybridge: 3 (enabled) or infinite (disabled)
2640 * Unfortunately, detecting this point in time is tricky, because
2641 * no version bump happened when this important change occurred.
2642 * On Haswell, if we can write any register, then the kernel is at
2643 * least this new, and we can start trusting the version number.
2645 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2646 * Command parser reaches version 4, allowing access to Haswell
2647 * atomic scratch and chicken3 registers. If version >= 4, we know
2648 * the kernel is new enough to support privileged features on all
2649 * hardware. However, the user might have disabled it...and the
2650 * kernel will still report version 4. So we still have to guess
2653 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2654 * Command parser v5 whitelists indirect compute shader dispatch
2655 * registers, needed for OpenGL 4.3 and later.
2658 * Command parser v7 lets us use MI_MATH on Haswell.
2660 * Additionally, the kernel begins reporting version 0 when
2661 * the command parser is disabled, allowing us to skip the
2662 * guess-and-check step on Haswell. Unfortunately, this also
2663 * means that we can no longer use it as an indicator of the
2664 * age of the kernel.
2666 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2667 &screen
->cmd_parser_version
) < 0) {
2668 /* Command parser does not exist - getparam is unrecognized */
2669 screen
->cmd_parser_version
= 0;
2672 /* Kernel 4.13 retuired for exec object capture */
2673 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2674 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2677 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2678 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2681 if (!intel_detect_pipelined_so(screen
)) {
2682 /* We can't do anything, so the effective version is 0. */
2683 screen
->cmd_parser_version
= 0;
2685 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2688 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2689 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2691 /* Haswell requires command parser version 4 in order to have L3
2692 * atomic scratch1 and chicken3 bits
2694 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2695 screen
->kernel_features
|=
2696 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2699 /* Haswell requires command parser version 6 in order to write to the
2700 * MI_MATH GPR registers, and version 7 in order to use
2701 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2703 if (devinfo
->gen
>= 8 ||
2704 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2705 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2708 /* Gen7 needs at least command parser version 5 to support compute */
2709 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2710 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2712 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2713 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2715 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2717 screen
->winsys_msaa_samples_override
=
2718 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2719 printf("Forcing winsys sample count to %d\n",
2720 screen
->winsys_msaa_samples_override
);
2722 screen
->winsys_msaa_samples_override
= -1;
2725 set_max_gl_versions(screen
);
2727 /* Notification of GPU resets requires hardware contexts and a kernel new
2728 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2729 * supported, calling it with a context of 0 will either generate EPERM or
2730 * no error. If the ioctl is not supported, it always generate EINVAL.
2731 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2732 * extension to the loader.
2734 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2736 if (devinfo
->gen
>= 6) {
2737 struct drm_i915_reset_stats stats
;
2738 memset(&stats
, 0, sizeof(stats
));
2740 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2742 screen
->has_context_reset_notification
=
2743 (ret
!= -1 || errno
!= EINVAL
);
2746 dri_screen
->extensions
= !screen
->has_context_reset_notification
2747 ? screenExtensions
: intelRobustScreenExtensions
;
2749 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2750 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2751 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2753 /* Changing the meaning of constant buffer pointers from a dynamic state
2754 * offset to an absolute address is only safe if the kernel isolates other
2755 * contexts from our changes.
2757 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8 ||
2758 !(screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
);
2760 screen
->compiler
->supports_pull_constants
= true;
2762 screen
->has_exec_fence
=
2763 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2765 intel_screen_init_surface_formats(screen
);
2767 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2768 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2770 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2771 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2772 fprintf(stderr
, " - User priority sorting enabled\n");
2773 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2774 fprintf(stderr
, " - Preemption enabled\n");
2778 brw_disk_cache_init(screen
);
2780 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2783 struct intel_buffer
{
2788 static __DRIbuffer
*
2789 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2790 unsigned attachment
, unsigned format
,
2791 int width
, int height
)
2793 struct intel_buffer
*intelBuffer
;
2794 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2796 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2797 attachment
== __DRI_BUFFER_BACK_LEFT
);
2799 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2800 if (intelBuffer
== NULL
)
2803 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2804 * supports Y tiled and compressed buffers, but there is no way to plumb that
2805 * through to here. */
2807 int cpp
= format
/ 8;
2808 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2809 "intelAllocateBuffer",
2814 I915_TILING_X
, &pitch
,
2817 if (intelBuffer
->bo
== NULL
) {
2822 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2824 intelBuffer
->base
.attachment
= attachment
;
2825 intelBuffer
->base
.cpp
= cpp
;
2826 intelBuffer
->base
.pitch
= pitch
;
2828 return &intelBuffer
->base
;
2832 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2834 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2836 brw_bo_unreference(intelBuffer
->bo
);
2840 static const struct __DriverAPIRec brw_driver_api
= {
2841 .InitScreen
= intelInitScreen2
,
2842 .DestroyScreen
= intelDestroyScreen
,
2843 .CreateContext
= brwCreateContext
,
2844 .DestroyContext
= intelDestroyContext
,
2845 .CreateBuffer
= intelCreateBuffer
,
2846 .DestroyBuffer
= intelDestroyBuffer
,
2847 .MakeCurrent
= intelMakeCurrent
,
2848 .UnbindContext
= intelUnbindContext
,
2849 .AllocateBuffer
= intelAllocateBuffer
,
2850 .ReleaseBuffer
= intelReleaseBuffer
2853 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2854 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2855 .vtable
= &brw_driver_api
,
2858 static const __DRIextension
*brw_driver_extensions
[] = {
2859 &driCoreExtension
.base
,
2860 &driImageDriverExtension
.base
,
2861 &driDRI2Extension
.base
,
2863 &brw_config_options
.base
,
2867 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2869 globalDriverAPI
= &brw_driver_api
;
2871 return brw_driver_extensions
;