2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/context.h"
30 #include "main/framebuffer.h"
31 #include "main/renderbuffer.h"
32 #include "main/texobj.h"
33 #include "main/hash.h"
34 #include "main/fbobject.h"
35 #include "main/version.h"
36 #include "swrast/s_renderbuffer.h"
37 #include "util/ralloc.h"
38 #include "brw_shader.h"
39 #include "compiler/nir/nir.h"
44 static const __DRIconfigOptionsExtension brw_config_options
= {
45 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
48 DRI_CONF_SECTION_PERFORMANCE
49 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
50 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
51 * DRI_CONF_BO_REUSE_ALL
53 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
54 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
55 DRI_CONF_ENUM(0, "Disable buffer object reuse")
56 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
61 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_FORCE_S3TC_ENABLE("false")
68 DRI_CONF_PRECISE_TRIG("false")
70 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
71 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
72 "given integer. If negative, then do not clamp.")
76 DRI_CONF_SECTION_DEBUG
77 DRI_CONF_NO_RAST("false")
78 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
79 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
80 DRI_CONF_DISABLE_THROTTLING("false")
81 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
82 DRI_CONF_FORCE_GLSL_VERSION(0)
83 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
84 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
85 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
86 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
88 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
89 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
93 DRI_CONF_SECTION_MISCELLANEOUS
94 DRI_CONF_GLSL_ZERO_INIT("false")
99 #include "intel_batchbuffer.h"
100 #include "intel_buffers.h"
101 #include "intel_bufmgr.h"
102 #include "intel_fbo.h"
103 #include "intel_mipmap_tree.h"
104 #include "intel_screen.h"
105 #include "intel_tex.h"
106 #include "intel_image.h"
108 #include "brw_context.h"
110 #include "i915_drm.h"
113 * For debugging purposes, this returns a time in seconds.
120 clock_gettime(CLOCK_MONOTONIC
, &tp
);
122 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
126 aub_dump_bmp(struct gl_context
*ctx
)
128 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
130 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
131 struct intel_renderbuffer
*irb
=
132 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
134 if (irb
&& irb
->mt
) {
135 enum aub_dump_bmp_format format
;
137 switch (irb
->Base
.Base
.Format
) {
138 case MESA_FORMAT_B8G8R8A8_UNORM
:
139 case MESA_FORMAT_B8G8R8X8_UNORM
:
140 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
146 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
149 irb
->Base
.Base
.Width
,
150 irb
->Base
.Base
.Height
,
158 static const __DRItexBufferExtension intelTexBufferExtension
= {
159 .base
= { __DRI_TEX_BUFFER
, 3 },
161 .setTexBuffer
= intelSetTexBuffer
,
162 .setTexBuffer2
= intelSetTexBuffer2
,
163 .releaseTexBuffer
= NULL
,
167 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
168 __DRIdrawable
*dPriv
,
170 enum __DRI2throttleReason reason
)
172 struct brw_context
*brw
= cPriv
->driverPrivate
;
177 struct gl_context
*ctx
= &brw
->ctx
;
179 FLUSH_VERTICES(ctx
, 0);
181 if (flags
& __DRI2_FLUSH_DRAWABLE
)
182 intel_resolve_for_dri2_flush(brw
, dPriv
);
184 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
185 brw
->need_swap_throttle
= true;
186 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
187 brw
->need_flush_throttle
= true;
189 intel_batchbuffer_flush(brw
);
191 if (INTEL_DEBUG
& DEBUG_AUB
) {
197 * Provides compatibility with loaders that only support the older (version
198 * 1-3) flush interface.
200 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
203 intel_dri2_flush(__DRIdrawable
*drawable
)
205 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
206 __DRI2_FLUSH_DRAWABLE
,
207 __DRI2_THROTTLE_SWAPBUFFER
);
210 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
211 .base
= { __DRI2_FLUSH
, 4 },
213 .flush
= intel_dri2_flush
,
214 .invalidate
= dri2InvalidateDrawable
,
215 .flush_with_flags
= intel_dri2_flush_with_flags
,
218 static struct intel_image_format intel_image_formats
[] = {
219 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
222 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
225 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
226 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
228 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
229 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
231 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
234 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
237 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
240 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
241 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
243 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
244 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
246 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
249 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
250 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
252 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
253 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
257 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
258 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
262 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
263 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
267 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
268 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
272 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
273 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
275 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
277 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
278 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
279 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
280 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
282 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
283 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
284 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
285 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
287 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
288 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
289 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
290 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
292 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
293 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
294 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
295 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
297 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
298 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
299 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
300 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
302 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
303 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
304 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
306 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
307 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
308 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
310 /* For YUYV buffers, we set up two overlapping DRI images and treat
311 * them as planar buffers in the compositors. Plane 0 is GR88 and
312 * samples YU or YV pairs and places Y into the R component, while
313 * plane 1 is ARGB and samples YUYV clusters and places pairs and
314 * places U into the G component and V into A. This lets the
315 * texture sampler interpolate the Y components correctly when
316 * sampling from plane 0, and interpolate U and V correctly when
317 * sampling from plane 1. */
318 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
319 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
320 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
324 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
326 uint32_t tiling
, swizzle
;
327 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
329 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
330 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
331 func
, image
->offset
);
335 static struct intel_image_format
*
336 intel_image_format_lookup(int fourcc
)
338 struct intel_image_format
*f
= NULL
;
340 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
341 if (intel_image_formats
[i
].fourcc
== fourcc
) {
342 f
= &intel_image_formats
[i
];
350 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
352 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
353 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
354 *fourcc
= intel_image_formats
[i
].fourcc
;
362 intel_allocate_image(int dri_format
, void *loaderPrivate
)
366 image
= calloc(1, sizeof *image
);
370 image
->dri_format
= dri_format
;
373 image
->format
= driImageFormatToGLFormat(dri_format
);
374 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
375 image
->format
== MESA_FORMAT_NONE
) {
380 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
381 image
->data
= loaderPrivate
;
387 * Sets up a DRIImage structure to point to a slice out of a miptree.
390 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
391 struct intel_mipmap_tree
*mt
, GLuint level
,
394 intel_miptree_make_shareable(brw
, mt
);
396 intel_miptree_check_level_layer(mt
, level
, zoffset
);
398 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
399 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
400 image
->pitch
= mt
->pitch
;
402 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
406 drm_intel_bo_unreference(image
->bo
);
408 drm_intel_bo_reference(mt
->bo
);
412 intel_create_image_from_name(__DRIscreen
*dri_screen
,
413 int width
, int height
, int format
,
414 int name
, int pitch
, void *loaderPrivate
)
416 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
420 image
= intel_allocate_image(format
, loaderPrivate
);
424 if (image
->format
== MESA_FORMAT_NONE
)
427 cpp
= _mesa_get_format_bytes(image
->format
);
429 image
->width
= width
;
430 image
->height
= height
;
431 image
->pitch
= pitch
* cpp
;
432 image
->bo
= drm_intel_bo_gem_create_from_name(screen
->bufmgr
, "image",
443 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
444 int renderbuffer
, void *loaderPrivate
)
447 struct brw_context
*brw
= context
->driverPrivate
;
448 struct gl_context
*ctx
= &brw
->ctx
;
449 struct gl_renderbuffer
*rb
;
450 struct intel_renderbuffer
*irb
;
452 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
454 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
458 irb
= intel_renderbuffer(rb
);
459 intel_miptree_make_shareable(brw
, irb
->mt
);
460 image
= calloc(1, sizeof *image
);
464 image
->internal_format
= rb
->InternalFormat
;
465 image
->format
= rb
->Format
;
467 image
->data
= loaderPrivate
;
468 drm_intel_bo_unreference(image
->bo
);
469 image
->bo
= irb
->mt
->bo
;
470 drm_intel_bo_reference(irb
->mt
->bo
);
471 image
->width
= rb
->Width
;
472 image
->height
= rb
->Height
;
473 image
->pitch
= irb
->mt
->pitch
;
474 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
475 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
477 rb
->NeedsFinishRenderTexture
= true;
482 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
483 unsigned texture
, int zoffset
,
489 struct brw_context
*brw
= context
->driverPrivate
;
490 struct gl_texture_object
*obj
;
491 struct intel_texture_object
*iobj
;
494 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
495 if (!obj
|| obj
->Target
!= target
) {
496 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
500 if (target
== GL_TEXTURE_CUBE_MAP
)
503 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
504 iobj
= intel_texture_object(obj
);
505 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
506 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
510 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
511 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
515 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
516 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
519 image
= calloc(1, sizeof *image
);
521 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
525 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
526 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
527 image
->data
= loaderPrivate
;
528 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
529 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
530 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
531 if (image
->dri_format
== MESA_FORMAT_NONE
) {
532 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
537 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
542 intel_destroy_image(__DRIimage
*image
)
544 drm_intel_bo_unreference(image
->bo
);
549 intel_create_image(__DRIscreen
*dri_screen
,
550 int width
, int height
, int format
,
555 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
560 tiling
= I915_TILING_X
;
561 if (use
& __DRI_IMAGE_USE_CURSOR
) {
562 if (width
!= 64 || height
!= 64)
564 tiling
= I915_TILING_NONE
;
567 if (use
& __DRI_IMAGE_USE_LINEAR
)
568 tiling
= I915_TILING_NONE
;
570 image
= intel_allocate_image(format
, loaderPrivate
);
574 cpp
= _mesa_get_format_bytes(image
->format
);
575 image
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "image",
576 width
, height
, cpp
, &tiling
,
578 if (image
->bo
== NULL
) {
582 image
->width
= width
;
583 image
->height
= height
;
584 image
->pitch
= pitch
;
590 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
593 case __DRI_IMAGE_ATTRIB_STRIDE
:
594 *value
= image
->pitch
;
596 case __DRI_IMAGE_ATTRIB_HANDLE
:
597 *value
= image
->bo
->handle
;
599 case __DRI_IMAGE_ATTRIB_NAME
:
600 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
601 case __DRI_IMAGE_ATTRIB_FORMAT
:
602 *value
= image
->dri_format
;
604 case __DRI_IMAGE_ATTRIB_WIDTH
:
605 *value
= image
->width
;
607 case __DRI_IMAGE_ATTRIB_HEIGHT
:
608 *value
= image
->height
;
610 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
611 if (image
->planar_format
== NULL
)
613 *value
= image
->planar_format
->components
;
615 case __DRI_IMAGE_ATTRIB_FD
:
616 return !drm_intel_bo_gem_export_to_prime(image
->bo
, value
);
617 case __DRI_IMAGE_ATTRIB_FOURCC
:
618 return intel_lookup_fourcc(image
->dri_format
, value
);
619 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
622 case __DRI_IMAGE_ATTRIB_OFFSET
:
623 *value
= image
->offset
;
632 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
636 image
= calloc(1, sizeof *image
);
640 drm_intel_bo_reference(orig_image
->bo
);
641 image
->bo
= orig_image
->bo
;
642 image
->internal_format
= orig_image
->internal_format
;
643 image
->planar_format
= orig_image
->planar_format
;
644 image
->dri_format
= orig_image
->dri_format
;
645 image
->format
= orig_image
->format
;
646 image
->offset
= orig_image
->offset
;
647 image
->width
= orig_image
->width
;
648 image
->height
= orig_image
->height
;
649 image
->pitch
= orig_image
->pitch
;
650 image
->tile_x
= orig_image
->tile_x
;
651 image
->tile_y
= orig_image
->tile_y
;
652 image
->has_depthstencil
= orig_image
->has_depthstencil
;
653 image
->data
= loaderPrivate
;
655 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
656 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
662 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
664 if (use
& __DRI_IMAGE_USE_CURSOR
) {
665 if (image
->width
!= 64 || image
->height
!= 64)
673 intel_create_image_from_names(__DRIscreen
*dri_screen
,
674 int width
, int height
, int fourcc
,
675 int *names
, int num_names
,
676 int *strides
, int *offsets
,
679 struct intel_image_format
*f
= NULL
;
683 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
686 f
= intel_image_format_lookup(fourcc
);
690 image
= intel_create_image_from_name(dri_screen
, width
, height
,
691 __DRI_IMAGE_FORMAT_NONE
,
692 names
[0], strides
[0],
698 image
->planar_format
= f
;
699 for (i
= 0; i
< f
->nplanes
; i
++) {
700 index
= f
->planes
[i
].buffer_index
;
701 image
->offsets
[index
] = offsets
[index
];
702 image
->strides
[index
] = strides
[index
];
709 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
710 int width
, int height
, int fourcc
,
711 int *fds
, int num_fds
, int *strides
, int *offsets
,
714 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
715 struct intel_image_format
*f
;
719 if (fds
== NULL
|| num_fds
< 1)
722 /* We only support all planes from the same bo */
723 for (i
= 0; i
< num_fds
; i
++)
724 if (fds
[0] != fds
[i
])
727 f
= intel_image_format_lookup(fourcc
);
732 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
734 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
739 image
->width
= width
;
740 image
->height
= height
;
741 image
->pitch
= strides
[0];
743 image
->planar_format
= f
;
745 for (i
= 0; i
< f
->nplanes
; i
++) {
746 index
= f
->planes
[i
].buffer_index
;
747 image
->offsets
[index
] = offsets
[index
];
748 image
->strides
[index
] = strides
[index
];
750 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
751 const int end
= offsets
[index
] + plane_height
* strides
[index
];
756 image
->bo
= drm_intel_bo_gem_create_from_prime(screen
->bufmgr
,
758 if (image
->bo
== NULL
) {
763 if (f
->nplanes
== 1) {
764 image
->offset
= image
->offsets
[0];
765 intel_image_warn_if_unaligned(image
, __func__
);
772 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
773 int width
, int height
, int fourcc
,
774 int *fds
, int num_fds
,
775 int *strides
, int *offsets
,
776 enum __DRIYUVColorSpace yuv_color_space
,
777 enum __DRISampleRange sample_range
,
778 enum __DRIChromaSiting horizontal_siting
,
779 enum __DRIChromaSiting vertical_siting
,
784 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
787 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
791 image
= intel_create_image_from_fds(dri_screen
, width
, height
, fourcc
, fds
,
792 num_fds
, strides
, offsets
,
796 * Invalid parameters and any inconsistencies between are assumed to be
797 * checked by the caller. Therefore besides unsupported formats one can fail
798 * only in allocation.
801 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
805 image
->dma_buf_imported
= true;
806 image
->yuv_color_space
= yuv_color_space
;
807 image
->sample_range
= sample_range
;
808 image
->horizontal_siting
= horizontal_siting
;
809 image
->vertical_siting
= vertical_siting
;
811 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
816 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
818 int width
, height
, offset
, stride
, dri_format
, index
;
819 struct intel_image_format
*f
;
822 if (parent
== NULL
|| parent
->planar_format
== NULL
)
825 f
= parent
->planar_format
;
827 if (plane
>= f
->nplanes
)
830 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
831 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
832 dri_format
= f
->planes
[plane
].dri_format
;
833 index
= f
->planes
[plane
].buffer_index
;
834 offset
= parent
->offsets
[index
];
835 stride
= parent
->strides
[index
];
837 image
= intel_allocate_image(dri_format
, loaderPrivate
);
841 if (offset
+ height
* stride
> parent
->bo
->size
) {
842 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
847 image
->bo
= parent
->bo
;
848 drm_intel_bo_reference(parent
->bo
);
850 image
->width
= width
;
851 image
->height
= height
;
852 image
->pitch
= stride
;
853 image
->offset
= offset
;
855 intel_image_warn_if_unaligned(image
, __func__
);
860 static const __DRIimageExtension intelImageExtension
= {
861 .base
= { __DRI_IMAGE
, 13 },
863 .createImageFromName
= intel_create_image_from_name
,
864 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
865 .destroyImage
= intel_destroy_image
,
866 .createImage
= intel_create_image
,
867 .queryImage
= intel_query_image
,
868 .dupImage
= intel_dup_image
,
869 .validateUsage
= intel_validate_usage
,
870 .createImageFromNames
= intel_create_image_from_names
,
871 .fromPlanar
= intel_from_planar
,
872 .createImageFromTexture
= intel_create_image_from_texture
,
873 .createImageFromFds
= intel_create_image_from_fds
,
874 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
876 .getCapabilities
= NULL
,
882 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
883 int param
, unsigned int *value
)
885 const struct intel_screen
*const screen
=
886 (struct intel_screen
*) dri_screen
->driverPrivate
;
889 case __DRI2_RENDERER_VENDOR_ID
:
892 case __DRI2_RENDERER_DEVICE_ID
:
893 value
[0] = screen
->deviceID
;
895 case __DRI2_RENDERER_ACCELERATED
:
898 case __DRI2_RENDERER_VIDEO_MEMORY
: {
899 /* Once a batch uses more than 75% of the maximum mappable size, we
900 * assume that there's some fragmentation, and we start doing extra
901 * flushing, etc. That's the big cliff apps will care about.
904 size_t mappable_size
;
906 drm_intel_get_aperture_sizes(dri_screen
->fd
, &mappable_size
, &aper_size
);
908 const unsigned gpu_mappable_megabytes
=
909 (aper_size
/ (1024 * 1024)) * 3 / 4;
911 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
912 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
914 if (system_memory_pages
<= 0 || system_page_size
<= 0)
917 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
918 * (uint64_t) system_page_size
;
920 const unsigned system_memory_megabytes
=
921 (unsigned) (system_memory_bytes
/ (1024 * 1024));
923 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
926 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
929 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
933 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
940 brw_query_renderer_string(__DRIscreen
*dri_screen
,
941 int param
, const char **value
)
943 const struct intel_screen
*screen
=
944 (struct intel_screen
*) dri_screen
->driverPrivate
;
947 case __DRI2_RENDERER_VENDOR_ID
:
948 value
[0] = brw_vendor_string
;
950 case __DRI2_RENDERER_DEVICE_ID
:
951 value
[0] = brw_get_renderer_string(screen
);
960 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
961 .base
= { __DRI2_RENDERER_QUERY
, 1 },
963 .queryInteger
= brw_query_renderer_integer
,
964 .queryString
= brw_query_renderer_string
967 static const __DRIrobustnessExtension dri2Robustness
= {
968 .base
= { __DRI2_ROBUSTNESS
, 1 }
971 static const __DRIextension
*screenExtensions
[] = {
972 &intelTexBufferExtension
.base
,
973 &intelFenceExtension
.base
,
974 &intelFlushExtension
.base
,
975 &intelImageExtension
.base
,
976 &intelRendererQueryExtension
.base
,
977 &dri2ConfigQueryExtension
.base
,
981 static const __DRIextension
*intelRobustScreenExtensions
[] = {
982 &intelTexBufferExtension
.base
,
983 &intelFenceExtension
.base
,
984 &intelFlushExtension
.base
,
985 &intelImageExtension
.base
,
986 &intelRendererQueryExtension
.base
,
987 &dri2ConfigQueryExtension
.base
,
988 &dri2Robustness
.base
,
993 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
996 struct drm_i915_getparam gp
;
998 memset(&gp
, 0, sizeof(gp
));
1002 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1005 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1012 intel_get_boolean(struct intel_screen
*screen
, int param
)
1015 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1019 intel_get_integer(struct intel_screen
*screen
, int param
)
1023 if (intel_get_param(screen
, param
, &value
) == 0)
1030 intelDestroyScreen(__DRIscreen
* sPriv
)
1032 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1034 dri_bufmgr_destroy(screen
->bufmgr
);
1035 driDestroyOptionInfo(&screen
->optionCache
);
1037 ralloc_free(screen
);
1038 sPriv
->driverPrivate
= NULL
;
1043 * This is called when we need to set up GL rendering to a new X window.
1046 intelCreateBuffer(__DRIscreen
*dri_screen
,
1047 __DRIdrawable
* driDrawPriv
,
1048 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1050 struct intel_renderbuffer
*rb
;
1051 struct intel_screen
*screen
= (struct intel_screen
*)
1052 dri_screen
->driverPrivate
;
1053 mesa_format rgbFormat
;
1054 unsigned num_samples
=
1055 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1056 struct gl_framebuffer
*fb
;
1061 fb
= CALLOC_STRUCT(gl_framebuffer
);
1065 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1067 if (screen
->winsys_msaa_samples_override
!= -1) {
1068 num_samples
= screen
->winsys_msaa_samples_override
;
1069 fb
->Visual
.samples
= num_samples
;
1072 if (mesaVis
->redBits
== 5) {
1073 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1074 : MESA_FORMAT_B5G6R5_UNORM
;
1075 } else if (mesaVis
->sRGBCapable
) {
1076 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1077 : MESA_FORMAT_B8G8R8A8_SRGB
;
1078 } else if (mesaVis
->alphaBits
== 0) {
1079 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1080 : MESA_FORMAT_B8G8R8X8_UNORM
;
1082 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1083 : MESA_FORMAT_B8G8R8A8_SRGB
;
1084 fb
->Visual
.sRGBCapable
= true;
1087 /* setup the hardware-based renderbuffers */
1088 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1089 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1091 if (mesaVis
->doubleBufferMode
) {
1092 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1093 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1097 * Assert here that the gl_config has an expected depth/stencil bit
1098 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1099 * which constructs the advertised configs.)
1101 if (mesaVis
->depthBits
== 24) {
1102 assert(mesaVis
->stencilBits
== 8);
1104 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1105 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1107 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1108 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1110 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1113 * Use combined depth/stencil. Note that the renderbuffer is
1114 * attached to two attachment points.
1116 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1118 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1119 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1122 else if (mesaVis
->depthBits
== 16) {
1123 assert(mesaVis
->stencilBits
== 0);
1124 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1126 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1129 assert(mesaVis
->depthBits
== 0);
1130 assert(mesaVis
->stencilBits
== 0);
1133 /* now add any/all software-based renderbuffers we may need */
1134 _swrast_add_soft_renderbuffers(fb
,
1135 false, /* never sw color */
1136 false, /* never sw depth */
1137 false, /* never sw stencil */
1138 mesaVis
->accumRedBits
> 0,
1139 false, /* never sw alpha */
1140 false /* never sw aux */ );
1141 driDrawPriv
->driverPrivate
= fb
;
1147 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1149 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1151 _mesa_reference_framebuffer(&fb
, NULL
);
1155 intel_detect_sseu(struct intel_screen
*screen
)
1157 assert(screen
->devinfo
.gen
>= 8);
1160 screen
->subslice_total
= -1;
1161 screen
->eu_total
= -1;
1163 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1164 &screen
->subslice_total
);
1165 if (ret
< 0 && ret
!= -EINVAL
)
1168 ret
= intel_get_param(screen
,
1169 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1170 if (ret
< 0 && ret
!= -EINVAL
)
1173 /* Without this information, we cannot get the right Braswell brandstrings,
1174 * and we have to use conservative numbers for GPGPU on many platforms, but
1175 * otherwise, things will just work.
1177 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1179 "Kernel 4.1 required to properly query GPU properties.\n");
1184 screen
->subslice_total
= -1;
1185 screen
->eu_total
= -1;
1186 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1190 intel_init_bufmgr(struct intel_screen
*screen
)
1192 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1194 screen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1196 screen
->bufmgr
= intel_bufmgr_gem_init(dri_screen
->fd
, BATCH_SZ
);
1197 if (screen
->bufmgr
== NULL
) {
1198 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1199 __func__
, __LINE__
);
1203 drm_intel_bufmgr_gem_enable_fenced_relocs(screen
->bufmgr
);
1205 if (!intel_get_boolean(screen
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1206 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1214 intel_detect_swizzling(struct intel_screen
*screen
)
1216 drm_intel_bo
*buffer
;
1217 unsigned long flags
= 0;
1218 unsigned long aligned_pitch
;
1219 uint32_t tiling
= I915_TILING_X
;
1220 uint32_t swizzle_mode
= 0;
1222 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1224 &tiling
, &aligned_pitch
, flags
);
1228 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1229 drm_intel_bo_unreference(buffer
);
1231 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1238 intel_detect_timestamp(struct intel_screen
*screen
)
1240 uint64_t dummy
= 0, last
= 0;
1241 int upper
, lower
, loops
;
1243 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1244 * TIMESTAMP register being shifted and the low 32bits always zero.
1246 * More recent kernels offer an interface to read the full 36bits
1249 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1252 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1253 * upper 32bits for a rapidly changing timestamp.
1255 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1259 for (loops
= 0; loops
< 10; loops
++) {
1260 /* The TIMESTAMP should change every 80ns, so several round trips
1261 * through the kernel should be enough to advance it.
1263 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1266 upper
+= (dummy
>> 32) != (last
>> 32);
1267 if (upper
> 1) /* beware 32bit counter overflow */
1268 return 2; /* upper dword holds the low 32bits of the timestamp */
1270 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1272 return 1; /* timestamp is unshifted */
1277 /* No advancement? No timestamp! */
1282 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1284 * Some combinations of hardware and kernel versions allow this feature,
1285 * while others don't. Instead of trying to enumerate every case, just
1286 * try and write a register and see if works.
1289 intel_detect_pipelined_register(struct intel_screen
*screen
,
1290 int reg
, uint32_t expected_value
, bool reset
)
1292 drm_intel_bo
*results
, *bo
;
1294 uint32_t offset
= 0;
1295 bool success
= false;
1297 /* Create a zero'ed temporary buffer for reading our results */
1298 results
= drm_intel_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1299 if (results
== NULL
)
1302 bo
= drm_intel_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1306 if (drm_intel_bo_map(bo
, 1))
1309 batch
= bo
->virtual;
1311 /* Write the register. */
1312 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1314 *batch
++ = expected_value
;
1316 /* Save the register's value back to the buffer. */
1317 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1319 drm_intel_bo_emit_reloc(bo
, (char *)batch
-(char *)bo
->virtual,
1320 results
, offset
*sizeof(uint32_t),
1321 I915_GEM_DOMAIN_INSTRUCTION
,
1322 I915_GEM_DOMAIN_INSTRUCTION
);
1323 *batch
++ = results
->offset
+ offset
*sizeof(uint32_t);
1325 /* And afterwards clear the register */
1327 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1332 *batch
++ = MI_BATCH_BUFFER_END
;
1334 drm_intel_bo_mrb_exec(bo
, ALIGN((char *)batch
- (char *)bo
->virtual, 8),
1338 /* Check whether the value got written. */
1339 if (drm_intel_bo_map(results
, false) == 0) {
1340 success
= *((uint32_t *)results
->virtual + offset
) == expected_value
;
1341 drm_intel_bo_unmap(results
);
1345 drm_intel_bo_unreference(bo
);
1347 drm_intel_bo_unreference(results
);
1353 intel_detect_pipelined_so(struct intel_screen
*screen
)
1355 /* Supposedly, Broadwell just works. */
1356 if (screen
->devinfo
.gen
>= 8)
1359 if (screen
->devinfo
.gen
<= 6)
1362 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1363 * statistics registers), and we already reset it to zero before using it.
1365 return intel_detect_pipelined_register(screen
,
1366 GEN7_SO_WRITE_OFFSET(0),
1372 * Return array of MSAA modes supported by the hardware. The array is
1373 * zero-terminated and sorted in decreasing order.
1376 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1378 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1379 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1380 static const int gen7_modes
[] = {8, 4, 0, -1};
1381 static const int gen6_modes
[] = {4, 0, -1};
1382 static const int gen4_modes
[] = {0, -1};
1384 if (screen
->devinfo
.gen
>= 9) {
1386 } else if (screen
->devinfo
.gen
>= 8) {
1388 } else if (screen
->devinfo
.gen
>= 7) {
1390 } else if (screen
->devinfo
.gen
== 6) {
1397 static __DRIconfig
**
1398 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1400 static const mesa_format formats
[] = {
1401 MESA_FORMAT_B5G6R5_UNORM
,
1402 MESA_FORMAT_B8G8R8A8_UNORM
,
1403 MESA_FORMAT_B8G8R8X8_UNORM
1406 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1407 static const GLenum back_buffer_modes
[] = {
1408 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1411 static const uint8_t singlesample_samples
[1] = {0};
1412 static const uint8_t multisample_samples
[2] = {4, 8};
1414 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1415 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1416 uint8_t depth_bits
[4], stencil_bits
[4];
1417 __DRIconfig
**configs
= NULL
;
1419 /* Generate singlesample configs without accumulation buffer. */
1420 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1421 __DRIconfig
**new_configs
;
1422 int num_depth_stencil_bits
= 2;
1424 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1425 * buffer that has a different number of bits per pixel than the color
1426 * buffer, gen >= 6 supports this.
1429 stencil_bits
[0] = 0;
1431 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1433 stencil_bits
[1] = 0;
1434 if (devinfo
->gen
>= 6) {
1436 stencil_bits
[2] = 8;
1437 num_depth_stencil_bits
= 3;
1441 stencil_bits
[1] = 8;
1444 new_configs
= driCreateConfigs(formats
[i
],
1447 num_depth_stencil_bits
,
1448 back_buffer_modes
, 2,
1449 singlesample_samples
, 1,
1451 configs
= driConcatConfigs(configs
, new_configs
);
1454 /* Generate the minimum possible set of configs that include an
1455 * accumulation buffer.
1457 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1458 __DRIconfig
**new_configs
;
1460 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1462 stencil_bits
[0] = 0;
1465 stencil_bits
[0] = 8;
1468 new_configs
= driCreateConfigs(formats
[i
],
1469 depth_bits
, stencil_bits
, 1,
1470 back_buffer_modes
, 1,
1471 singlesample_samples
, 1,
1473 configs
= driConcatConfigs(configs
, new_configs
);
1476 /* Generate multisample configs.
1478 * This loop breaks early, and hence is a no-op, on gen < 6.
1480 * Multisample configs must follow the singlesample configs in order to
1481 * work around an X server bug present in 1.12. The X server chooses to
1482 * associate the first listed RGBA888-Z24S8 config, regardless of its
1483 * sample count, with the 32-bit depth visual used for compositing.
1485 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1486 * supported. Singlebuffer configs are not supported because no one wants
1489 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1490 if (devinfo
->gen
< 6)
1493 __DRIconfig
**new_configs
;
1494 const int num_depth_stencil_bits
= 2;
1495 int num_msaa_modes
= 0;
1498 stencil_bits
[0] = 0;
1500 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1502 stencil_bits
[1] = 0;
1505 stencil_bits
[1] = 8;
1508 if (devinfo
->gen
>= 7)
1510 else if (devinfo
->gen
== 6)
1513 new_configs
= driCreateConfigs(formats
[i
],
1516 num_depth_stencil_bits
,
1517 back_buffer_modes
, 1,
1518 multisample_samples
,
1521 configs
= driConcatConfigs(configs
, new_configs
);
1524 if (configs
== NULL
) {
1525 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1534 set_max_gl_versions(struct intel_screen
*screen
)
1536 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1537 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1539 switch (screen
->devinfo
.gen
) {
1542 dri_screen
->max_gl_core_version
= 45;
1543 dri_screen
->max_gl_compat_version
= 30;
1544 dri_screen
->max_gl_es1_version
= 11;
1545 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1548 dri_screen
->max_gl_core_version
= screen
->devinfo
.is_haswell
&&
1549 can_do_pipelined_register_writes(screen
) ? 45 : 33;
1550 dri_screen
->max_gl_compat_version
= 30;
1551 dri_screen
->max_gl_es1_version
= 11;
1552 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1555 dri_screen
->max_gl_core_version
= 33;
1556 dri_screen
->max_gl_compat_version
= 30;
1557 dri_screen
->max_gl_es1_version
= 11;
1558 dri_screen
->max_gl_es2_version
= 30;
1562 dri_screen
->max_gl_core_version
= 0;
1563 dri_screen
->max_gl_compat_version
= 21;
1564 dri_screen
->max_gl_es1_version
= 11;
1565 dri_screen
->max_gl_es2_version
= 20;
1568 unreachable("unrecognized intel_screen::gen");
1573 * Return the revision (generally the revid field of the PCI header) of the
1576 * XXX: This function is useful to keep around even if it is not currently in
1577 * use. It is necessary for new platforms and revision specific workarounds or
1578 * features. Please don't remove it so that we know it at least continues to
1581 static __attribute__((__unused__
)) int
1582 brw_get_revision(int fd
)
1584 struct drm_i915_getparam gp
;
1588 memset(&gp
, 0, sizeof(gp
));
1589 gp
.param
= I915_PARAM_REVISION
;
1590 gp
.value
= &revision
;
1592 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1599 /* Drop when RS headers get pulled to libdrm */
1600 #ifndef I915_PARAM_HAS_RESOURCE_STREAMER
1601 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
1605 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1607 struct brw_context
*brw
= (struct brw_context
*)data
;
1610 va_start(args
, fmt
);
1612 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1613 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1614 MESA_DEBUG_TYPE_OTHER
,
1615 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1620 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1622 struct brw_context
*brw
= (struct brw_context
*)data
;
1625 va_start(args
, fmt
);
1627 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1629 va_copy(args_copy
, args
);
1630 vfprintf(stderr
, fmt
, args_copy
);
1634 if (brw
->perf_debug
) {
1636 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1637 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1638 MESA_DEBUG_TYPE_PERFORMANCE
,
1639 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1645 * This is the driver specific part of the createNewScreen entry point.
1646 * Called when using DRI2.
1648 * \return the struct gl_config supported by this driver
1651 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
1653 struct intel_screen
*screen
;
1655 if (dri_screen
->image
.loader
) {
1656 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
1657 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1659 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1660 "support required\n");
1664 /* Allocate the private area */
1665 screen
= rzalloc(NULL
, struct intel_screen
);
1667 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1670 /* parse information in __driConfigOptions */
1671 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
1673 screen
->driScrnPriv
= dri_screen
;
1674 dri_screen
->driverPrivate
= (void *) screen
;
1676 if (!intel_init_bufmgr(screen
))
1679 screen
->deviceID
= drm_intel_bufmgr_gem_get_devid(screen
->bufmgr
);
1680 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
1683 brw_process_intel_debug_variable();
1685 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1686 dri_bufmgr_set_debug(screen
->bufmgr
, true);
1688 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && screen
->devinfo
.gen
< 7) {
1690 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1691 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1694 if (INTEL_DEBUG
& DEBUG_AUB
)
1695 drm_intel_bufmgr_gem_set_aub_dump(screen
->bufmgr
, true);
1697 #ifndef I915_PARAM_MMAP_GTT_VERSION
1698 #define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */
1700 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1701 /* Theorectically unlimited! At least for individual objects...
1703 * Currently the entire (global) address space for all GTT maps is
1704 * limited to 64bits. That is all objects on the system that are
1705 * setup for GTT mmapping must fit within 64bits. An attempt to use
1706 * one that exceeds the limit with fail in drm_intel_bo_map_gtt().
1708 * Long before we hit that limit, we will be practically limited by
1709 * that any single object must fit in physical memory (RAM). The upper
1710 * limit on the CPU's address space is currently 48bits (Skylake), of
1711 * which only 39bits can be physical memory. (The GPU itself also has
1712 * a 48bit addressable virtual space.) We can fit over 32 million
1713 * objects of the current maximum allocable size before running out
1716 screen
->max_gtt_map_object_size
= UINT64_MAX
;
1718 /* Estimate the size of the mappable aperture into the GTT. There's an
1719 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1720 * It turns out it's basically always 256MB, though some ancient hardware
1723 uint32_t gtt_size
= 256 * 1024 * 1024;
1725 /* We don't want to map two objects such that a memcpy between them would
1726 * just fault one mapping in and then the other over and over forever. So
1727 * we would need to divide the GTT size by 2. Additionally, some GTT is
1728 * taken up by things like the framebuffer and the ringbuffer and such, so
1729 * be more conservative.
1731 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
1734 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
1735 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
1737 /* GENs prior to 8 do not support EU/Subslice info */
1738 if (screen
->devinfo
.gen
>= 8) {
1739 intel_detect_sseu(screen
);
1740 } else if (screen
->devinfo
.gen
== 7) {
1741 screen
->subslice_total
= 1 << (screen
->devinfo
.gt
- 1);
1744 if (intel_detect_pipelined_so(screen
))
1745 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
1747 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1749 screen
->winsys_msaa_samples_override
=
1750 intel_quantize_num_samples(screen
, atoi(force_msaa
));
1751 printf("Forcing winsys sample count to %d\n",
1752 screen
->winsys_msaa_samples_override
);
1754 screen
->winsys_msaa_samples_override
= -1;
1757 set_max_gl_versions(screen
);
1759 /* Notification of GPU resets requires hardware contexts and a kernel new
1760 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1761 * supported, calling it with a context of 0 will either generate EPERM or
1762 * no error. If the ioctl is not supported, it always generate EINVAL.
1763 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1764 * extension to the loader.
1766 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1768 if (screen
->devinfo
.gen
>= 6) {
1769 struct drm_i915_reset_stats stats
;
1770 memset(&stats
, 0, sizeof(stats
));
1772 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1774 screen
->has_context_reset_notification
=
1775 (ret
!= -1 || errno
!= EINVAL
);
1778 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
1779 &screen
->cmd_parser_version
) < 0) {
1780 screen
->cmd_parser_version
= 0;
1783 if (screen
->devinfo
.gen
>= 8 || screen
->cmd_parser_version
>= 2)
1784 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
1786 /* Haswell requires command parser version 4 in order to have L3
1787 * atomic scratch1 and chicken3 bits
1789 if (screen
->devinfo
.is_haswell
&& screen
->cmd_parser_version
>= 4) {
1790 screen
->kernel_features
|=
1791 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
1794 /* Haswell requires command parser version 6 in order to write to the
1795 * MI_MATH GPR registers, and version 7 in order to use
1796 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
1798 if (screen
->devinfo
.gen
>= 8 ||
1799 (screen
->devinfo
.is_haswell
&& screen
->cmd_parser_version
>= 7)) {
1800 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
1803 /* Gen7 needs at least command parser version 5 to support compute */
1804 if (screen
->devinfo
.gen
>= 8 || screen
->cmd_parser_version
>= 5)
1805 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
1807 dri_screen
->extensions
= !screen
->has_context_reset_notification
1808 ? screenExtensions
: intelRobustScreenExtensions
;
1810 screen
->compiler
= brw_compiler_create(screen
,
1812 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
1813 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
1814 screen
->program_id
= 1;
1816 if (screen
->devinfo
.has_resource_streamer
) {
1817 screen
->has_resource_streamer
=
1818 intel_get_boolean(screen
, I915_PARAM_HAS_RESOURCE_STREAMER
);
1821 screen
->has_exec_fence
=
1822 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
1824 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
1827 struct intel_buffer
{
1832 static __DRIbuffer
*
1833 intelAllocateBuffer(__DRIscreen
*dri_screen
,
1834 unsigned attachment
, unsigned format
,
1835 int width
, int height
)
1837 struct intel_buffer
*intelBuffer
;
1838 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1840 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1841 attachment
== __DRI_BUFFER_BACK_LEFT
);
1843 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1844 if (intelBuffer
== NULL
)
1847 /* The front and back buffers are color buffers, which are X tiled. */
1848 uint32_t tiling
= I915_TILING_X
;
1849 unsigned long pitch
;
1850 int cpp
= format
/ 8;
1851 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
,
1852 "intelAllocateBuffer",
1857 BO_ALLOC_FOR_RENDER
);
1859 if (intelBuffer
->bo
== NULL
) {
1864 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1866 intelBuffer
->base
.attachment
= attachment
;
1867 intelBuffer
->base
.cpp
= cpp
;
1868 intelBuffer
->base
.pitch
= pitch
;
1870 return &intelBuffer
->base
;
1874 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
1876 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1878 drm_intel_bo_unreference(intelBuffer
->bo
);
1882 static const struct __DriverAPIRec brw_driver_api
= {
1883 .InitScreen
= intelInitScreen2
,
1884 .DestroyScreen
= intelDestroyScreen
,
1885 .CreateContext
= brwCreateContext
,
1886 .DestroyContext
= intelDestroyContext
,
1887 .CreateBuffer
= intelCreateBuffer
,
1888 .DestroyBuffer
= intelDestroyBuffer
,
1889 .MakeCurrent
= intelMakeCurrent
,
1890 .UnbindContext
= intelUnbindContext
,
1891 .AllocateBuffer
= intelAllocateBuffer
,
1892 .ReleaseBuffer
= intelReleaseBuffer
1895 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1896 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1897 .vtable
= &brw_driver_api
,
1900 static const __DRIextension
*brw_driver_extensions
[] = {
1901 &driCoreExtension
.base
,
1902 &driImageDriverExtension
.base
,
1903 &driDRI2Extension
.base
,
1905 &brw_config_options
.base
,
1909 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1911 globalDriverAPI
= &brw_driver_api
;
1913 return brw_driver_extensions
;