2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "main/glthread.h"
38 #include "swrast/s_renderbuffer.h"
39 #include "util/ralloc.h"
40 #include "util/disk_cache.h"
41 #include "brw_defines.h"
42 #include "brw_state.h"
43 #include "compiler/nir/nir.h"
46 #include "util/disk_cache.h"
47 #include "util/xmlpool.h"
49 #include "common/gen_defines.h"
51 static const __DRIconfigOptionsExtension brw_config_options
= {
52 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
55 DRI_CONF_SECTION_PERFORMANCE
56 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
57 * DRI_CONF_BO_REUSE_ALL
59 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
60 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
61 DRI_CONF_ENUM(0, "Disable buffer object reuse")
62 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
65 DRI_CONF_MESA_NO_ERROR("false")
66 DRI_CONF_MESA_GLTHREAD("false")
69 DRI_CONF_SECTION_QUALITY
70 DRI_CONF_PRECISE_TRIG("false")
72 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
73 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
74 "given integer. If negative, then do not clamp.")
78 DRI_CONF_SECTION_DEBUG
79 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
80 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
81 DRI_CONF_DISABLE_THROTTLING("false")
82 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
83 DRI_CONF_FORCE_GLSL_VERSION(0)
84 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
85 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
86 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
87 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
88 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
89 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
90 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
91 DRI_CONF_FORCE_COMPAT_PROFILE("false")
92 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
94 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
95 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
99 DRI_CONF_SECTION_MISCELLANEOUS
100 DRI_CONF_GLSL_ZERO_INIT("false")
101 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
102 DRI_CONF_ALLOW_RGB565_CONFIGS("true")
107 #include "intel_batchbuffer.h"
108 #include "intel_buffers.h"
109 #include "brw_bufmgr.h"
110 #include "intel_fbo.h"
111 #include "intel_mipmap_tree.h"
112 #include "intel_screen.h"
113 #include "intel_tex.h"
114 #include "intel_image.h"
116 #include "brw_context.h"
118 #include "drm-uapi/i915_drm.h"
121 * For debugging purposes, this returns a time in seconds.
128 clock_gettime(CLOCK_MONOTONIC
, &tp
);
130 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
133 static const __DRItexBufferExtension intelTexBufferExtension
= {
134 .base
= { __DRI_TEX_BUFFER
, 3 },
136 .setTexBuffer
= intelSetTexBuffer
,
137 .setTexBuffer2
= intelSetTexBuffer2
,
138 .releaseTexBuffer
= intelReleaseTexBuffer
,
142 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
143 __DRIdrawable
*dPriv
,
145 enum __DRI2throttleReason reason
)
147 struct brw_context
*brw
= cPriv
->driverPrivate
;
152 struct gl_context
*ctx
= &brw
->ctx
;
154 _mesa_glthread_finish(ctx
);
156 FLUSH_VERTICES(ctx
, 0);
158 if (flags
& __DRI2_FLUSH_DRAWABLE
)
159 intel_resolve_for_dri2_flush(brw
, dPriv
);
161 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
162 brw
->need_swap_throttle
= true;
163 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
164 brw
->need_flush_throttle
= true;
166 intel_batchbuffer_flush(brw
);
170 * Provides compatibility with loaders that only support the older (version
171 * 1-3) flush interface.
173 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
176 intel_dri2_flush(__DRIdrawable
*drawable
)
178 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
179 __DRI2_FLUSH_DRAWABLE
,
180 __DRI2_THROTTLE_SWAPBUFFER
);
183 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
184 .base
= { __DRI2_FLUSH
, 4 },
186 .flush
= intel_dri2_flush
,
187 .invalidate
= dri2InvalidateDrawable
,
188 .flush_with_flags
= intel_dri2_flush_with_flags
,
191 static const struct intel_image_format intel_image_formats
[] = {
192 { __DRI_IMAGE_FOURCC_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
193 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
195 { __DRI_IMAGE_FOURCC_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
198 { __DRI_IMAGE_FOURCC_ABGR2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010
, 4 } } },
201 { __DRI_IMAGE_FOURCC_XBGR2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010
, 4 } } },
204 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
207 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
210 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
213 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
216 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
219 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
222 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
225 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
226 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
228 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
229 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
231 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
234 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
237 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
240 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
242 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
247 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
248 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
252 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
253 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
257 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
258 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
262 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
263 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
267 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
268 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
272 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
273 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
275 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
277 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
278 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
279 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
280 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
282 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
283 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
284 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
285 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
287 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
288 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
289 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
291 { __DRI_IMAGE_FOURCC_P010
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
292 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
293 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
295 { __DRI_IMAGE_FOURCC_P012
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
296 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
297 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
299 { __DRI_IMAGE_FOURCC_P016
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
300 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
301 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
303 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
304 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
305 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
307 { __DRI_IMAGE_FOURCC_AYUV
, __DRI_IMAGE_COMPONENTS_AYUV
, 1,
308 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
310 { __DRI_IMAGE_FOURCC_XYUV8888
, __DRI_IMAGE_COMPONENTS_XYUV
, 1,
311 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 } } },
313 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
314 * and treat them as planar buffers in the compositors.
315 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
316 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
317 * clusters and places pairs and places U into the G component and
318 * V into A. This lets the texture sampler interpolate the Y
319 * components correctly when sampling from plane 0, and interpolate
320 * U and V correctly when sampling from plane 1. */
321 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
322 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
323 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
324 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
325 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
326 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
329 static const struct {
332 } supported_modifiers
[] = {
333 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
334 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
335 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
336 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
340 modifier_is_supported(const struct gen_device_info
*devinfo
,
341 const struct intel_image_format
*fmt
, int dri_format
,
344 const struct isl_drm_modifier_info
*modinfo
=
345 isl_drm_modifier_get_info(modifier
);
348 /* ISL had better know about the modifier */
352 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
353 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
354 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
357 /* CCS_E is not supported for planar images */
358 if (fmt
&& fmt
->nplanes
> 1)
362 assert(dri_format
== 0);
363 dri_format
= fmt
->planes
[0].dri_format
;
366 mesa_format format
= driImageFormatToGLFormat(dri_format
);
367 /* Whether or not we support compression is based on the RGBA non-sRGB
368 * version of the format.
370 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
371 format
= _mesa_get_srgb_format_linear(format
);
372 if (!isl_format_supports_ccs_e(devinfo
,
373 brw_isl_format_for_mesa_format(format
)))
377 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
378 if (supported_modifiers
[i
].modifier
!= modifier
)
381 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
388 tiling_to_modifier(uint32_t tiling
)
390 static const uint64_t map
[] = {
391 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
392 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
393 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
396 assert(tiling
< ARRAY_SIZE(map
));
402 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
404 uint32_t tiling
, swizzle
;
405 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
407 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
408 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
409 func
, image
->offset
);
413 static const struct intel_image_format
*
414 intel_image_format_lookup(int fourcc
)
416 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
417 if (intel_image_formats
[i
].fourcc
== fourcc
)
418 return &intel_image_formats
[i
];
425 intel_image_get_fourcc(__DRIimage
*image
, int *fourcc
)
427 if (image
->planar_format
) {
428 *fourcc
= image
->planar_format
->fourcc
;
432 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
433 if (intel_image_formats
[i
].planes
[0].dri_format
== image
->dri_format
) {
434 *fourcc
= intel_image_formats
[i
].fourcc
;
442 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
447 image
= calloc(1, sizeof *image
);
451 image
->screen
= screen
;
452 image
->dri_format
= dri_format
;
455 image
->format
= driImageFormatToGLFormat(dri_format
);
456 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
457 image
->format
== MESA_FORMAT_NONE
) {
462 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
463 image
->data
= loaderPrivate
;
469 * Sets up a DRIImage structure to point to a slice out of a miptree.
472 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
473 struct intel_mipmap_tree
*mt
, GLuint level
,
476 intel_miptree_make_shareable(brw
, mt
);
478 intel_miptree_check_level_layer(mt
, level
, zoffset
);
480 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
481 level
- mt
->first_level
);
482 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
483 level
- mt
->first_level
);
484 image
->pitch
= mt
->surf
.row_pitch_B
;
486 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
490 brw_bo_unreference(image
->bo
);
492 brw_bo_reference(mt
->bo
);
496 intel_create_image_from_name(__DRIscreen
*dri_screen
,
497 int width
, int height
, int format
,
498 int name
, int pitch
, void *loaderPrivate
)
500 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
504 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
508 if (image
->format
== MESA_FORMAT_NONE
)
511 cpp
= _mesa_get_format_bytes(image
->format
);
513 image
->width
= width
;
514 image
->height
= height
;
515 image
->pitch
= pitch
* cpp
;
516 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
522 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
528 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
529 int renderbuffer
, void *loaderPrivate
)
532 struct brw_context
*brw
= context
->driverPrivate
;
533 struct gl_context
*ctx
= &brw
->ctx
;
534 struct gl_renderbuffer
*rb
;
535 struct intel_renderbuffer
*irb
;
537 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
539 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
543 irb
= intel_renderbuffer(rb
);
544 intel_miptree_make_shareable(brw
, irb
->mt
);
545 image
= calloc(1, sizeof *image
);
549 image
->internal_format
= rb
->InternalFormat
;
550 image
->format
= rb
->Format
;
551 image
->modifier
= tiling_to_modifier(
552 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
554 image
->data
= loaderPrivate
;
555 brw_bo_unreference(image
->bo
);
556 image
->bo
= irb
->mt
->bo
;
557 brw_bo_reference(irb
->mt
->bo
);
558 image
->width
= rb
->Width
;
559 image
->height
= rb
->Height
;
560 image
->pitch
= irb
->mt
->surf
.row_pitch_B
;
561 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
562 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
564 rb
->NeedsFinishRenderTexture
= true;
569 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
570 unsigned texture
, int zoffset
,
576 struct brw_context
*brw
= context
->driverPrivate
;
577 struct gl_texture_object
*obj
;
578 struct intel_texture_object
*iobj
;
581 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
582 if (!obj
|| obj
->Target
!= target
) {
583 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
587 if (target
== GL_TEXTURE_CUBE_MAP
)
590 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
591 iobj
= intel_texture_object(obj
);
592 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
593 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
597 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
598 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
602 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
603 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
606 image
= calloc(1, sizeof *image
);
608 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
612 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
613 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
614 image
->modifier
= tiling_to_modifier(
615 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
616 image
->data
= loaderPrivate
;
617 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
618 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
619 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
620 image
->planar_format
= iobj
->planar_format
;
621 if (image
->dri_format
== __DRI_IMAGE_FORMAT_NONE
) {
622 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
627 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
632 intel_destroy_image(__DRIimage
*image
)
634 brw_bo_unreference(image
->bo
);
638 enum modifier_priority
{
639 MODIFIER_PRIORITY_INVALID
= 0,
640 MODIFIER_PRIORITY_LINEAR
,
643 MODIFIER_PRIORITY_Y_CCS
,
646 const uint64_t priority_to_modifier
[] = {
647 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
648 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
649 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
650 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
651 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
655 select_best_modifier(struct gen_device_info
*devinfo
,
657 const uint64_t *modifiers
,
658 const unsigned count
)
660 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
662 for (int i
= 0; i
< count
; i
++) {
663 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
666 switch (modifiers
[i
]) {
667 case I915_FORMAT_MOD_Y_TILED_CCS
:
668 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
670 case I915_FORMAT_MOD_Y_TILED
:
671 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
673 case I915_FORMAT_MOD_X_TILED
:
674 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
676 case DRM_FORMAT_MOD_LINEAR
:
677 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
679 case DRM_FORMAT_MOD_INVALID
:
685 return priority_to_modifier
[prio
];
689 intel_create_image_common(__DRIscreen
*dri_screen
,
690 int width
, int height
, int format
,
692 const uint64_t *modifiers
,
697 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
698 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
701 /* Callers of this may specify a modifier, or a dri usage, but not both. The
702 * newer modifier interface deprecates the older usage flags newer modifier
703 * interface deprecates the older usage flags.
705 assert(!(use
&& count
));
707 if (use
& __DRI_IMAGE_USE_CURSOR
) {
708 if (width
!= 64 || height
!= 64)
710 modifier
= DRM_FORMAT_MOD_LINEAR
;
713 if (use
& __DRI_IMAGE_USE_LINEAR
)
714 modifier
= DRM_FORMAT_MOD_LINEAR
;
716 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
718 /* User requested specific modifiers */
719 modifier
= select_best_modifier(&screen
->devinfo
, format
,
721 if (modifier
== DRM_FORMAT_MOD_INVALID
)
724 /* Historically, X-tiled was the default, and so lack of modifier means
727 modifier
= I915_FORMAT_MOD_X_TILED
;
731 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
735 const struct isl_drm_modifier_info
*mod_info
=
736 isl_drm_modifier_get_info(modifier
);
738 struct isl_surf surf
;
739 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
740 .dim
= ISL_SURF_DIM_2D
,
741 .format
= brw_isl_format_for_mesa_format(image
->format
),
748 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
749 ISL_SURF_USAGE_TEXTURE_BIT
|
750 ISL_SURF_USAGE_STORAGE_BIT
,
751 .tiling_flags
= (1 << mod_info
->tiling
));
758 struct isl_surf aux_surf
;
759 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
760 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, 0);
766 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
770 /* We request that the bufmgr zero the buffer for us for two reasons:
772 * 1) If a buffer gets re-used from the pool, we don't want to leak random
773 * garbage from our process to some other.
775 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
776 * a valid state. A CCS value of 0 indicates that the given block is
777 * in the pass-through state which is what we want.
779 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
780 surf
.size_B
+ aux_surf
.size_B
,
782 isl_tiling_to_i915_tiling(mod_info
->tiling
),
783 surf
.row_pitch_B
, BO_ALLOC_ZEROED
);
784 if (image
->bo
== NULL
) {
788 image
->width
= width
;
789 image
->height
= height
;
790 image
->pitch
= surf
.row_pitch_B
;
791 image
->modifier
= modifier
;
793 if (aux_surf
.size_B
) {
794 image
->aux_offset
= surf
.size_B
;
795 image
->aux_pitch
= aux_surf
.row_pitch_B
;
796 image
->aux_size
= aux_surf
.size_B
;
803 intel_create_image(__DRIscreen
*dri_screen
,
804 int width
, int height
, int format
,
808 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
813 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
814 int x0
, int y0
, int width
, int height
,
815 unsigned int flags
, int *stride
, void **map_info
)
817 struct brw_context
*brw
= NULL
;
818 struct brw_bo
*bo
= NULL
;
819 void *raw_data
= NULL
;
824 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
827 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
830 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
833 if (flags
& MAP_INTERNAL_MASK
)
836 brw
= context
->driverPrivate
;
842 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
843 raw_data
= brw_bo_map(brw
, bo
, flags
);
847 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
848 pix_bytes
= _mesa_get_format_bytes(image
->format
);
852 assert(pix_bytes
> 0);
854 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
856 brw_bo_reference(bo
);
858 *stride
= image
->pitch
;
865 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
867 struct brw_bo
*bo
= map_info
;
870 brw_bo_unreference(bo
);
874 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
875 int width
, int height
, int format
,
876 const uint64_t *modifiers
,
877 const unsigned count
,
880 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
881 modifiers
, count
, loaderPrivate
);
885 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
888 case __DRI_IMAGE_ATTRIB_STRIDE
:
889 *value
= image
->pitch
;
891 case __DRI_IMAGE_ATTRIB_HANDLE
:
892 *value
= brw_bo_export_gem_handle(image
->bo
);
894 case __DRI_IMAGE_ATTRIB_NAME
:
895 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
896 case __DRI_IMAGE_ATTRIB_FORMAT
:
897 *value
= image
->dri_format
;
899 case __DRI_IMAGE_ATTRIB_WIDTH
:
900 *value
= image
->width
;
902 case __DRI_IMAGE_ATTRIB_HEIGHT
:
903 *value
= image
->height
;
905 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
906 if (image
->planar_format
== NULL
)
908 *value
= image
->planar_format
->components
;
910 case __DRI_IMAGE_ATTRIB_FD
:
911 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
912 case __DRI_IMAGE_ATTRIB_FOURCC
:
913 return intel_image_get_fourcc(image
, value
);
914 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
915 if (isl_drm_modifier_has_aux(image
->modifier
)) {
916 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
918 } else if (image
->planar_format
) {
919 *value
= image
->planar_format
->nplanes
;
924 case __DRI_IMAGE_ATTRIB_OFFSET
:
925 *value
= image
->offset
;
927 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
928 *value
= (image
->modifier
& 0xffffffff);
930 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
931 *value
= ((image
->modifier
>> 32) & 0xffffffff);
940 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
941 uint32_t fourcc
, uint64_t modifier
,
942 int attrib
, uint64_t *value
)
944 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
945 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
947 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
951 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
952 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
961 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
965 image
= calloc(1, sizeof *image
);
969 brw_bo_reference(orig_image
->bo
);
970 image
->bo
= orig_image
->bo
;
971 image
->internal_format
= orig_image
->internal_format
;
972 image
->planar_format
= orig_image
->planar_format
;
973 image
->dri_format
= orig_image
->dri_format
;
974 image
->format
= orig_image
->format
;
975 image
->modifier
= orig_image
->modifier
;
976 image
->offset
= orig_image
->offset
;
977 image
->width
= orig_image
->width
;
978 image
->height
= orig_image
->height
;
979 image
->pitch
= orig_image
->pitch
;
980 image
->tile_x
= orig_image
->tile_x
;
981 image
->tile_y
= orig_image
->tile_y
;
982 image
->has_depthstencil
= orig_image
->has_depthstencil
;
983 image
->data
= loaderPrivate
;
984 image
->aux_offset
= orig_image
->aux_offset
;
985 image
->aux_pitch
= orig_image
->aux_pitch
;
987 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
988 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
994 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
996 if (use
& __DRI_IMAGE_USE_CURSOR
) {
997 if (image
->width
!= 64 || image
->height
!= 64)
1005 intel_create_image_from_names(__DRIscreen
*dri_screen
,
1006 int width
, int height
, int fourcc
,
1007 int *names
, int num_names
,
1008 int *strides
, int *offsets
,
1009 void *loaderPrivate
)
1011 const struct intel_image_format
*f
= NULL
;
1015 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
1018 f
= intel_image_format_lookup(fourcc
);
1022 image
= intel_create_image_from_name(dri_screen
, width
, height
,
1023 __DRI_IMAGE_FORMAT_NONE
,
1024 names
[0], strides
[0],
1030 image
->planar_format
= f
;
1031 for (i
= 0; i
< f
->nplanes
; i
++) {
1032 index
= f
->planes
[i
].buffer_index
;
1033 image
->offsets
[index
] = offsets
[index
];
1034 image
->strides
[index
] = strides
[index
];
1041 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1042 int width
, int height
, int fourcc
,
1043 uint64_t modifier
, int *fds
, int num_fds
,
1044 int *strides
, int *offsets
,
1045 void *loaderPrivate
)
1047 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1048 const struct intel_image_format
*f
;
1053 if (fds
== NULL
|| num_fds
< 1)
1056 f
= intel_image_format_lookup(fourcc
);
1060 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1061 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1064 if (f
->nplanes
== 1)
1065 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1068 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1074 image
->width
= width
;
1075 image
->height
= height
;
1076 image
->pitch
= strides
[0];
1078 image
->planar_format
= f
;
1080 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1081 const struct isl_drm_modifier_info
*mod_info
=
1082 isl_drm_modifier_get_info(modifier
);
1083 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1084 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1085 tiling
, strides
[0]);
1087 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1090 if (image
->bo
== NULL
) {
1095 /* We only support all planes from the same bo.
1096 * brw_bo_gem_create_from_prime() should return the same pointer for all
1097 * fds received here */
1098 for (i
= 1; i
< num_fds
; i
++) {
1099 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1100 brw_bo_unreference(aux
);
1101 if (aux
!= image
->bo
) {
1102 brw_bo_unreference(image
->bo
);
1108 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1109 image
->modifier
= modifier
;
1111 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1113 const struct isl_drm_modifier_info
*mod_info
=
1114 isl_drm_modifier_get_info(image
->modifier
);
1117 struct isl_surf surf
;
1118 for (i
= 0; i
< f
->nplanes
; i
++) {
1119 index
= f
->planes
[i
].buffer_index
;
1120 image
->offsets
[index
] = offsets
[index
];
1121 image
->strides
[index
] = strides
[index
];
1123 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1124 /* The images we will create are actually based on the RGBA non-sRGB
1125 * version of the format.
1127 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1128 format
= _mesa_get_srgb_format_linear(format
);
1130 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1131 .dim
= ISL_SURF_DIM_2D
,
1132 .format
= brw_isl_format_for_mesa_format(format
),
1133 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1134 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1139 .row_pitch_B
= strides
[index
],
1140 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1141 ISL_SURF_USAGE_TEXTURE_BIT
|
1142 ISL_SURF_USAGE_STORAGE_BIT
,
1143 .tiling_flags
= (1 << mod_info
->tiling
));
1145 brw_bo_unreference(image
->bo
);
1150 const int end
= offsets
[index
] + surf
.size_B
;
1155 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1156 /* Even though we initialize surf in the loop above, we know that
1157 * anything with CCS_E will have exactly one plane so surf is properly
1158 * initialized when we get here.
1160 assert(f
->nplanes
== 1);
1162 image
->aux_offset
= offsets
[1];
1163 image
->aux_pitch
= strides
[1];
1165 /* Scanout hardware requires that the CCS be placed after the main
1166 * surface in memory. We consider any CCS that is placed any earlier in
1167 * memory to be invalid and reject it.
1169 * At some point in the future, this restriction may be relaxed if the
1170 * hardware becomes less strict but we may need a new modifier for that.
1173 if (image
->aux_offset
< size
) {
1174 brw_bo_unreference(image
->bo
);
1179 struct isl_surf aux_surf
;
1180 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
,
1183 brw_bo_unreference(image
->bo
);
1188 image
->aux_size
= aux_surf
.size_B
;
1190 const int end
= image
->aux_offset
+ aux_surf
.size_B
;
1194 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1197 /* Check that the requested image actually fits within the BO. 'size'
1198 * is already relative to the offsets, so we don't need to add that. */
1199 if (image
->bo
->size
== 0) {
1200 image
->bo
->size
= size
;
1201 } else if (size
> image
->bo
->size
) {
1202 brw_bo_unreference(image
->bo
);
1207 if (f
->nplanes
== 1) {
1208 image
->offset
= image
->offsets
[0];
1209 intel_image_warn_if_unaligned(image
, __func__
);
1216 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1217 int width
, int height
, int fourcc
,
1218 int *fds
, int num_fds
, int *strides
, int *offsets
,
1219 void *loaderPrivate
)
1221 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1222 DRM_FORMAT_MOD_INVALID
,
1223 fds
, num_fds
, strides
, offsets
,
1228 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1229 int width
, int height
,
1230 int fourcc
, uint64_t modifier
,
1231 int *fds
, int num_fds
,
1232 int *strides
, int *offsets
,
1233 enum __DRIYUVColorSpace yuv_color_space
,
1234 enum __DRISampleRange sample_range
,
1235 enum __DRIChromaSiting horizontal_siting
,
1236 enum __DRIChromaSiting vertical_siting
,
1238 void *loaderPrivate
)
1241 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1244 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1248 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1250 fds
, num_fds
, strides
, offsets
,
1254 * Invalid parameters and any inconsistencies between are assumed to be
1255 * checked by the caller. Therefore besides unsupported formats one can fail
1256 * only in allocation.
1259 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1263 image
->yuv_color_space
= yuv_color_space
;
1264 image
->sample_range
= sample_range
;
1265 image
->horizontal_siting
= horizontal_siting
;
1266 image
->vertical_siting
= vertical_siting
;
1268 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1273 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1274 int width
, int height
, int fourcc
,
1275 int *fds
, int num_fds
,
1276 int *strides
, int *offsets
,
1277 enum __DRIYUVColorSpace yuv_color_space
,
1278 enum __DRISampleRange sample_range
,
1279 enum __DRIChromaSiting horizontal_siting
,
1280 enum __DRIChromaSiting vertical_siting
,
1282 void *loaderPrivate
)
1284 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1285 fourcc
, DRM_FORMAT_MOD_INVALID
,
1286 fds
, num_fds
, strides
, offsets
,
1296 intel_image_format_is_supported(const struct gen_device_info
*devinfo
,
1297 const struct intel_image_format
*fmt
)
1299 /* Currently, all formats with an intel_image_format are available on all
1300 * platforms so there's really nothing to check there.
1304 if (fmt
->nplanes
== 1) {
1305 mesa_format format
= driImageFormatToGLFormat(fmt
->planes
[0].dri_format
);
1306 /* The images we will create are actually based on the RGBA non-sRGB
1307 * version of the format.
1309 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1310 format
= _mesa_get_srgb_format_linear(format
);
1311 enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
1312 assert(isl_format_supports_rendering(devinfo
, isl_format
));
1320 intel_query_dma_buf_formats(__DRIscreen
*_screen
, int max
,
1321 int *formats
, int *count
)
1323 struct intel_screen
*screen
= _screen
->driverPrivate
;
1324 int num_formats
= 0, i
;
1326 for (i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
1327 /* These two formats are valid DRI formats but do not exist in
1328 * drm_fourcc.h in the Linux kernel. We don't want to accidentally
1329 * advertise them through the EGL layer.
1331 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
||
1332 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SABGR8888
)
1335 if (!intel_image_format_is_supported(&screen
->devinfo
,
1336 &intel_image_formats
[i
]))
1343 formats
[num_formats
- 1] = intel_image_formats
[i
].fourcc
;
1344 if (num_formats
>= max
)
1348 *count
= num_formats
;
1353 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1354 uint64_t *modifiers
,
1355 unsigned int *external_only
,
1358 struct intel_screen
*screen
= _screen
->driverPrivate
;
1359 const struct intel_image_format
*f
;
1360 int num_mods
= 0, i
;
1362 f
= intel_image_format_lookup(fourcc
);
1366 if (!intel_image_format_is_supported(&screen
->devinfo
, f
))
1369 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1370 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1371 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1378 modifiers
[num_mods
- 1] = modifier
;
1379 if (num_mods
>= max
)
1383 if (external_only
!= NULL
) {
1384 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1385 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1386 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1387 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
||
1388 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UXVX
) {
1389 external_only
[i
] = GL_TRUE
;
1392 external_only
[i
] = GL_FALSE
;
1402 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1404 int width
, height
, offset
, stride
, size
, dri_format
;
1410 width
= parent
->width
;
1411 height
= parent
->height
;
1413 const struct intel_image_format
*f
= parent
->planar_format
;
1415 if (f
&& plane
< f
->nplanes
) {
1416 /* Use the planar format definition. */
1417 width
>>= f
->planes
[plane
].width_shift
;
1418 height
>>= f
->planes
[plane
].height_shift
;
1419 dri_format
= f
->planes
[plane
].dri_format
;
1420 int index
= f
->planes
[plane
].buffer_index
;
1421 offset
= parent
->offsets
[index
];
1422 stride
= parent
->strides
[index
];
1423 size
= height
* stride
;
1424 } else if (plane
== 0) {
1425 /* The only plane of a non-planar image: copy the parent definition
1427 dri_format
= parent
->dri_format
;
1428 offset
= parent
->offset
;
1429 stride
= parent
->pitch
;
1430 size
= height
* stride
;
1431 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1432 isl_drm_modifier_has_aux(parent
->modifier
)) {
1433 /* Auxiliary plane */
1434 dri_format
= parent
->dri_format
;
1435 offset
= parent
->aux_offset
;
1436 stride
= parent
->aux_pitch
;
1437 size
= parent
->aux_size
;
1442 if (offset
+ size
> parent
->bo
->size
) {
1443 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1447 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1451 image
->bo
= parent
->bo
;
1452 brw_bo_reference(parent
->bo
);
1453 image
->modifier
= parent
->modifier
;
1455 image
->width
= width
;
1456 image
->height
= height
;
1457 image
->pitch
= stride
;
1458 image
->offset
= offset
;
1460 intel_image_warn_if_unaligned(image
, __func__
);
1465 static const __DRIimageExtension intelImageExtension
= {
1466 .base
= { __DRI_IMAGE
, 16 },
1468 .createImageFromName
= intel_create_image_from_name
,
1469 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1470 .destroyImage
= intel_destroy_image
,
1471 .createImage
= intel_create_image
,
1472 .queryImage
= intel_query_image
,
1473 .dupImage
= intel_dup_image
,
1474 .validateUsage
= intel_validate_usage
,
1475 .createImageFromNames
= intel_create_image_from_names
,
1476 .fromPlanar
= intel_from_planar
,
1477 .createImageFromTexture
= intel_create_image_from_texture
,
1478 .createImageFromFds
= intel_create_image_from_fds
,
1479 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1481 .getCapabilities
= NULL
,
1482 .mapImage
= intel_map_image
,
1483 .unmapImage
= intel_unmap_image
,
1484 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1485 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1486 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1487 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1488 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1492 get_aperture_size(int fd
)
1494 struct drm_i915_gem_get_aperture aperture
;
1496 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1499 return aperture
.aper_size
;
1503 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1504 int param
, unsigned int *value
)
1506 const struct intel_screen
*const screen
=
1507 (struct intel_screen
*) dri_screen
->driverPrivate
;
1510 case __DRI2_RENDERER_VENDOR_ID
:
1513 case __DRI2_RENDERER_DEVICE_ID
:
1514 value
[0] = screen
->deviceID
;
1516 case __DRI2_RENDERER_ACCELERATED
:
1519 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1520 /* Once a batch uses more than 75% of the maximum mappable size, we
1521 * assume that there's some fragmentation, and we start doing extra
1522 * flushing, etc. That's the big cliff apps will care about.
1524 const unsigned gpu_mappable_megabytes
=
1525 screen
->aperture_threshold
/ (1024 * 1024);
1527 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1528 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1530 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1533 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1534 * (uint64_t) system_page_size
;
1536 const unsigned system_memory_megabytes
=
1537 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1539 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1542 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1545 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1548 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1550 if (brw_hw_context_set_priority(screen
->bufmgr
,
1551 0, GEN_CONTEXT_HIGH_PRIORITY
) == 0)
1552 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1553 if (brw_hw_context_set_priority(screen
->bufmgr
,
1554 0, GEN_CONTEXT_LOW_PRIORITY
) == 0)
1555 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1556 /* reset to default last, just in case */
1557 if (brw_hw_context_set_priority(screen
->bufmgr
,
1558 0, GEN_CONTEXT_MEDIUM_PRIORITY
) == 0)
1559 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1561 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1565 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1572 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1573 int param
, const char **value
)
1575 const struct intel_screen
*screen
=
1576 (struct intel_screen
*) dri_screen
->driverPrivate
;
1579 case __DRI2_RENDERER_VENDOR_ID
:
1580 value
[0] = brw_vendor_string
;
1582 case __DRI2_RENDERER_DEVICE_ID
:
1583 value
[0] = brw_get_renderer_string(screen
);
1593 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1594 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1596 const struct intel_screen
*const screen
=
1597 (struct intel_screen
*) dri_screen
->driverPrivate
;
1599 if (!screen
->disk_cache
)
1602 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1605 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1606 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1608 .queryInteger
= brw_query_renderer_integer
,
1609 .queryString
= brw_query_renderer_string
1612 static const __DRIrobustnessExtension dri2Robustness
= {
1613 .base
= { __DRI2_ROBUSTNESS
, 1 }
1616 static const __DRI2blobExtension intelBlobExtension
= {
1617 .base
= { __DRI2_BLOB
, 1 },
1618 .set_cache_funcs
= brw_set_cache_funcs
1621 static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension
= {
1622 .base
= { __DRI_MUTABLE_RENDER_BUFFER_DRIVER
, 1 },
1625 static const __DRIextension
*screenExtensions
[] = {
1626 &intelTexBufferExtension
.base
,
1627 &intelFenceExtension
.base
,
1628 &intelFlushExtension
.base
,
1629 &intelImageExtension
.base
,
1630 &intelRendererQueryExtension
.base
,
1631 &intelMutableRenderBufferExtension
.base
,
1632 &dri2ConfigQueryExtension
.base
,
1633 &dri2NoErrorExtension
.base
,
1634 &intelBlobExtension
.base
,
1638 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1639 &intelTexBufferExtension
.base
,
1640 &intelFenceExtension
.base
,
1641 &intelFlushExtension
.base
,
1642 &intelImageExtension
.base
,
1643 &intelRendererQueryExtension
.base
,
1644 &intelMutableRenderBufferExtension
.base
,
1645 &dri2ConfigQueryExtension
.base
,
1646 &dri2Robustness
.base
,
1647 &dri2NoErrorExtension
.base
,
1648 &intelBlobExtension
.base
,
1653 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1656 struct drm_i915_getparam gp
;
1658 memset(&gp
, 0, sizeof(gp
));
1662 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1665 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1672 intel_get_boolean(struct intel_screen
*screen
, int param
)
1675 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1679 intel_get_integer(struct intel_screen
*screen
, int param
)
1683 if (intel_get_param(screen
, param
, &value
) == 0)
1690 intelDestroyScreen(__DRIscreen
* sPriv
)
1692 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1694 brw_bufmgr_destroy(screen
->bufmgr
);
1695 driDestroyOptionInfo(&screen
->optionCache
);
1697 disk_cache_destroy(screen
->disk_cache
);
1699 ralloc_free(screen
);
1700 sPriv
->driverPrivate
= NULL
;
1705 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1707 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1708 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1709 * this does not allocate GPU memory.
1712 intelCreateBuffer(__DRIscreen
*dri_screen
,
1713 __DRIdrawable
* driDrawPriv
,
1714 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1716 struct intel_renderbuffer
*rb
;
1717 struct intel_screen
*screen
= (struct intel_screen
*)
1718 dri_screen
->driverPrivate
;
1719 mesa_format rgbFormat
;
1720 unsigned num_samples
=
1721 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1726 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1730 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1732 if (screen
->winsys_msaa_samples_override
!= -1) {
1733 num_samples
= screen
->winsys_msaa_samples_override
;
1734 fb
->Visual
.samples
= num_samples
;
1737 if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1738 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1739 : MESA_FORMAT_R10G10B10A2_UNORM
;
1740 } else if (mesaVis
->redBits
== 10) {
1741 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1742 : MESA_FORMAT_R10G10B10X2_UNORM
;
1743 } else if (mesaVis
->redBits
== 5) {
1744 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1745 : MESA_FORMAT_B5G6R5_UNORM
;
1746 } else if (mesaVis
->sRGBCapable
) {
1747 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1748 : MESA_FORMAT_B8G8R8A8_SRGB
;
1749 } else if (mesaVis
->alphaBits
== 0) {
1750 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1751 : MESA_FORMAT_B8G8R8X8_UNORM
;
1753 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1754 : MESA_FORMAT_B8G8R8A8_SRGB
;
1755 fb
->Visual
.sRGBCapable
= true;
1758 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1759 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1761 /* setup the hardware-based renderbuffers */
1762 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1763 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1764 rb
->need_srgb
= srgb_cap_set
;
1766 if (mesaVis
->doubleBufferMode
) {
1767 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1768 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1769 rb
->need_srgb
= srgb_cap_set
;
1773 * Assert here that the gl_config has an expected depth/stencil bit
1774 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1775 * which constructs the advertised configs.)
1777 if (mesaVis
->depthBits
== 24) {
1778 assert(mesaVis
->stencilBits
== 8);
1780 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1781 rb
= intel_create_private_renderbuffer(screen
,
1782 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1784 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1785 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1787 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1790 * Use combined depth/stencil. Note that the renderbuffer is
1791 * attached to two attachment points.
1793 rb
= intel_create_private_renderbuffer(screen
,
1794 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1796 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1797 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1800 else if (mesaVis
->depthBits
== 16) {
1801 assert(mesaVis
->stencilBits
== 0);
1802 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1804 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1807 assert(mesaVis
->depthBits
== 0);
1808 assert(mesaVis
->stencilBits
== 0);
1811 /* now add any/all software-based renderbuffers we may need */
1812 _swrast_add_soft_renderbuffers(fb
,
1813 false, /* never sw color */
1814 false, /* never sw depth */
1815 false, /* never sw stencil */
1816 mesaVis
->accumRedBits
> 0,
1817 false, /* never sw alpha */
1818 false /* never sw aux */ );
1819 driDrawPriv
->driverPrivate
= fb
;
1825 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1827 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1829 _mesa_reference_framebuffer(&fb
, NULL
);
1833 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1835 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1836 * gen10, PCI-id is enough to figure it out.
1838 assert(screen
->devinfo
.gen
>= 10);
1842 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1846 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1850 screen
->devinfo
.timestamp_frequency
= freq
;
1854 intel_detect_sseu(struct intel_screen
*screen
)
1856 assert(screen
->devinfo
.gen
>= 8);
1859 screen
->subslice_total
= -1;
1860 screen
->eu_total
= -1;
1862 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1863 &screen
->subslice_total
);
1864 if (ret
< 0 && ret
!= -EINVAL
)
1867 ret
= intel_get_param(screen
,
1868 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1869 if (ret
< 0 && ret
!= -EINVAL
)
1872 /* Without this information, we cannot get the right Braswell brandstrings,
1873 * and we have to use conservative numbers for GPGPU on many platforms, but
1874 * otherwise, things will just work.
1876 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1878 "Kernel 4.1 required to properly query GPU properties.\n");
1883 screen
->subslice_total
= -1;
1884 screen
->eu_total
= -1;
1885 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1889 intel_init_bufmgr(struct intel_screen
*screen
)
1891 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1893 if (getenv("INTEL_NO_HW") != NULL
)
1894 screen
->no_hw
= true;
1896 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
);
1897 if (screen
->bufmgr
== NULL
) {
1898 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1899 __func__
, __LINE__
);
1903 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1904 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1912 intel_detect_swizzling(struct intel_screen
*screen
)
1914 /* Broadwell PRM says:
1916 * "Before Gen8, there was a historical configuration control field to
1917 * swizzle address bit[6] for in X/Y tiling modes. This was set in three
1918 * different places: TILECTL[1:0], ARB_MODE[5:4], and
1919 * DISP_ARB_CTL[14:13].
1921 * For Gen8 and subsequent generations, the swizzle fields are all
1922 * reserved, and the CPU's memory controller performs all address
1923 * swizzling modifications."
1925 if (screen
->devinfo
.gen
>= 8)
1928 uint32_t tiling
= I915_TILING_X
;
1929 uint32_t swizzle_mode
= 0;
1930 struct brw_bo
*buffer
=
1931 brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test", 32768,
1932 BRW_MEMZONE_OTHER
, tiling
, 512, 0);
1936 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1937 brw_bo_unreference(buffer
);
1939 return swizzle_mode
!= I915_BIT_6_SWIZZLE_NONE
;
1943 intel_detect_timestamp(struct intel_screen
*screen
)
1945 uint64_t dummy
= 0, last
= 0;
1946 int upper
, lower
, loops
;
1948 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1949 * TIMESTAMP register being shifted and the low 32bits always zero.
1951 * More recent kernels offer an interface to read the full 36bits
1954 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1957 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1958 * upper 32bits for a rapidly changing timestamp.
1960 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1964 for (loops
= 0; loops
< 10; loops
++) {
1965 /* The TIMESTAMP should change every 80ns, so several round trips
1966 * through the kernel should be enough to advance it.
1968 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1971 upper
+= (dummy
>> 32) != (last
>> 32);
1972 if (upper
> 1) /* beware 32bit counter overflow */
1973 return 2; /* upper dword holds the low 32bits of the timestamp */
1975 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1977 return 1; /* timestamp is unshifted */
1982 /* No advancement? No timestamp! */
1987 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1989 * Some combinations of hardware and kernel versions allow this feature,
1990 * while others don't. Instead of trying to enumerate every case, just
1991 * try and write a register and see if works.
1994 intel_detect_pipelined_register(struct intel_screen
*screen
,
1995 int reg
, uint32_t expected_value
, bool reset
)
2000 struct brw_bo
*results
, *bo
;
2002 uint32_t offset
= 0;
2004 bool success
= false;
2006 /* Create a zero'ed temporary buffer for reading our results */
2007 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, BRW_MEMZONE_OTHER
);
2008 if (results
== NULL
)
2011 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, BRW_MEMZONE_OTHER
);
2015 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
2021 /* Write the register. */
2022 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2024 *batch
++ = expected_value
;
2026 /* Save the register's value back to the buffer. */
2027 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
2029 struct drm_i915_gem_relocation_entry reloc
= {
2030 .offset
= (char *) batch
- (char *) map
,
2031 .delta
= offset
* sizeof(uint32_t),
2032 .target_handle
= results
->gem_handle
,
2033 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
2034 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
2036 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
2038 /* And afterwards clear the register */
2040 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2045 *batch
++ = MI_BATCH_BUFFER_END
;
2047 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
2049 .handle
= results
->gem_handle
,
2052 .handle
= bo
->gem_handle
,
2053 .relocation_count
= 1,
2054 .relocs_ptr
= (uintptr_t) &reloc
,
2058 struct drm_i915_gem_execbuffer2 execbuf
= {
2059 .buffers_ptr
= (uintptr_t) exec_objects
,
2061 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
2062 .flags
= I915_EXEC_RENDER
,
2065 /* Don't bother with error checking - if the execbuf fails, the
2066 * value won't be written and we'll just report that there's no access.
2068 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2069 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
2071 /* Check whether the value got written. */
2072 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
2074 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
2075 brw_bo_unmap(results
);
2079 brw_bo_unreference(bo
);
2081 brw_bo_unreference(results
);
2087 intel_detect_pipelined_so(struct intel_screen
*screen
)
2089 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2091 /* Supposedly, Broadwell just works. */
2092 if (devinfo
->gen
>= 8)
2095 if (devinfo
->gen
<= 6)
2098 /* See the big explanation about command parser versions below */
2099 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2102 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2103 * statistics registers), and we already reset it to zero before using it.
2105 return intel_detect_pipelined_register(screen
,
2106 GEN7_SO_WRITE_OFFSET(0),
2112 * Return array of MSAA modes supported by the hardware. The array is
2113 * zero-terminated and sorted in decreasing order.
2116 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2118 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2119 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2120 static const int gen7_modes
[] = {8, 4, 0, -1};
2121 static const int gen6_modes
[] = {4, 0, -1};
2122 static const int gen4_modes
[] = {0, -1};
2124 if (screen
->devinfo
.gen
>= 9) {
2126 } else if (screen
->devinfo
.gen
>= 8) {
2128 } else if (screen
->devinfo
.gen
>= 7) {
2130 } else if (screen
->devinfo
.gen
== 6) {
2138 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2140 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2141 dri_screen
->dri2
.loader
->getCapability
)
2142 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2144 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2145 dri_screen
->image
.loader
->getCapability
)
2146 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2151 static __DRIconfig
**
2152 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2154 static const mesa_format formats
[] = {
2155 MESA_FORMAT_B5G6R5_UNORM
,
2156 MESA_FORMAT_B8G8R8A8_UNORM
,
2157 MESA_FORMAT_B8G8R8X8_UNORM
,
2159 MESA_FORMAT_B8G8R8A8_SRGB
,
2161 /* For 10 bpc, 30 bit depth framebuffers. */
2162 MESA_FORMAT_B10G10R10A2_UNORM
,
2163 MESA_FORMAT_B10G10R10X2_UNORM
,
2165 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2166 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2167 * server may disagree on which format the GLXFBConfig represents,
2168 * resulting in swapped color channels.
2170 * The problem, as of 2017-05-30:
2171 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2172 * order and chooses the first __DRIconfig with the expected channel
2173 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2174 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2176 * EGL does not suffer from this problem. It correctly compares the
2177 * channel masks when matching EGLConfig to __DRIconfig.
2180 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2181 MESA_FORMAT_R8G8B8A8_UNORM
,
2183 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2184 MESA_FORMAT_R8G8B8X8_UNORM
,
2186 MESA_FORMAT_R8G8B8A8_SRGB
,
2189 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
2190 static const GLenum back_buffer_modes
[] = {
2191 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2194 static const uint8_t singlesample_samples
[1] = {0};
2196 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2197 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2198 uint8_t depth_bits
[4], stencil_bits
[4];
2199 __DRIconfig
**configs
= NULL
;
2201 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2202 unsigned num_formats
;
2203 if (intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
))
2204 num_formats
= ARRAY_SIZE(formats
);
2206 num_formats
= ARRAY_SIZE(formats
) - 3; /* all - RGBA_ORDERING formats */
2208 /* Shall we expose 10 bpc formats? */
2209 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2210 "allow_rgb10_configs");
2211 /* Shall we expose 565 formats? */
2212 bool allow_rgb565_configs
= driQueryOptionb(&screen
->optionCache
,
2213 "allow_rgb565_configs");
2215 /* Generate singlesample configs, each without accumulation buffer
2216 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
2218 for (unsigned i
= 0; i
< num_formats
; i
++) {
2219 __DRIconfig
**new_configs
;
2220 int num_depth_stencil_bits
= 2;
2222 if (!allow_rgb10_configs
&&
2223 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2224 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2227 if (!allow_rgb565_configs
&& formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
)
2230 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2231 * buffer that has a different number of bits per pixel than the color
2232 * buffer, gen >= 6 supports this.
2235 stencil_bits
[0] = 0;
2237 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2239 stencil_bits
[1] = 0;
2240 if (devinfo
->gen
>= 6) {
2242 stencil_bits
[2] = 8;
2243 num_depth_stencil_bits
= 3;
2247 stencil_bits
[1] = 8;
2250 new_configs
= driCreateConfigs(formats
[i
],
2253 num_depth_stencil_bits
,
2254 back_buffer_modes
, 2,
2255 singlesample_samples
, 1,
2257 /*mutable_render_buffer*/ true);
2258 configs
= driConcatConfigs(configs
, new_configs
);
2261 /* Generate the minimum possible set of configs that include an
2262 * accumulation buffer.
2264 for (unsigned i
= 0; i
< num_formats
; i
++) {
2265 __DRIconfig
**new_configs
;
2267 if (!allow_rgb10_configs
&&
2268 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2269 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2272 if (!allow_rgb565_configs
&& formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
)
2275 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2277 stencil_bits
[0] = 0;
2280 stencil_bits
[0] = 8;
2283 new_configs
= driCreateConfigs(formats
[i
],
2284 depth_bits
, stencil_bits
, 1,
2285 back_buffer_modes
, 1,
2286 singlesample_samples
, 1,
2287 true, false, false);
2288 configs
= driConcatConfigs(configs
, new_configs
);
2291 /* Generate multisample configs.
2293 * This loop breaks early, and hence is a no-op, on gen < 6.
2295 * Multisample configs must follow the singlesample configs in order to
2296 * work around an X server bug present in 1.12. The X server chooses to
2297 * associate the first listed RGBA888-Z24S8 config, regardless of its
2298 * sample count, with the 32-bit depth visual used for compositing.
2300 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2301 * supported. Singlebuffer configs are not supported because no one wants
2304 for (unsigned i
= 0; i
< num_formats
; i
++) {
2305 if (devinfo
->gen
< 6)
2308 if (!allow_rgb10_configs
&&
2309 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2310 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2313 if (!allow_rgb565_configs
&& formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
)
2316 __DRIconfig
**new_configs
;
2317 const int num_depth_stencil_bits
= 2;
2318 int num_msaa_modes
= 0;
2319 const uint8_t *multisample_samples
= NULL
;
2322 stencil_bits
[0] = 0;
2324 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2326 stencil_bits
[1] = 0;
2329 stencil_bits
[1] = 8;
2332 if (devinfo
->gen
>= 9) {
2333 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2334 multisample_samples
= multisample_samples_gen9
;
2335 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2336 } else if (devinfo
->gen
== 8) {
2337 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2338 multisample_samples
= multisample_samples_gen8
;
2339 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2340 } else if (devinfo
->gen
== 7) {
2341 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2342 multisample_samples
= multisample_samples_gen7
;
2343 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2344 } else if (devinfo
->gen
== 6) {
2345 static const uint8_t multisample_samples_gen6
[] = {4};
2346 multisample_samples
= multisample_samples_gen6
;
2347 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2350 new_configs
= driCreateConfigs(formats
[i
],
2353 num_depth_stencil_bits
,
2354 back_buffer_modes
, 1,
2355 multisample_samples
,
2357 false, false, false);
2358 configs
= driConcatConfigs(configs
, new_configs
);
2361 if (configs
== NULL
) {
2362 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2371 set_max_gl_versions(struct intel_screen
*screen
)
2373 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2374 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2376 switch (screen
->devinfo
.gen
) {
2381 dri_screen
->max_gl_core_version
= 46;
2382 dri_screen
->max_gl_compat_version
= 30;
2383 dri_screen
->max_gl_es1_version
= 11;
2384 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2387 dri_screen
->max_gl_core_version
= 33;
2388 if (can_do_pipelined_register_writes(screen
)) {
2389 dri_screen
->max_gl_core_version
= 42;
2390 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2391 dri_screen
->max_gl_core_version
= 43;
2392 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2393 dri_screen
->max_gl_core_version
= 45;
2395 dri_screen
->max_gl_compat_version
= 30;
2396 dri_screen
->max_gl_es1_version
= 11;
2397 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2400 dri_screen
->max_gl_core_version
= 33;
2401 dri_screen
->max_gl_compat_version
= 30;
2402 dri_screen
->max_gl_es1_version
= 11;
2403 dri_screen
->max_gl_es2_version
= 30;
2407 dri_screen
->max_gl_core_version
= 0;
2408 dri_screen
->max_gl_compat_version
= 21;
2409 dri_screen
->max_gl_es1_version
= 11;
2410 dri_screen
->max_gl_es2_version
= 20;
2413 unreachable("unrecognized intel_screen::gen");
2418 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2420 struct brw_context
*brw
= (struct brw_context
*)data
;
2423 va_start(args
, fmt
);
2425 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2426 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2427 MESA_DEBUG_TYPE_OTHER
,
2428 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2433 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2435 struct brw_context
*brw
= (struct brw_context
*)data
;
2438 va_start(args
, fmt
);
2440 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2442 va_copy(args_copy
, args
);
2443 vfprintf(stderr
, fmt
, args_copy
);
2447 if (brw
->perf_debug
) {
2449 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2450 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2451 MESA_DEBUG_TYPE_PERFORMANCE
,
2452 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2458 * This is the driver specific part of the createNewScreen entry point.
2459 * Called when using DRI2.
2461 * \return the struct gl_config supported by this driver
2464 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2466 struct intel_screen
*screen
;
2468 if (dri_screen
->image
.loader
) {
2469 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2470 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2472 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2473 "support required\n");
2477 /* Allocate the private area */
2478 screen
= rzalloc(NULL
, struct intel_screen
);
2480 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2483 /* parse information in __driConfigOptions */
2484 driOptionCache options
;
2485 memset(&options
, 0, sizeof(options
));
2487 driParseOptionInfo(&options
, brw_config_options
.xml
);
2488 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
,
2490 driDestroyOptionCache(&options
);
2492 screen
->driScrnPriv
= dri_screen
;
2493 dri_screen
->driverPrivate
= (void *) screen
;
2495 if (!gen_get_device_info_from_fd(dri_screen
->fd
, &screen
->devinfo
))
2498 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2499 screen
->deviceID
= devinfo
->chipset_id
;
2500 screen
->no_hw
= devinfo
->no_hw
;
2502 if (!intel_init_bufmgr(screen
))
2505 brw_process_intel_debug_variable();
2507 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2509 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2510 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2513 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2514 /* Theorectically unlimited! At least for individual objects...
2516 * Currently the entire (global) address space for all GTT maps is
2517 * limited to 64bits. That is all objects on the system that are
2518 * setup for GTT mmapping must fit within 64bits. An attempt to use
2519 * one that exceeds the limit with fail in brw_bo_map_gtt().
2521 * Long before we hit that limit, we will be practically limited by
2522 * that any single object must fit in physical memory (RAM). The upper
2523 * limit on the CPU's address space is currently 48bits (Skylake), of
2524 * which only 39bits can be physical memory. (The GPU itself also has
2525 * a 48bit addressable virtual space.) We can fit over 32 million
2526 * objects of the current maximum allocable size before running out
2529 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2531 /* Estimate the size of the mappable aperture into the GTT. There's an
2532 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2533 * It turns out it's basically always 256MB, though some ancient hardware
2536 uint32_t gtt_size
= 256 * 1024 * 1024;
2538 /* We don't want to map two objects such that a memcpy between them would
2539 * just fault one mapping in and then the other over and over forever. So
2540 * we would need to divide the GTT size by 2. Additionally, some GTT is
2541 * taken up by things like the framebuffer and the ringbuffer and such, so
2542 * be more conservative.
2544 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2547 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2549 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2550 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2552 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2553 screen
->hw_has_swizzling
);
2555 if (devinfo
->gen
>= 10)
2556 intel_cs_timestamp_frequency(screen
);
2558 /* GENs prior to 8 do not support EU/Subslice info */
2559 if (devinfo
->gen
>= 8) {
2560 intel_detect_sseu(screen
);
2561 } else if (devinfo
->gen
== 7) {
2562 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2565 /* Gen7-7.5 kernel requirements / command parser saga:
2568 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2570 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2571 * all batches secure, allowing them to use any feature with no checking.
2572 * This is effectively equivalent to a command parser version of
2573 * \infinity - everything is possible.
2575 * The command parser does not exist, and querying the version will
2579 * The kernel enables the command parser by default, for systems with
2580 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2581 * hardware checker is still enabled, so Haswell and Baytrail cannot
2584 * Ivybridge goes from "everything is possible" to "only what the
2585 * command parser allows" (if the user boots with i915.cmd_parser=0,
2586 * then everything is possible again). We can only safely use features
2587 * allowed by the supported command parser version.
2589 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2590 * implemented by the kernel, even if it's turned off. So, checking
2591 * for version > 0 does not mean that you can write registers. We have
2592 * to try it and see. The version does, however, indicate the age of
2595 * Instead of matching the hardware checker's behavior of converting
2596 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2597 * -EINVAL, making it dangerous to try and use privileged features.
2599 * Effective command parser versions:
2600 * - Haswell: 0 (reporting 1, writes don't work)
2601 * - Baytrail: 0 (reporting 1, writes don't work)
2602 * - Ivybridge: 1 (enabled) or infinite (disabled)
2605 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2606 * effectively version 1 (enabled) or infinite (disabled).
2608 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2609 * Command parser v2 supports predicate writes.
2611 * - Haswell: 0 (reporting 1, writes don't work)
2612 * - Baytrail: 2 (enabled) or infinite (disabled)
2613 * - Ivybridge: 2 (enabled) or infinite (disabled)
2615 * So version >= 2 is enough to know that Ivybridge and Baytrail
2616 * will work. Haswell still can't do anything.
2618 * - v4.0: Version 3 happened. Largely not relevant.
2620 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2621 * L3 config registers are properly saved and restored as part
2622 * of the hardware context. We can approximately detect this point
2623 * in time by checking if I915_PARAM_REVISION is recognized - it
2624 * landed in a later commit, but in the same release cycle.
2626 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2627 * Command parser finally gains secure batch promotion. On Haswell,
2628 * the hardware checker gets disabled, which finally allows it to do
2629 * privileged commands.
2631 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2632 * - Haswell: 3 (enabled) or 0 (disabled)
2633 * - Baytrail: 3 (enabled) or infinite (disabled)
2634 * - Ivybridge: 3 (enabled) or infinite (disabled)
2636 * Unfortunately, detecting this point in time is tricky, because
2637 * no version bump happened when this important change occurred.
2638 * On Haswell, if we can write any register, then the kernel is at
2639 * least this new, and we can start trusting the version number.
2641 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2642 * Command parser reaches version 4, allowing access to Haswell
2643 * atomic scratch and chicken3 registers. If version >= 4, we know
2644 * the kernel is new enough to support privileged features on all
2645 * hardware. However, the user might have disabled it...and the
2646 * kernel will still report version 4. So we still have to guess
2649 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2650 * Command parser v5 whitelists indirect compute shader dispatch
2651 * registers, needed for OpenGL 4.3 and later.
2654 * Command parser v7 lets us use MI_MATH on Haswell.
2656 * Additionally, the kernel begins reporting version 0 when
2657 * the command parser is disabled, allowing us to skip the
2658 * guess-and-check step on Haswell. Unfortunately, this also
2659 * means that we can no longer use it as an indicator of the
2660 * age of the kernel.
2662 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2663 &screen
->cmd_parser_version
) < 0) {
2664 /* Command parser does not exist - getparam is unrecognized */
2665 screen
->cmd_parser_version
= 0;
2668 /* Kernel 4.13 retuired for exec object capture */
2669 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2670 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2673 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2674 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2677 if (!intel_detect_pipelined_so(screen
)) {
2678 /* We can't do anything, so the effective version is 0. */
2679 screen
->cmd_parser_version
= 0;
2681 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2684 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2685 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2687 /* Haswell requires command parser version 4 in order to have L3
2688 * atomic scratch1 and chicken3 bits
2690 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2691 screen
->kernel_features
|=
2692 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2695 /* Haswell requires command parser version 6 in order to write to the
2696 * MI_MATH GPR registers, and version 7 in order to use
2697 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2699 if (devinfo
->gen
>= 8 ||
2700 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2701 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2704 /* Gen7 needs at least command parser version 5 to support compute */
2705 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2706 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2708 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2709 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2711 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2713 screen
->winsys_msaa_samples_override
=
2714 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2715 printf("Forcing winsys sample count to %d\n",
2716 screen
->winsys_msaa_samples_override
);
2718 screen
->winsys_msaa_samples_override
= -1;
2721 set_max_gl_versions(screen
);
2723 /* Notification of GPU resets requires hardware contexts and a kernel new
2724 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2725 * supported, calling it with a context of 0 will either generate EPERM or
2726 * no error. If the ioctl is not supported, it always generate EINVAL.
2727 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2728 * extension to the loader.
2730 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2732 if (devinfo
->gen
>= 6) {
2733 struct drm_i915_reset_stats stats
;
2734 memset(&stats
, 0, sizeof(stats
));
2736 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2738 screen
->has_context_reset_notification
=
2739 (ret
!= -1 || errno
!= EINVAL
);
2742 dri_screen
->extensions
= !screen
->has_context_reset_notification
2743 ? screenExtensions
: intelRobustScreenExtensions
;
2745 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2746 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2747 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2749 /* Changing the meaning of constant buffer pointers from a dynamic state
2750 * offset to an absolute address is only safe if the kernel isolates other
2751 * contexts from our changes.
2753 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8 ||
2754 !(screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
);
2756 screen
->compiler
->supports_pull_constants
= true;
2758 screen
->has_exec_fence
=
2759 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2761 intel_screen_init_surface_formats(screen
);
2763 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2764 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2766 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2767 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2768 fprintf(stderr
, " - User priority sorting enabled\n");
2769 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2770 fprintf(stderr
, " - Preemption enabled\n");
2774 brw_disk_cache_init(screen
);
2776 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2779 struct intel_buffer
{
2784 static __DRIbuffer
*
2785 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2786 unsigned attachment
, unsigned format
,
2787 int width
, int height
)
2789 struct intel_buffer
*intelBuffer
;
2790 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2792 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2793 attachment
== __DRI_BUFFER_BACK_LEFT
);
2795 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2796 if (intelBuffer
== NULL
)
2799 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2800 * supports Y tiled and compressed buffers, but there is no way to plumb that
2801 * through to here. */
2803 int cpp
= format
/ 8;
2804 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2805 "intelAllocateBuffer",
2810 I915_TILING_X
, &pitch
,
2813 if (intelBuffer
->bo
== NULL
) {
2818 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2820 intelBuffer
->base
.attachment
= attachment
;
2821 intelBuffer
->base
.cpp
= cpp
;
2822 intelBuffer
->base
.pitch
= pitch
;
2824 return &intelBuffer
->base
;
2828 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2830 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2832 brw_bo_unreference(intelBuffer
->bo
);
2836 static const struct __DriverAPIRec brw_driver_api
= {
2837 .InitScreen
= intelInitScreen2
,
2838 .DestroyScreen
= intelDestroyScreen
,
2839 .CreateContext
= brwCreateContext
,
2840 .DestroyContext
= intelDestroyContext
,
2841 .CreateBuffer
= intelCreateBuffer
,
2842 .DestroyBuffer
= intelDestroyBuffer
,
2843 .MakeCurrent
= intelMakeCurrent
,
2844 .UnbindContext
= intelUnbindContext
,
2845 .AllocateBuffer
= intelAllocateBuffer
,
2846 .ReleaseBuffer
= intelReleaseBuffer
2849 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2850 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2851 .vtable
= &brw_driver_api
,
2854 static const __DRIextension
*brw_driver_extensions
[] = {
2855 &driCoreExtension
.base
,
2856 &driImageDriverExtension
.base
,
2857 &driDRI2Extension
.base
,
2859 &brw_config_options
.base
,
2863 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2865 globalDriverAPI
= &brw_driver_api
;
2867 return brw_driver_extensions
;