2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "main/glthread.h"
38 #include "swrast/s_renderbuffer.h"
39 #include "util/ralloc.h"
40 #include "util/disk_cache.h"
41 #include "brw_defines.h"
42 #include "brw_state.h"
43 #include "compiler/nir/nir.h"
46 #include "util/disk_cache.h"
47 #include "util/xmlpool.h"
49 #include "common/gen_defines.h"
51 static const __DRIconfigOptionsExtension brw_config_options
= {
52 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
55 DRI_CONF_SECTION_PERFORMANCE
56 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
57 * DRI_CONF_BO_REUSE_ALL
59 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
60 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
61 DRI_CONF_ENUM(0, "Disable buffer object reuse")
62 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
65 DRI_CONF_MESA_NO_ERROR("false")
66 DRI_CONF_MESA_GLTHREAD("false")
69 DRI_CONF_SECTION_QUALITY
70 DRI_CONF_PRECISE_TRIG("false")
72 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
73 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
74 "given integer. If negative, then do not clamp.")
78 DRI_CONF_SECTION_DEBUG
79 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
80 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
81 DRI_CONF_DISABLE_THROTTLING("false")
82 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
83 DRI_CONF_FORCE_GLSL_VERSION(0)
84 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
85 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
86 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
87 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
88 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
89 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
90 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
91 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
93 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
94 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
98 DRI_CONF_SECTION_MISCELLANEOUS
99 DRI_CONF_GLSL_ZERO_INIT("false")
100 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
101 DRI_CONF_ALLOW_RGB565_CONFIGS("true")
106 #include "intel_batchbuffer.h"
107 #include "intel_buffers.h"
108 #include "brw_bufmgr.h"
109 #include "intel_fbo.h"
110 #include "intel_mipmap_tree.h"
111 #include "intel_screen.h"
112 #include "intel_tex.h"
113 #include "intel_image.h"
115 #include "brw_context.h"
117 #include "drm-uapi/i915_drm.h"
120 * For debugging purposes, this returns a time in seconds.
127 clock_gettime(CLOCK_MONOTONIC
, &tp
);
129 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
132 static const __DRItexBufferExtension intelTexBufferExtension
= {
133 .base
= { __DRI_TEX_BUFFER
, 3 },
135 .setTexBuffer
= intelSetTexBuffer
,
136 .setTexBuffer2
= intelSetTexBuffer2
,
137 .releaseTexBuffer
= intelReleaseTexBuffer
,
141 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
142 __DRIdrawable
*dPriv
,
144 enum __DRI2throttleReason reason
)
146 struct brw_context
*brw
= cPriv
->driverPrivate
;
151 struct gl_context
*ctx
= &brw
->ctx
;
153 _mesa_glthread_finish(ctx
);
155 FLUSH_VERTICES(ctx
, 0);
157 if (flags
& __DRI2_FLUSH_DRAWABLE
)
158 intel_resolve_for_dri2_flush(brw
, dPriv
);
160 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
161 brw
->need_swap_throttle
= true;
162 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
163 brw
->need_flush_throttle
= true;
165 intel_batchbuffer_flush(brw
);
169 * Provides compatibility with loaders that only support the older (version
170 * 1-3) flush interface.
172 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
175 intel_dri2_flush(__DRIdrawable
*drawable
)
177 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
178 __DRI2_FLUSH_DRAWABLE
,
179 __DRI2_THROTTLE_SWAPBUFFER
);
182 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
183 .base
= { __DRI2_FLUSH
, 4 },
185 .flush
= intel_dri2_flush
,
186 .invalidate
= dri2InvalidateDrawable
,
187 .flush_with_flags
= intel_dri2_flush_with_flags
,
190 static const struct intel_image_format intel_image_formats
[] = {
191 { __DRI_IMAGE_FOURCC_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
192 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
194 { __DRI_IMAGE_FOURCC_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
195 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
197 { __DRI_IMAGE_FOURCC_ABGR2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
198 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010
, 4 } } },
200 { __DRI_IMAGE_FOURCC_XBGR2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
201 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010
, 4 } } },
203 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
204 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
206 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
207 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
209 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
210 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
212 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
215 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
218 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
221 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
224 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
227 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
230 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
233 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
236 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
241 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
246 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
251 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
256 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
261 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
266 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
267 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
271 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
272 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
273 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
276 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
279 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
281 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
282 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
283 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
284 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
286 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
287 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
288 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
290 { __DRI_IMAGE_FOURCC_P010
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
291 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
292 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
294 { __DRI_IMAGE_FOURCC_P012
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
295 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
296 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
298 { __DRI_IMAGE_FOURCC_P016
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
299 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 2 },
300 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616
, 4 } } },
302 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
303 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
304 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
306 { __DRI_IMAGE_FOURCC_AYUV
, __DRI_IMAGE_COMPONENTS_AYUV
, 1,
307 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
309 { __DRI_IMAGE_FOURCC_XYUV8888
, __DRI_IMAGE_COMPONENTS_XYUV
, 1,
310 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 } } },
312 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
313 * and treat them as planar buffers in the compositors.
314 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
315 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
316 * clusters and places pairs and places U into the G component and
317 * V into A. This lets the texture sampler interpolate the Y
318 * components correctly when sampling from plane 0, and interpolate
319 * U and V correctly when sampling from plane 1. */
320 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
321 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
322 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
323 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
324 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
325 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
328 static const struct {
331 } supported_modifiers
[] = {
332 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
333 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
334 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
335 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
339 modifier_is_supported(const struct gen_device_info
*devinfo
,
340 const struct intel_image_format
*fmt
, int dri_format
,
343 const struct isl_drm_modifier_info
*modinfo
=
344 isl_drm_modifier_get_info(modifier
);
347 /* ISL had better know about the modifier */
351 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
352 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
353 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
356 /* CCS_E is not supported for planar images */
357 if (fmt
&& fmt
->nplanes
> 1)
361 assert(dri_format
== 0);
362 dri_format
= fmt
->planes
[0].dri_format
;
365 mesa_format format
= driImageFormatToGLFormat(dri_format
);
366 /* Whether or not we support compression is based on the RGBA non-sRGB
367 * version of the format.
369 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
370 format
= _mesa_get_srgb_format_linear(format
);
371 if (!isl_format_supports_ccs_e(devinfo
,
372 brw_isl_format_for_mesa_format(format
)))
376 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
377 if (supported_modifiers
[i
].modifier
!= modifier
)
380 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
387 tiling_to_modifier(uint32_t tiling
)
389 static const uint64_t map
[] = {
390 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
391 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
392 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
395 assert(tiling
< ARRAY_SIZE(map
));
401 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
403 uint32_t tiling
, swizzle
;
404 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
406 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
407 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
408 func
, image
->offset
);
412 static const struct intel_image_format
*
413 intel_image_format_lookup(int fourcc
)
415 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
416 if (intel_image_formats
[i
].fourcc
== fourcc
)
417 return &intel_image_formats
[i
];
424 intel_image_get_fourcc(__DRIimage
*image
, int *fourcc
)
426 if (image
->planar_format
) {
427 *fourcc
= image
->planar_format
->fourcc
;
431 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
432 if (intel_image_formats
[i
].planes
[0].dri_format
== image
->dri_format
) {
433 *fourcc
= intel_image_formats
[i
].fourcc
;
441 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
446 image
= calloc(1, sizeof *image
);
450 image
->screen
= screen
;
451 image
->dri_format
= dri_format
;
454 image
->format
= driImageFormatToGLFormat(dri_format
);
455 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
456 image
->format
== MESA_FORMAT_NONE
) {
461 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
462 image
->data
= loaderPrivate
;
468 * Sets up a DRIImage structure to point to a slice out of a miptree.
471 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
472 struct intel_mipmap_tree
*mt
, GLuint level
,
475 intel_miptree_make_shareable(brw
, mt
);
477 intel_miptree_check_level_layer(mt
, level
, zoffset
);
479 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
480 level
- mt
->first_level
);
481 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
482 level
- mt
->first_level
);
483 image
->pitch
= mt
->surf
.row_pitch_B
;
485 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
489 brw_bo_unreference(image
->bo
);
491 brw_bo_reference(mt
->bo
);
495 intel_create_image_from_name(__DRIscreen
*dri_screen
,
496 int width
, int height
, int format
,
497 int name
, int pitch
, void *loaderPrivate
)
499 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
503 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
507 if (image
->format
== MESA_FORMAT_NONE
)
510 cpp
= _mesa_get_format_bytes(image
->format
);
512 image
->width
= width
;
513 image
->height
= height
;
514 image
->pitch
= pitch
* cpp
;
515 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
521 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
527 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
528 int renderbuffer
, void *loaderPrivate
)
531 struct brw_context
*brw
= context
->driverPrivate
;
532 struct gl_context
*ctx
= &brw
->ctx
;
533 struct gl_renderbuffer
*rb
;
534 struct intel_renderbuffer
*irb
;
536 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
538 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
542 irb
= intel_renderbuffer(rb
);
543 intel_miptree_make_shareable(brw
, irb
->mt
);
544 image
= calloc(1, sizeof *image
);
548 image
->internal_format
= rb
->InternalFormat
;
549 image
->format
= rb
->Format
;
550 image
->modifier
= tiling_to_modifier(
551 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
553 image
->data
= loaderPrivate
;
554 brw_bo_unreference(image
->bo
);
555 image
->bo
= irb
->mt
->bo
;
556 brw_bo_reference(irb
->mt
->bo
);
557 image
->width
= rb
->Width
;
558 image
->height
= rb
->Height
;
559 image
->pitch
= irb
->mt
->surf
.row_pitch_B
;
560 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
561 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
563 rb
->NeedsFinishRenderTexture
= true;
568 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
569 unsigned texture
, int zoffset
,
575 struct brw_context
*brw
= context
->driverPrivate
;
576 struct gl_texture_object
*obj
;
577 struct intel_texture_object
*iobj
;
580 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
581 if (!obj
|| obj
->Target
!= target
) {
582 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
586 if (target
== GL_TEXTURE_CUBE_MAP
)
589 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
590 iobj
= intel_texture_object(obj
);
591 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
592 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
596 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
597 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
601 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
602 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
605 image
= calloc(1, sizeof *image
);
607 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
611 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
612 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
613 image
->modifier
= tiling_to_modifier(
614 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
615 image
->data
= loaderPrivate
;
616 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
617 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
618 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
619 image
->planar_format
= iobj
->planar_format
;
620 if (image
->dri_format
== __DRI_IMAGE_FORMAT_NONE
) {
621 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
626 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
631 intel_destroy_image(__DRIimage
*image
)
633 brw_bo_unreference(image
->bo
);
637 enum modifier_priority
{
638 MODIFIER_PRIORITY_INVALID
= 0,
639 MODIFIER_PRIORITY_LINEAR
,
642 MODIFIER_PRIORITY_Y_CCS
,
645 const uint64_t priority_to_modifier
[] = {
646 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
647 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
648 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
649 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
650 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
654 select_best_modifier(struct gen_device_info
*devinfo
,
656 const uint64_t *modifiers
,
657 const unsigned count
)
659 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
661 for (int i
= 0; i
< count
; i
++) {
662 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
665 switch (modifiers
[i
]) {
666 case I915_FORMAT_MOD_Y_TILED_CCS
:
667 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
669 case I915_FORMAT_MOD_Y_TILED
:
670 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
672 case I915_FORMAT_MOD_X_TILED
:
673 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
675 case DRM_FORMAT_MOD_LINEAR
:
676 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
678 case DRM_FORMAT_MOD_INVALID
:
684 return priority_to_modifier
[prio
];
688 intel_create_image_common(__DRIscreen
*dri_screen
,
689 int width
, int height
, int format
,
691 const uint64_t *modifiers
,
696 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
697 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
700 /* Callers of this may specify a modifier, or a dri usage, but not both. The
701 * newer modifier interface deprecates the older usage flags newer modifier
702 * interface deprecates the older usage flags.
704 assert(!(use
&& count
));
706 if (use
& __DRI_IMAGE_USE_CURSOR
) {
707 if (width
!= 64 || height
!= 64)
709 modifier
= DRM_FORMAT_MOD_LINEAR
;
712 if (use
& __DRI_IMAGE_USE_LINEAR
)
713 modifier
= DRM_FORMAT_MOD_LINEAR
;
715 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
717 /* User requested specific modifiers */
718 modifier
= select_best_modifier(&screen
->devinfo
, format
,
720 if (modifier
== DRM_FORMAT_MOD_INVALID
)
723 /* Historically, X-tiled was the default, and so lack of modifier means
726 modifier
= I915_FORMAT_MOD_X_TILED
;
730 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
734 const struct isl_drm_modifier_info
*mod_info
=
735 isl_drm_modifier_get_info(modifier
);
737 struct isl_surf surf
;
738 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
739 .dim
= ISL_SURF_DIM_2D
,
740 .format
= brw_isl_format_for_mesa_format(image
->format
),
747 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
748 ISL_SURF_USAGE_TEXTURE_BIT
|
749 ISL_SURF_USAGE_STORAGE_BIT
,
750 .tiling_flags
= (1 << mod_info
->tiling
));
757 struct isl_surf aux_surf
;
758 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
759 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, 0);
765 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
769 /* We request that the bufmgr zero the buffer for us for two reasons:
771 * 1) If a buffer gets re-used from the pool, we don't want to leak random
772 * garbage from our process to some other.
774 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
775 * a valid state. A CCS value of 0 indicates that the given block is
776 * in the pass-through state which is what we want.
778 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
779 surf
.size_B
+ aux_surf
.size_B
,
781 isl_tiling_to_i915_tiling(mod_info
->tiling
),
782 surf
.row_pitch_B
, BO_ALLOC_ZEROED
);
783 if (image
->bo
== NULL
) {
787 image
->width
= width
;
788 image
->height
= height
;
789 image
->pitch
= surf
.row_pitch_B
;
790 image
->modifier
= modifier
;
792 if (aux_surf
.size_B
) {
793 image
->aux_offset
= surf
.size_B
;
794 image
->aux_pitch
= aux_surf
.row_pitch_B
;
795 image
->aux_size
= aux_surf
.size_B
;
802 intel_create_image(__DRIscreen
*dri_screen
,
803 int width
, int height
, int format
,
807 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
812 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
813 int x0
, int y0
, int width
, int height
,
814 unsigned int flags
, int *stride
, void **map_info
)
816 struct brw_context
*brw
= NULL
;
817 struct brw_bo
*bo
= NULL
;
818 void *raw_data
= NULL
;
823 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
826 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
829 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
832 if (flags
& MAP_INTERNAL_MASK
)
835 brw
= context
->driverPrivate
;
841 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
842 raw_data
= brw_bo_map(brw
, bo
, flags
);
846 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
847 pix_bytes
= _mesa_get_format_bytes(image
->format
);
851 assert(pix_bytes
> 0);
853 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
855 brw_bo_reference(bo
);
857 *stride
= image
->pitch
;
864 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
866 struct brw_bo
*bo
= map_info
;
869 brw_bo_unreference(bo
);
873 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
874 int width
, int height
, int format
,
875 const uint64_t *modifiers
,
876 const unsigned count
,
879 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
880 modifiers
, count
, loaderPrivate
);
884 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
887 case __DRI_IMAGE_ATTRIB_STRIDE
:
888 *value
= image
->pitch
;
890 case __DRI_IMAGE_ATTRIB_HANDLE
:
891 *value
= brw_bo_export_gem_handle(image
->bo
);
893 case __DRI_IMAGE_ATTRIB_NAME
:
894 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
895 case __DRI_IMAGE_ATTRIB_FORMAT
:
896 *value
= image
->dri_format
;
898 case __DRI_IMAGE_ATTRIB_WIDTH
:
899 *value
= image
->width
;
901 case __DRI_IMAGE_ATTRIB_HEIGHT
:
902 *value
= image
->height
;
904 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
905 if (image
->planar_format
== NULL
)
907 *value
= image
->planar_format
->components
;
909 case __DRI_IMAGE_ATTRIB_FD
:
910 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
911 case __DRI_IMAGE_ATTRIB_FOURCC
:
912 return intel_image_get_fourcc(image
, value
);
913 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
914 if (isl_drm_modifier_has_aux(image
->modifier
)) {
915 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
917 } else if (image
->planar_format
) {
918 *value
= image
->planar_format
->nplanes
;
923 case __DRI_IMAGE_ATTRIB_OFFSET
:
924 *value
= image
->offset
;
926 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
927 *value
= (image
->modifier
& 0xffffffff);
929 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
930 *value
= ((image
->modifier
>> 32) & 0xffffffff);
939 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
940 uint32_t fourcc
, uint64_t modifier
,
941 int attrib
, uint64_t *value
)
943 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
944 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
946 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
950 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
951 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
960 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
964 image
= calloc(1, sizeof *image
);
968 brw_bo_reference(orig_image
->bo
);
969 image
->bo
= orig_image
->bo
;
970 image
->internal_format
= orig_image
->internal_format
;
971 image
->planar_format
= orig_image
->planar_format
;
972 image
->dri_format
= orig_image
->dri_format
;
973 image
->format
= orig_image
->format
;
974 image
->modifier
= orig_image
->modifier
;
975 image
->offset
= orig_image
->offset
;
976 image
->width
= orig_image
->width
;
977 image
->height
= orig_image
->height
;
978 image
->pitch
= orig_image
->pitch
;
979 image
->tile_x
= orig_image
->tile_x
;
980 image
->tile_y
= orig_image
->tile_y
;
981 image
->has_depthstencil
= orig_image
->has_depthstencil
;
982 image
->data
= loaderPrivate
;
983 image
->aux_offset
= orig_image
->aux_offset
;
984 image
->aux_pitch
= orig_image
->aux_pitch
;
986 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
987 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
993 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
995 if (use
& __DRI_IMAGE_USE_CURSOR
) {
996 if (image
->width
!= 64 || image
->height
!= 64)
1004 intel_create_image_from_names(__DRIscreen
*dri_screen
,
1005 int width
, int height
, int fourcc
,
1006 int *names
, int num_names
,
1007 int *strides
, int *offsets
,
1008 void *loaderPrivate
)
1010 const struct intel_image_format
*f
= NULL
;
1014 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
1017 f
= intel_image_format_lookup(fourcc
);
1021 image
= intel_create_image_from_name(dri_screen
, width
, height
,
1022 __DRI_IMAGE_FORMAT_NONE
,
1023 names
[0], strides
[0],
1029 image
->planar_format
= f
;
1030 for (i
= 0; i
< f
->nplanes
; i
++) {
1031 index
= f
->planes
[i
].buffer_index
;
1032 image
->offsets
[index
] = offsets
[index
];
1033 image
->strides
[index
] = strides
[index
];
1040 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1041 int width
, int height
, int fourcc
,
1042 uint64_t modifier
, int *fds
, int num_fds
,
1043 int *strides
, int *offsets
,
1044 void *loaderPrivate
)
1046 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1047 const struct intel_image_format
*f
;
1052 if (fds
== NULL
|| num_fds
< 1)
1055 f
= intel_image_format_lookup(fourcc
);
1059 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1060 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1063 if (f
->nplanes
== 1)
1064 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1067 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1073 image
->width
= width
;
1074 image
->height
= height
;
1075 image
->pitch
= strides
[0];
1077 image
->planar_format
= f
;
1079 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1080 const struct isl_drm_modifier_info
*mod_info
=
1081 isl_drm_modifier_get_info(modifier
);
1082 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1083 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1084 tiling
, strides
[0]);
1086 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1089 if (image
->bo
== NULL
) {
1094 /* We only support all planes from the same bo.
1095 * brw_bo_gem_create_from_prime() should return the same pointer for all
1096 * fds received here */
1097 for (i
= 1; i
< num_fds
; i
++) {
1098 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1099 brw_bo_unreference(aux
);
1100 if (aux
!= image
->bo
) {
1101 brw_bo_unreference(image
->bo
);
1107 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1108 image
->modifier
= modifier
;
1110 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1112 const struct isl_drm_modifier_info
*mod_info
=
1113 isl_drm_modifier_get_info(image
->modifier
);
1116 struct isl_surf surf
;
1117 for (i
= 0; i
< f
->nplanes
; i
++) {
1118 index
= f
->planes
[i
].buffer_index
;
1119 image
->offsets
[index
] = offsets
[index
];
1120 image
->strides
[index
] = strides
[index
];
1122 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1123 /* The images we will create are actually based on the RGBA non-sRGB
1124 * version of the format.
1126 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1127 format
= _mesa_get_srgb_format_linear(format
);
1129 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1130 .dim
= ISL_SURF_DIM_2D
,
1131 .format
= brw_isl_format_for_mesa_format(format
),
1132 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1133 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1138 .row_pitch_B
= strides
[index
],
1139 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1140 ISL_SURF_USAGE_TEXTURE_BIT
|
1141 ISL_SURF_USAGE_STORAGE_BIT
,
1142 .tiling_flags
= (1 << mod_info
->tiling
));
1144 brw_bo_unreference(image
->bo
);
1149 const int end
= offsets
[index
] + surf
.size_B
;
1154 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1155 /* Even though we initialize surf in the loop above, we know that
1156 * anything with CCS_E will have exactly one plane so surf is properly
1157 * initialized when we get here.
1159 assert(f
->nplanes
== 1);
1161 image
->aux_offset
= offsets
[1];
1162 image
->aux_pitch
= strides
[1];
1164 /* Scanout hardware requires that the CCS be placed after the main
1165 * surface in memory. We consider any CCS that is placed any earlier in
1166 * memory to be invalid and reject it.
1168 * At some point in the future, this restriction may be relaxed if the
1169 * hardware becomes less strict but we may need a new modifier for that.
1172 if (image
->aux_offset
< size
) {
1173 brw_bo_unreference(image
->bo
);
1178 struct isl_surf aux_surf
;
1179 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
,
1182 brw_bo_unreference(image
->bo
);
1187 image
->aux_size
= aux_surf
.size_B
;
1189 const int end
= image
->aux_offset
+ aux_surf
.size_B
;
1193 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1196 /* Check that the requested image actually fits within the BO. 'size'
1197 * is already relative to the offsets, so we don't need to add that. */
1198 if (image
->bo
->size
== 0) {
1199 image
->bo
->size
= size
;
1200 } else if (size
> image
->bo
->size
) {
1201 brw_bo_unreference(image
->bo
);
1206 if (f
->nplanes
== 1) {
1207 image
->offset
= image
->offsets
[0];
1208 intel_image_warn_if_unaligned(image
, __func__
);
1215 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1216 int width
, int height
, int fourcc
,
1217 int *fds
, int num_fds
, int *strides
, int *offsets
,
1218 void *loaderPrivate
)
1220 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1221 DRM_FORMAT_MOD_INVALID
,
1222 fds
, num_fds
, strides
, offsets
,
1227 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1228 int width
, int height
,
1229 int fourcc
, uint64_t modifier
,
1230 int *fds
, int num_fds
,
1231 int *strides
, int *offsets
,
1232 enum __DRIYUVColorSpace yuv_color_space
,
1233 enum __DRISampleRange sample_range
,
1234 enum __DRIChromaSiting horizontal_siting
,
1235 enum __DRIChromaSiting vertical_siting
,
1237 void *loaderPrivate
)
1240 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1243 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1247 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1249 fds
, num_fds
, strides
, offsets
,
1253 * Invalid parameters and any inconsistencies between are assumed to be
1254 * checked by the caller. Therefore besides unsupported formats one can fail
1255 * only in allocation.
1258 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1262 image
->yuv_color_space
= yuv_color_space
;
1263 image
->sample_range
= sample_range
;
1264 image
->horizontal_siting
= horizontal_siting
;
1265 image
->vertical_siting
= vertical_siting
;
1267 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1272 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1273 int width
, int height
, int fourcc
,
1274 int *fds
, int num_fds
,
1275 int *strides
, int *offsets
,
1276 enum __DRIYUVColorSpace yuv_color_space
,
1277 enum __DRISampleRange sample_range
,
1278 enum __DRIChromaSiting horizontal_siting
,
1279 enum __DRIChromaSiting vertical_siting
,
1281 void *loaderPrivate
)
1283 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1284 fourcc
, DRM_FORMAT_MOD_INVALID
,
1285 fds
, num_fds
, strides
, offsets
,
1295 intel_image_format_is_supported(const struct gen_device_info
*devinfo
,
1296 const struct intel_image_format
*fmt
)
1298 /* Currently, all formats with an intel_image_format are available on all
1299 * platforms so there's really nothing to check there.
1303 if (fmt
->nplanes
== 1) {
1304 mesa_format format
= driImageFormatToGLFormat(fmt
->planes
[0].dri_format
);
1305 /* The images we will create are actually based on the RGBA non-sRGB
1306 * version of the format.
1308 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1309 format
= _mesa_get_srgb_format_linear(format
);
1310 enum isl_format isl_format
= brw_isl_format_for_mesa_format(format
);
1311 assert(isl_format_supports_rendering(devinfo
, isl_format
));
1319 intel_query_dma_buf_formats(__DRIscreen
*_screen
, int max
,
1320 int *formats
, int *count
)
1322 struct intel_screen
*screen
= _screen
->driverPrivate
;
1323 int num_formats
= 0, i
;
1325 for (i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
1326 /* These two formats are valid DRI formats but do not exist in
1327 * drm_fourcc.h in the Linux kernel. We don't want to accidentally
1328 * advertise them through the EGL layer.
1330 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
||
1331 intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SABGR8888
)
1334 if (!intel_image_format_is_supported(&screen
->devinfo
,
1335 &intel_image_formats
[i
]))
1342 formats
[num_formats
- 1] = intel_image_formats
[i
].fourcc
;
1343 if (num_formats
>= max
)
1347 *count
= num_formats
;
1352 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1353 uint64_t *modifiers
,
1354 unsigned int *external_only
,
1357 struct intel_screen
*screen
= _screen
->driverPrivate
;
1358 const struct intel_image_format
*f
;
1359 int num_mods
= 0, i
;
1361 f
= intel_image_format_lookup(fourcc
);
1365 if (!intel_image_format_is_supported(&screen
->devinfo
, f
))
1368 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1369 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1370 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1377 modifiers
[num_mods
- 1] = modifier
;
1378 if (num_mods
>= max
)
1382 if (external_only
!= NULL
) {
1383 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1384 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1385 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1386 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1387 external_only
[i
] = GL_TRUE
;
1390 external_only
[i
] = GL_FALSE
;
1400 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1402 int width
, height
, offset
, stride
, size
, dri_format
;
1408 width
= parent
->width
;
1409 height
= parent
->height
;
1411 const struct intel_image_format
*f
= parent
->planar_format
;
1413 if (f
&& plane
< f
->nplanes
) {
1414 /* Use the planar format definition. */
1415 width
>>= f
->planes
[plane
].width_shift
;
1416 height
>>= f
->planes
[plane
].height_shift
;
1417 dri_format
= f
->planes
[plane
].dri_format
;
1418 int index
= f
->planes
[plane
].buffer_index
;
1419 offset
= parent
->offsets
[index
];
1420 stride
= parent
->strides
[index
];
1421 size
= height
* stride
;
1422 } else if (plane
== 0) {
1423 /* The only plane of a non-planar image: copy the parent definition
1425 dri_format
= parent
->dri_format
;
1426 offset
= parent
->offset
;
1427 stride
= parent
->pitch
;
1428 size
= height
* stride
;
1429 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1430 isl_drm_modifier_has_aux(parent
->modifier
)) {
1431 /* Auxiliary plane */
1432 dri_format
= parent
->dri_format
;
1433 offset
= parent
->aux_offset
;
1434 stride
= parent
->aux_pitch
;
1435 size
= parent
->aux_size
;
1440 if (offset
+ size
> parent
->bo
->size
) {
1441 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1445 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1449 image
->bo
= parent
->bo
;
1450 brw_bo_reference(parent
->bo
);
1451 image
->modifier
= parent
->modifier
;
1453 image
->width
= width
;
1454 image
->height
= height
;
1455 image
->pitch
= stride
;
1456 image
->offset
= offset
;
1458 intel_image_warn_if_unaligned(image
, __func__
);
1463 static const __DRIimageExtension intelImageExtension
= {
1464 .base
= { __DRI_IMAGE
, 16 },
1466 .createImageFromName
= intel_create_image_from_name
,
1467 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1468 .destroyImage
= intel_destroy_image
,
1469 .createImage
= intel_create_image
,
1470 .queryImage
= intel_query_image
,
1471 .dupImage
= intel_dup_image
,
1472 .validateUsage
= intel_validate_usage
,
1473 .createImageFromNames
= intel_create_image_from_names
,
1474 .fromPlanar
= intel_from_planar
,
1475 .createImageFromTexture
= intel_create_image_from_texture
,
1476 .createImageFromFds
= intel_create_image_from_fds
,
1477 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1479 .getCapabilities
= NULL
,
1480 .mapImage
= intel_map_image
,
1481 .unmapImage
= intel_unmap_image
,
1482 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1483 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1484 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1485 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1486 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1490 get_aperture_size(int fd
)
1492 struct drm_i915_gem_get_aperture aperture
;
1494 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1497 return aperture
.aper_size
;
1501 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1502 int param
, unsigned int *value
)
1504 const struct intel_screen
*const screen
=
1505 (struct intel_screen
*) dri_screen
->driverPrivate
;
1508 case __DRI2_RENDERER_VENDOR_ID
:
1511 case __DRI2_RENDERER_DEVICE_ID
:
1512 value
[0] = screen
->deviceID
;
1514 case __DRI2_RENDERER_ACCELERATED
:
1517 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1518 /* Once a batch uses more than 75% of the maximum mappable size, we
1519 * assume that there's some fragmentation, and we start doing extra
1520 * flushing, etc. That's the big cliff apps will care about.
1522 const unsigned gpu_mappable_megabytes
=
1523 screen
->aperture_threshold
/ (1024 * 1024);
1525 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1526 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1528 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1531 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1532 * (uint64_t) system_page_size
;
1534 const unsigned system_memory_megabytes
=
1535 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1537 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1540 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1543 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1546 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1548 if (brw_hw_context_set_priority(screen
->bufmgr
,
1549 0, GEN_CONTEXT_HIGH_PRIORITY
) == 0)
1550 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1551 if (brw_hw_context_set_priority(screen
->bufmgr
,
1552 0, GEN_CONTEXT_LOW_PRIORITY
) == 0)
1553 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1554 /* reset to default last, just in case */
1555 if (brw_hw_context_set_priority(screen
->bufmgr
,
1556 0, GEN_CONTEXT_MEDIUM_PRIORITY
) == 0)
1557 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1559 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1563 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1570 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1571 int param
, const char **value
)
1573 const struct intel_screen
*screen
=
1574 (struct intel_screen
*) dri_screen
->driverPrivate
;
1577 case __DRI2_RENDERER_VENDOR_ID
:
1578 value
[0] = brw_vendor_string
;
1580 case __DRI2_RENDERER_DEVICE_ID
:
1581 value
[0] = brw_get_renderer_string(screen
);
1591 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1592 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1594 const struct intel_screen
*const screen
=
1595 (struct intel_screen
*) dri_screen
->driverPrivate
;
1597 if (!screen
->disk_cache
)
1600 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1603 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1604 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1606 .queryInteger
= brw_query_renderer_integer
,
1607 .queryString
= brw_query_renderer_string
1610 static const __DRIrobustnessExtension dri2Robustness
= {
1611 .base
= { __DRI2_ROBUSTNESS
, 1 }
1614 static const __DRI2blobExtension intelBlobExtension
= {
1615 .base
= { __DRI2_BLOB
, 1 },
1616 .set_cache_funcs
= brw_set_cache_funcs
1619 static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension
= {
1620 .base
= { __DRI_MUTABLE_RENDER_BUFFER_DRIVER
, 1 },
1623 static const __DRIextension
*screenExtensions
[] = {
1624 &intelTexBufferExtension
.base
,
1625 &intelFenceExtension
.base
,
1626 &intelFlushExtension
.base
,
1627 &intelImageExtension
.base
,
1628 &intelRendererQueryExtension
.base
,
1629 &intelMutableRenderBufferExtension
.base
,
1630 &dri2ConfigQueryExtension
.base
,
1631 &dri2NoErrorExtension
.base
,
1632 &intelBlobExtension
.base
,
1636 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1637 &intelTexBufferExtension
.base
,
1638 &intelFenceExtension
.base
,
1639 &intelFlushExtension
.base
,
1640 &intelImageExtension
.base
,
1641 &intelRendererQueryExtension
.base
,
1642 &intelMutableRenderBufferExtension
.base
,
1643 &dri2ConfigQueryExtension
.base
,
1644 &dri2Robustness
.base
,
1645 &dri2NoErrorExtension
.base
,
1646 &intelBlobExtension
.base
,
1651 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1654 struct drm_i915_getparam gp
;
1656 memset(&gp
, 0, sizeof(gp
));
1660 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1663 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1670 intel_get_boolean(struct intel_screen
*screen
, int param
)
1673 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1677 intel_get_integer(struct intel_screen
*screen
, int param
)
1681 if (intel_get_param(screen
, param
, &value
) == 0)
1688 intelDestroyScreen(__DRIscreen
* sPriv
)
1690 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1692 brw_bufmgr_destroy(screen
->bufmgr
);
1693 driDestroyOptionInfo(&screen
->optionCache
);
1695 disk_cache_destroy(screen
->disk_cache
);
1697 ralloc_free(screen
);
1698 sPriv
->driverPrivate
= NULL
;
1703 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1705 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1706 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1707 * this does not allocate GPU memory.
1710 intelCreateBuffer(__DRIscreen
*dri_screen
,
1711 __DRIdrawable
* driDrawPriv
,
1712 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1714 struct intel_renderbuffer
*rb
;
1715 struct intel_screen
*screen
= (struct intel_screen
*)
1716 dri_screen
->driverPrivate
;
1717 mesa_format rgbFormat
;
1718 unsigned num_samples
=
1719 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1724 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1728 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1730 if (screen
->winsys_msaa_samples_override
!= -1) {
1731 num_samples
= screen
->winsys_msaa_samples_override
;
1732 fb
->Visual
.samples
= num_samples
;
1735 if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1736 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1737 : MESA_FORMAT_R10G10B10A2_UNORM
;
1738 } else if (mesaVis
->redBits
== 10) {
1739 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1740 : MESA_FORMAT_R10G10B10X2_UNORM
;
1741 } else if (mesaVis
->redBits
== 5) {
1742 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1743 : MESA_FORMAT_B5G6R5_UNORM
;
1744 } else if (mesaVis
->sRGBCapable
) {
1745 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1746 : MESA_FORMAT_B8G8R8A8_SRGB
;
1747 } else if (mesaVis
->alphaBits
== 0) {
1748 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1749 : MESA_FORMAT_B8G8R8X8_UNORM
;
1751 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1752 : MESA_FORMAT_B8G8R8A8_SRGB
;
1753 fb
->Visual
.sRGBCapable
= true;
1756 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1757 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1759 /* setup the hardware-based renderbuffers */
1760 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1761 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1762 rb
->need_srgb
= srgb_cap_set
;
1764 if (mesaVis
->doubleBufferMode
) {
1765 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1766 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1767 rb
->need_srgb
= srgb_cap_set
;
1771 * Assert here that the gl_config has an expected depth/stencil bit
1772 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1773 * which constructs the advertised configs.)
1775 if (mesaVis
->depthBits
== 24) {
1776 assert(mesaVis
->stencilBits
== 8);
1778 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1779 rb
= intel_create_private_renderbuffer(screen
,
1780 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1782 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1783 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1785 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1788 * Use combined depth/stencil. Note that the renderbuffer is
1789 * attached to two attachment points.
1791 rb
= intel_create_private_renderbuffer(screen
,
1792 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1794 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1795 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1798 else if (mesaVis
->depthBits
== 16) {
1799 assert(mesaVis
->stencilBits
== 0);
1800 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1802 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1805 assert(mesaVis
->depthBits
== 0);
1806 assert(mesaVis
->stencilBits
== 0);
1809 /* now add any/all software-based renderbuffers we may need */
1810 _swrast_add_soft_renderbuffers(fb
,
1811 false, /* never sw color */
1812 false, /* never sw depth */
1813 false, /* never sw stencil */
1814 mesaVis
->accumRedBits
> 0,
1815 false, /* never sw alpha */
1816 false /* never sw aux */ );
1817 driDrawPriv
->driverPrivate
= fb
;
1823 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1825 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1827 _mesa_reference_framebuffer(&fb
, NULL
);
1831 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1833 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1834 * gen10, PCI-id is enough to figure it out.
1836 assert(screen
->devinfo
.gen
>= 10);
1840 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1844 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1848 screen
->devinfo
.timestamp_frequency
= freq
;
1852 intel_detect_sseu(struct intel_screen
*screen
)
1854 assert(screen
->devinfo
.gen
>= 8);
1857 screen
->subslice_total
= -1;
1858 screen
->eu_total
= -1;
1860 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1861 &screen
->subslice_total
);
1862 if (ret
< 0 && ret
!= -EINVAL
)
1865 ret
= intel_get_param(screen
,
1866 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1867 if (ret
< 0 && ret
!= -EINVAL
)
1870 /* Without this information, we cannot get the right Braswell brandstrings,
1871 * and we have to use conservative numbers for GPGPU on many platforms, but
1872 * otherwise, things will just work.
1874 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1876 "Kernel 4.1 required to properly query GPU properties.\n");
1881 screen
->subslice_total
= -1;
1882 screen
->eu_total
= -1;
1883 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1887 intel_init_bufmgr(struct intel_screen
*screen
)
1889 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1891 if (getenv("INTEL_NO_HW") != NULL
)
1892 screen
->no_hw
= true;
1894 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
);
1895 if (screen
->bufmgr
== NULL
) {
1896 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1897 __func__
, __LINE__
);
1901 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1902 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1910 intel_detect_swizzling(struct intel_screen
*screen
)
1912 /* Broadwell PRM says:
1914 * "Before Gen8, there was a historical configuration control field to
1915 * swizzle address bit[6] for in X/Y tiling modes. This was set in three
1916 * different places: TILECTL[1:0], ARB_MODE[5:4], and
1917 * DISP_ARB_CTL[14:13].
1919 * For Gen8 and subsequent generations, the swizzle fields are all
1920 * reserved, and the CPU's memory controller performs all address
1921 * swizzling modifications."
1923 if (screen
->devinfo
.gen
>= 8)
1926 uint32_t tiling
= I915_TILING_X
;
1927 uint32_t swizzle_mode
= 0;
1928 struct brw_bo
*buffer
=
1929 brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test", 32768,
1930 BRW_MEMZONE_OTHER
, tiling
, 512, 0);
1934 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1935 brw_bo_unreference(buffer
);
1937 return swizzle_mode
!= I915_BIT_6_SWIZZLE_NONE
;
1941 intel_detect_timestamp(struct intel_screen
*screen
)
1943 uint64_t dummy
= 0, last
= 0;
1944 int upper
, lower
, loops
;
1946 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1947 * TIMESTAMP register being shifted and the low 32bits always zero.
1949 * More recent kernels offer an interface to read the full 36bits
1952 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1955 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1956 * upper 32bits for a rapidly changing timestamp.
1958 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1962 for (loops
= 0; loops
< 10; loops
++) {
1963 /* The TIMESTAMP should change every 80ns, so several round trips
1964 * through the kernel should be enough to advance it.
1966 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1969 upper
+= (dummy
>> 32) != (last
>> 32);
1970 if (upper
> 1) /* beware 32bit counter overflow */
1971 return 2; /* upper dword holds the low 32bits of the timestamp */
1973 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1975 return 1; /* timestamp is unshifted */
1980 /* No advancement? No timestamp! */
1985 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1987 * Some combinations of hardware and kernel versions allow this feature,
1988 * while others don't. Instead of trying to enumerate every case, just
1989 * try and write a register and see if works.
1992 intel_detect_pipelined_register(struct intel_screen
*screen
,
1993 int reg
, uint32_t expected_value
, bool reset
)
1998 struct brw_bo
*results
, *bo
;
2000 uint32_t offset
= 0;
2002 bool success
= false;
2004 /* Create a zero'ed temporary buffer for reading our results */
2005 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, BRW_MEMZONE_OTHER
);
2006 if (results
== NULL
)
2009 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, BRW_MEMZONE_OTHER
);
2013 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
2019 /* Write the register. */
2020 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2022 *batch
++ = expected_value
;
2024 /* Save the register's value back to the buffer. */
2025 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
2027 struct drm_i915_gem_relocation_entry reloc
= {
2028 .offset
= (char *) batch
- (char *) map
,
2029 .delta
= offset
* sizeof(uint32_t),
2030 .target_handle
= results
->gem_handle
,
2031 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
2032 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
2034 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
2036 /* And afterwards clear the register */
2038 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
2043 *batch
++ = MI_BATCH_BUFFER_END
;
2045 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
2047 .handle
= results
->gem_handle
,
2050 .handle
= bo
->gem_handle
,
2051 .relocation_count
= 1,
2052 .relocs_ptr
= (uintptr_t) &reloc
,
2056 struct drm_i915_gem_execbuffer2 execbuf
= {
2057 .buffers_ptr
= (uintptr_t) exec_objects
,
2059 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
2060 .flags
= I915_EXEC_RENDER
,
2063 /* Don't bother with error checking - if the execbuf fails, the
2064 * value won't be written and we'll just report that there's no access.
2066 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2067 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
2069 /* Check whether the value got written. */
2070 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
2072 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
2073 brw_bo_unmap(results
);
2077 brw_bo_unreference(bo
);
2079 brw_bo_unreference(results
);
2085 intel_detect_pipelined_so(struct intel_screen
*screen
)
2087 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2089 /* Supposedly, Broadwell just works. */
2090 if (devinfo
->gen
>= 8)
2093 if (devinfo
->gen
<= 6)
2096 /* See the big explanation about command parser versions below */
2097 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2100 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2101 * statistics registers), and we already reset it to zero before using it.
2103 return intel_detect_pipelined_register(screen
,
2104 GEN7_SO_WRITE_OFFSET(0),
2110 * Return array of MSAA modes supported by the hardware. The array is
2111 * zero-terminated and sorted in decreasing order.
2114 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2116 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2117 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2118 static const int gen7_modes
[] = {8, 4, 0, -1};
2119 static const int gen6_modes
[] = {4, 0, -1};
2120 static const int gen4_modes
[] = {0, -1};
2122 if (screen
->devinfo
.gen
>= 9) {
2124 } else if (screen
->devinfo
.gen
>= 8) {
2126 } else if (screen
->devinfo
.gen
>= 7) {
2128 } else if (screen
->devinfo
.gen
== 6) {
2136 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2138 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2139 dri_screen
->dri2
.loader
->getCapability
)
2140 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2142 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2143 dri_screen
->image
.loader
->getCapability
)
2144 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2149 static __DRIconfig
**
2150 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2152 static const mesa_format formats
[] = {
2153 MESA_FORMAT_B5G6R5_UNORM
,
2154 MESA_FORMAT_B8G8R8A8_UNORM
,
2155 MESA_FORMAT_B8G8R8X8_UNORM
,
2157 MESA_FORMAT_B8G8R8A8_SRGB
,
2159 /* For 10 bpc, 30 bit depth framebuffers. */
2160 MESA_FORMAT_B10G10R10A2_UNORM
,
2161 MESA_FORMAT_B10G10R10X2_UNORM
,
2163 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2164 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2165 * server may disagree on which format the GLXFBConfig represents,
2166 * resulting in swapped color channels.
2168 * The problem, as of 2017-05-30:
2169 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2170 * order and chooses the first __DRIconfig with the expected channel
2171 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2172 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2174 * EGL does not suffer from this problem. It correctly compares the
2175 * channel masks when matching EGLConfig to __DRIconfig.
2178 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2179 MESA_FORMAT_R8G8B8A8_UNORM
,
2181 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2182 MESA_FORMAT_R8G8B8X8_UNORM
,
2184 MESA_FORMAT_R8G8B8A8_SRGB
,
2187 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
2188 static const GLenum back_buffer_modes
[] = {
2189 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2192 static const uint8_t singlesample_samples
[1] = {0};
2194 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2195 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2196 uint8_t depth_bits
[4], stencil_bits
[4];
2197 __DRIconfig
**configs
= NULL
;
2199 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2200 unsigned num_formats
;
2201 if (intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
))
2202 num_formats
= ARRAY_SIZE(formats
);
2204 num_formats
= ARRAY_SIZE(formats
) - 3; /* all - RGBA_ORDERING formats */
2206 /* Shall we expose 10 bpc formats? */
2207 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2208 "allow_rgb10_configs");
2209 /* Shall we expose 565 formats? */
2210 bool allow_rgb565_configs
= driQueryOptionb(&screen
->optionCache
,
2211 "allow_rgb565_configs");
2213 /* Generate singlesample configs, each without accumulation buffer
2214 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
2216 for (unsigned i
= 0; i
< num_formats
; i
++) {
2217 __DRIconfig
**new_configs
;
2218 int num_depth_stencil_bits
= 2;
2220 if (!allow_rgb10_configs
&&
2221 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2222 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2225 if (!allow_rgb565_configs
&& formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
)
2228 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2229 * buffer that has a different number of bits per pixel than the color
2230 * buffer, gen >= 6 supports this.
2233 stencil_bits
[0] = 0;
2235 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2237 stencil_bits
[1] = 0;
2238 if (devinfo
->gen
>= 6) {
2240 stencil_bits
[2] = 8;
2241 num_depth_stencil_bits
= 3;
2245 stencil_bits
[1] = 8;
2248 new_configs
= driCreateConfigs(formats
[i
],
2251 num_depth_stencil_bits
,
2252 back_buffer_modes
, 2,
2253 singlesample_samples
, 1,
2255 /*mutable_render_buffer*/ true);
2256 configs
= driConcatConfigs(configs
, new_configs
);
2259 /* Generate the minimum possible set of configs that include an
2260 * accumulation buffer.
2262 for (unsigned i
= 0; i
< num_formats
; i
++) {
2263 __DRIconfig
**new_configs
;
2265 if (!allow_rgb10_configs
&&
2266 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2267 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2270 if (!allow_rgb565_configs
&& formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
)
2273 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2275 stencil_bits
[0] = 0;
2278 stencil_bits
[0] = 8;
2281 new_configs
= driCreateConfigs(formats
[i
],
2282 depth_bits
, stencil_bits
, 1,
2283 back_buffer_modes
, 1,
2284 singlesample_samples
, 1,
2285 true, false, false);
2286 configs
= driConcatConfigs(configs
, new_configs
);
2289 /* Generate multisample configs.
2291 * This loop breaks early, and hence is a no-op, on gen < 6.
2293 * Multisample configs must follow the singlesample configs in order to
2294 * work around an X server bug present in 1.12. The X server chooses to
2295 * associate the first listed RGBA888-Z24S8 config, regardless of its
2296 * sample count, with the 32-bit depth visual used for compositing.
2298 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2299 * supported. Singlebuffer configs are not supported because no one wants
2302 for (unsigned i
= 0; i
< num_formats
; i
++) {
2303 if (devinfo
->gen
< 6)
2306 if (!allow_rgb10_configs
&&
2307 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2308 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2311 if (!allow_rgb565_configs
&& formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
)
2314 __DRIconfig
**new_configs
;
2315 const int num_depth_stencil_bits
= 2;
2316 int num_msaa_modes
= 0;
2317 const uint8_t *multisample_samples
= NULL
;
2320 stencil_bits
[0] = 0;
2322 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2324 stencil_bits
[1] = 0;
2327 stencil_bits
[1] = 8;
2330 if (devinfo
->gen
>= 9) {
2331 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2332 multisample_samples
= multisample_samples_gen9
;
2333 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2334 } else if (devinfo
->gen
== 8) {
2335 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2336 multisample_samples
= multisample_samples_gen8
;
2337 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2338 } else if (devinfo
->gen
== 7) {
2339 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2340 multisample_samples
= multisample_samples_gen7
;
2341 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2342 } else if (devinfo
->gen
== 6) {
2343 static const uint8_t multisample_samples_gen6
[] = {4};
2344 multisample_samples
= multisample_samples_gen6
;
2345 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2348 new_configs
= driCreateConfigs(formats
[i
],
2351 num_depth_stencil_bits
,
2352 back_buffer_modes
, 1,
2353 multisample_samples
,
2355 false, false, false);
2356 configs
= driConcatConfigs(configs
, new_configs
);
2359 if (configs
== NULL
) {
2360 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2369 set_max_gl_versions(struct intel_screen
*screen
)
2371 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2372 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2374 switch (screen
->devinfo
.gen
) {
2379 dri_screen
->max_gl_core_version
= 45;
2380 dri_screen
->max_gl_compat_version
= 30;
2381 dri_screen
->max_gl_es1_version
= 11;
2382 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2385 dri_screen
->max_gl_core_version
= 33;
2386 if (can_do_pipelined_register_writes(screen
)) {
2387 dri_screen
->max_gl_core_version
= 42;
2388 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2389 dri_screen
->max_gl_core_version
= 43;
2390 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2391 dri_screen
->max_gl_core_version
= 45;
2393 dri_screen
->max_gl_compat_version
= 30;
2394 dri_screen
->max_gl_es1_version
= 11;
2395 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2398 dri_screen
->max_gl_core_version
= 33;
2399 dri_screen
->max_gl_compat_version
= 30;
2400 dri_screen
->max_gl_es1_version
= 11;
2401 dri_screen
->max_gl_es2_version
= 30;
2405 dri_screen
->max_gl_core_version
= 0;
2406 dri_screen
->max_gl_compat_version
= 21;
2407 dri_screen
->max_gl_es1_version
= 11;
2408 dri_screen
->max_gl_es2_version
= 20;
2411 unreachable("unrecognized intel_screen::gen");
2416 * Return the revision (generally the revid field of the PCI header) of the
2420 intel_device_get_revision(int fd
)
2422 struct drm_i915_getparam gp
;
2426 memset(&gp
, 0, sizeof(gp
));
2427 gp
.param
= I915_PARAM_REVISION
;
2428 gp
.value
= &revision
;
2430 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
2438 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2440 struct brw_context
*brw
= (struct brw_context
*)data
;
2443 va_start(args
, fmt
);
2445 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2446 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2447 MESA_DEBUG_TYPE_OTHER
,
2448 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2453 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2455 struct brw_context
*brw
= (struct brw_context
*)data
;
2458 va_start(args
, fmt
);
2460 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2462 va_copy(args_copy
, args
);
2463 vfprintf(stderr
, fmt
, args_copy
);
2467 if (brw
->perf_debug
) {
2469 _mesa_gl_vdebugf(&brw
->ctx
, &msg_id
,
2470 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2471 MESA_DEBUG_TYPE_PERFORMANCE
,
2472 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2478 * This is the driver specific part of the createNewScreen entry point.
2479 * Called when using DRI2.
2481 * \return the struct gl_config supported by this driver
2484 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2486 struct intel_screen
*screen
;
2488 if (dri_screen
->image
.loader
) {
2489 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2490 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2492 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2493 "support required\n");
2497 /* Allocate the private area */
2498 screen
= rzalloc(NULL
, struct intel_screen
);
2500 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2503 /* parse information in __driConfigOptions */
2504 driOptionCache options
;
2505 memset(&options
, 0, sizeof(options
));
2507 driParseOptionInfo(&options
, brw_config_options
.xml
);
2508 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
,
2510 driDestroyOptionCache(&options
);
2512 screen
->driScrnPriv
= dri_screen
;
2513 dri_screen
->driverPrivate
= (void *) screen
;
2515 screen
->deviceID
= gen_get_pci_device_id_override();
2516 if (screen
->deviceID
< 0)
2517 screen
->deviceID
= intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2519 screen
->no_hw
= true;
2521 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2524 screen
->devinfo
.revision
= intel_device_get_revision(dri_screen
->fd
);
2526 if (!intel_init_bufmgr(screen
))
2529 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2531 brw_process_intel_debug_variable();
2533 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2535 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2536 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2539 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2540 /* Theorectically unlimited! At least for individual objects...
2542 * Currently the entire (global) address space for all GTT maps is
2543 * limited to 64bits. That is all objects on the system that are
2544 * setup for GTT mmapping must fit within 64bits. An attempt to use
2545 * one that exceeds the limit with fail in brw_bo_map_gtt().
2547 * Long before we hit that limit, we will be practically limited by
2548 * that any single object must fit in physical memory (RAM). The upper
2549 * limit on the CPU's address space is currently 48bits (Skylake), of
2550 * which only 39bits can be physical memory. (The GPU itself also has
2551 * a 48bit addressable virtual space.) We can fit over 32 million
2552 * objects of the current maximum allocable size before running out
2555 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2557 /* Estimate the size of the mappable aperture into the GTT. There's an
2558 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2559 * It turns out it's basically always 256MB, though some ancient hardware
2562 uint32_t gtt_size
= 256 * 1024 * 1024;
2564 /* We don't want to map two objects such that a memcpy between them would
2565 * just fault one mapping in and then the other over and over forever. So
2566 * we would need to divide the GTT size by 2. Additionally, some GTT is
2567 * taken up by things like the framebuffer and the ringbuffer and such, so
2568 * be more conservative.
2570 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2573 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2575 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2576 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2578 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2579 screen
->hw_has_swizzling
);
2581 if (devinfo
->gen
>= 10)
2582 intel_cs_timestamp_frequency(screen
);
2584 /* GENs prior to 8 do not support EU/Subslice info */
2585 if (devinfo
->gen
>= 8) {
2586 intel_detect_sseu(screen
);
2587 } else if (devinfo
->gen
== 7) {
2588 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2591 /* Gen7-7.5 kernel requirements / command parser saga:
2594 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2596 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2597 * all batches secure, allowing them to use any feature with no checking.
2598 * This is effectively equivalent to a command parser version of
2599 * \infinity - everything is possible.
2601 * The command parser does not exist, and querying the version will
2605 * The kernel enables the command parser by default, for systems with
2606 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2607 * hardware checker is still enabled, so Haswell and Baytrail cannot
2610 * Ivybridge goes from "everything is possible" to "only what the
2611 * command parser allows" (if the user boots with i915.cmd_parser=0,
2612 * then everything is possible again). We can only safely use features
2613 * allowed by the supported command parser version.
2615 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2616 * implemented by the kernel, even if it's turned off. So, checking
2617 * for version > 0 does not mean that you can write registers. We have
2618 * to try it and see. The version does, however, indicate the age of
2621 * Instead of matching the hardware checker's behavior of converting
2622 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2623 * -EINVAL, making it dangerous to try and use privileged features.
2625 * Effective command parser versions:
2626 * - Haswell: 0 (reporting 1, writes don't work)
2627 * - Baytrail: 0 (reporting 1, writes don't work)
2628 * - Ivybridge: 1 (enabled) or infinite (disabled)
2631 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2632 * effectively version 1 (enabled) or infinite (disabled).
2634 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2635 * Command parser v2 supports predicate writes.
2637 * - Haswell: 0 (reporting 1, writes don't work)
2638 * - Baytrail: 2 (enabled) or infinite (disabled)
2639 * - Ivybridge: 2 (enabled) or infinite (disabled)
2641 * So version >= 2 is enough to know that Ivybridge and Baytrail
2642 * will work. Haswell still can't do anything.
2644 * - v4.0: Version 3 happened. Largely not relevant.
2646 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2647 * L3 config registers are properly saved and restored as part
2648 * of the hardware context. We can approximately detect this point
2649 * in time by checking if I915_PARAM_REVISION is recognized - it
2650 * landed in a later commit, but in the same release cycle.
2652 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2653 * Command parser finally gains secure batch promotion. On Haswell,
2654 * the hardware checker gets disabled, which finally allows it to do
2655 * privileged commands.
2657 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2658 * - Haswell: 3 (enabled) or 0 (disabled)
2659 * - Baytrail: 3 (enabled) or infinite (disabled)
2660 * - Ivybridge: 3 (enabled) or infinite (disabled)
2662 * Unfortunately, detecting this point in time is tricky, because
2663 * no version bump happened when this important change occurred.
2664 * On Haswell, if we can write any register, then the kernel is at
2665 * least this new, and we can start trusting the version number.
2667 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2668 * Command parser reaches version 4, allowing access to Haswell
2669 * atomic scratch and chicken3 registers. If version >= 4, we know
2670 * the kernel is new enough to support privileged features on all
2671 * hardware. However, the user might have disabled it...and the
2672 * kernel will still report version 4. So we still have to guess
2675 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2676 * Command parser v5 whitelists indirect compute shader dispatch
2677 * registers, needed for OpenGL 4.3 and later.
2680 * Command parser v7 lets us use MI_MATH on Haswell.
2682 * Additionally, the kernel begins reporting version 0 when
2683 * the command parser is disabled, allowing us to skip the
2684 * guess-and-check step on Haswell. Unfortunately, this also
2685 * means that we can no longer use it as an indicator of the
2686 * age of the kernel.
2688 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2689 &screen
->cmd_parser_version
) < 0) {
2690 /* Command parser does not exist - getparam is unrecognized */
2691 screen
->cmd_parser_version
= 0;
2694 /* Kernel 4.13 retuired for exec object capture */
2695 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2696 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2699 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2700 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2703 if (!intel_detect_pipelined_so(screen
)) {
2704 /* We can't do anything, so the effective version is 0. */
2705 screen
->cmd_parser_version
= 0;
2707 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2710 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2711 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2713 /* Haswell requires command parser version 4 in order to have L3
2714 * atomic scratch1 and chicken3 bits
2716 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2717 screen
->kernel_features
|=
2718 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2721 /* Haswell requires command parser version 6 in order to write to the
2722 * MI_MATH GPR registers, and version 7 in order to use
2723 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2725 if (devinfo
->gen
>= 8 ||
2726 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2727 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2730 /* Gen7 needs at least command parser version 5 to support compute */
2731 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2732 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2734 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2735 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2737 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2739 screen
->winsys_msaa_samples_override
=
2740 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2741 printf("Forcing winsys sample count to %d\n",
2742 screen
->winsys_msaa_samples_override
);
2744 screen
->winsys_msaa_samples_override
= -1;
2747 set_max_gl_versions(screen
);
2749 /* Notification of GPU resets requires hardware contexts and a kernel new
2750 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2751 * supported, calling it with a context of 0 will either generate EPERM or
2752 * no error. If the ioctl is not supported, it always generate EINVAL.
2753 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2754 * extension to the loader.
2756 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2758 if (devinfo
->gen
>= 6) {
2759 struct drm_i915_reset_stats stats
;
2760 memset(&stats
, 0, sizeof(stats
));
2762 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2764 screen
->has_context_reset_notification
=
2765 (ret
!= -1 || errno
!= EINVAL
);
2768 dri_screen
->extensions
= !screen
->has_context_reset_notification
2769 ? screenExtensions
: intelRobustScreenExtensions
;
2771 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2772 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2773 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2775 /* Changing the meaning of constant buffer pointers from a dynamic state
2776 * offset to an absolute address is only safe if the kernel isolates other
2777 * contexts from our changes.
2779 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8 ||
2780 !(screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
);
2782 screen
->compiler
->supports_pull_constants
= true;
2784 screen
->has_exec_fence
=
2785 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2787 intel_screen_init_surface_formats(screen
);
2789 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2790 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2792 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2793 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2794 fprintf(stderr
, " - User priority sorting enabled\n");
2795 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2796 fprintf(stderr
, " - Preemption enabled\n");
2800 brw_disk_cache_init(screen
);
2802 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2805 struct intel_buffer
{
2810 static __DRIbuffer
*
2811 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2812 unsigned attachment
, unsigned format
,
2813 int width
, int height
)
2815 struct intel_buffer
*intelBuffer
;
2816 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2818 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2819 attachment
== __DRI_BUFFER_BACK_LEFT
);
2821 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2822 if (intelBuffer
== NULL
)
2825 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2826 * supports Y tiled and compressed buffers, but there is no way to plumb that
2827 * through to here. */
2829 int cpp
= format
/ 8;
2830 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2831 "intelAllocateBuffer",
2836 I915_TILING_X
, &pitch
,
2839 if (intelBuffer
->bo
== NULL
) {
2844 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2846 intelBuffer
->base
.attachment
= attachment
;
2847 intelBuffer
->base
.cpp
= cpp
;
2848 intelBuffer
->base
.pitch
= pitch
;
2850 return &intelBuffer
->base
;
2854 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2856 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2858 brw_bo_unreference(intelBuffer
->bo
);
2862 static const struct __DriverAPIRec brw_driver_api
= {
2863 .InitScreen
= intelInitScreen2
,
2864 .DestroyScreen
= intelDestroyScreen
,
2865 .CreateContext
= brwCreateContext
,
2866 .DestroyContext
= intelDestroyContext
,
2867 .CreateBuffer
= intelCreateBuffer
,
2868 .DestroyBuffer
= intelDestroyBuffer
,
2869 .MakeCurrent
= intelMakeCurrent
,
2870 .UnbindContext
= intelUnbindContext
,
2871 .AllocateBuffer
= intelAllocateBuffer
,
2872 .ReleaseBuffer
= intelReleaseBuffer
2875 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2876 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2877 .vtable
= &brw_driver_api
,
2880 static const __DRIextension
*brw_driver_extensions
[] = {
2881 &driCoreExtension
.base
,
2882 &driImageDriverExtension
.base
,
2883 &driDRI2Extension
.base
,
2885 &brw_config_options
.base
,
2889 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2891 globalDriverAPI
= &brw_driver_api
;
2893 return brw_driver_extensions
;