2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "brw_state.h"
41 #include "compiler/nir/nir.h"
44 #include "util/xmlpool.h"
46 static const __DRIconfigOptionsExtension brw_config_options
= {
47 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
50 DRI_CONF_SECTION_PERFORMANCE
51 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
52 * DRI_CONF_BO_REUSE_ALL
54 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
55 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
56 DRI_CONF_ENUM(0, "Disable buffer object reuse")
57 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_MESA_NO_ERROR("false")
63 DRI_CONF_SECTION_QUALITY
64 DRI_CONF_PRECISE_TRIG("false")
66 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
67 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
68 "given integer. If negative, then do not clamp.")
72 DRI_CONF_SECTION_DEBUG
73 DRI_CONF_NO_RAST("false")
74 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
75 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
76 DRI_CONF_DISABLE_THROTTLING("false")
77 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
78 DRI_CONF_FORCE_GLSL_VERSION(0)
79 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
80 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
81 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
82 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
83 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
84 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
85 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
87 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
88 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
92 DRI_CONF_SECTION_MISCELLANEOUS
93 DRI_CONF_GLSL_ZERO_INIT("false")
98 #include "intel_batchbuffer.h"
99 #include "intel_buffers.h"
100 #include "brw_bufmgr.h"
101 #include "intel_fbo.h"
102 #include "intel_mipmap_tree.h"
103 #include "intel_screen.h"
104 #include "intel_tex.h"
105 #include "intel_image.h"
107 #include "brw_context.h"
109 #include "i915_drm.h"
112 * For debugging purposes, this returns a time in seconds.
119 clock_gettime(CLOCK_MONOTONIC
, &tp
);
121 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
124 static const __DRItexBufferExtension intelTexBufferExtension
= {
125 .base
= { __DRI_TEX_BUFFER
, 3 },
127 .setTexBuffer
= intelSetTexBuffer
,
128 .setTexBuffer2
= intelSetTexBuffer2
,
129 .releaseTexBuffer
= NULL
,
133 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
134 __DRIdrawable
*dPriv
,
136 enum __DRI2throttleReason reason
)
138 struct brw_context
*brw
= cPriv
->driverPrivate
;
143 struct gl_context
*ctx
= &brw
->ctx
;
145 FLUSH_VERTICES(ctx
, 0);
147 if (flags
& __DRI2_FLUSH_DRAWABLE
)
148 intel_resolve_for_dri2_flush(brw
, dPriv
);
150 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
151 brw
->need_swap_throttle
= true;
152 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
153 brw
->need_flush_throttle
= true;
155 intel_batchbuffer_flush(brw
);
159 * Provides compatibility with loaders that only support the older (version
160 * 1-3) flush interface.
162 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
165 intel_dri2_flush(__DRIdrawable
*drawable
)
167 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
168 __DRI2_FLUSH_DRAWABLE
,
169 __DRI2_THROTTLE_SWAPBUFFER
);
172 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
173 .base
= { __DRI2_FLUSH
, 4 },
175 .flush
= intel_dri2_flush
,
176 .invalidate
= dri2InvalidateDrawable
,
177 .flush_with_flags
= intel_dri2_flush_with_flags
,
180 static const struct intel_image_format intel_image_formats
[] = {
181 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
182 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
184 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
185 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
187 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
188 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
190 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
191 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
193 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
194 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
196 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
197 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
199 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
200 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
202 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
203 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
205 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
206 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
208 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
209 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
211 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
212 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
214 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
215 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
216 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
217 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
219 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
221 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
222 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
224 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
226 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
227 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
229 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
230 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
231 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
232 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
234 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
236 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
237 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
239 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
241 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
242 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
244 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
245 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
246 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
247 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
249 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
250 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
254 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
255 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
259 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
260 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
264 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
265 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
268 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
269 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
272 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
273 * and treat them as planar buffers in the compositors.
274 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
275 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
276 * clusters and places pairs and places U into the G component and
277 * V into A. This lets the texture sampler interpolate the Y
278 * components correctly when sampling from plane 0, and interpolate
279 * U and V correctly when sampling from plane 1. */
280 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
281 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
282 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
283 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
284 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
285 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
288 static const struct {
291 } supported_modifiers
[] = {
292 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
293 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
294 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
295 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
299 modifier_is_supported(const struct gen_device_info
*devinfo
,
300 const struct intel_image_format
*fmt
, int dri_format
,
303 const struct isl_drm_modifier_info
*modinfo
=
304 isl_drm_modifier_get_info(modifier
);
307 /* ISL had better know about the modifier */
311 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
312 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
313 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
316 /* CCS_E is not supported for planar images */
317 if (fmt
&& fmt
->nplanes
> 1)
321 assert(dri_format
== 0);
322 dri_format
= fmt
->planes
[0].dri_format
;
325 mesa_format format
= driImageFormatToGLFormat(dri_format
);
326 format
= _mesa_get_srgb_format_linear(format
);
327 if (!isl_format_supports_ccs_e(devinfo
,
328 brw_isl_format_for_mesa_format(format
)))
332 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
333 if (supported_modifiers
[i
].modifier
!= modifier
)
336 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
343 tiling_to_modifier(uint32_t tiling
)
345 static const uint64_t map
[] = {
346 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
347 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
348 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
351 assert(tiling
< ARRAY_SIZE(map
));
357 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
359 uint32_t tiling
, swizzle
;
360 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
362 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
363 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
364 func
, image
->offset
);
368 static const struct intel_image_format
*
369 intel_image_format_lookup(int fourcc
)
371 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
372 if (intel_image_formats
[i
].fourcc
== fourcc
)
373 return &intel_image_formats
[i
];
379 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
381 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
382 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
383 *fourcc
= intel_image_formats
[i
].fourcc
;
391 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
396 image
= calloc(1, sizeof *image
);
400 image
->screen
= screen
;
401 image
->dri_format
= dri_format
;
404 image
->format
= driImageFormatToGLFormat(dri_format
);
405 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
406 image
->format
== MESA_FORMAT_NONE
) {
411 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
412 image
->data
= loaderPrivate
;
418 * Sets up a DRIImage structure to point to a slice out of a miptree.
421 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
422 struct intel_mipmap_tree
*mt
, GLuint level
,
425 intel_miptree_make_shareable(brw
, mt
);
427 intel_miptree_check_level_layer(mt
, level
, zoffset
);
429 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
430 level
- mt
->first_level
);
431 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
432 level
- mt
->first_level
);
433 image
->pitch
= mt
->surf
.row_pitch
;
435 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
439 brw_bo_unreference(image
->bo
);
441 brw_bo_reference(mt
->bo
);
445 intel_create_image_from_name(__DRIscreen
*dri_screen
,
446 int width
, int height
, int format
,
447 int name
, int pitch
, void *loaderPrivate
)
449 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
453 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
457 if (image
->format
== MESA_FORMAT_NONE
)
460 cpp
= _mesa_get_format_bytes(image
->format
);
462 image
->width
= width
;
463 image
->height
= height
;
464 image
->pitch
= pitch
* cpp
;
465 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
471 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
477 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
478 int renderbuffer
, void *loaderPrivate
)
481 struct brw_context
*brw
= context
->driverPrivate
;
482 struct gl_context
*ctx
= &brw
->ctx
;
483 struct gl_renderbuffer
*rb
;
484 struct intel_renderbuffer
*irb
;
486 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
488 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
492 irb
= intel_renderbuffer(rb
);
493 intel_miptree_make_shareable(brw
, irb
->mt
);
494 image
= calloc(1, sizeof *image
);
498 image
->internal_format
= rb
->InternalFormat
;
499 image
->format
= rb
->Format
;
500 image
->modifier
= tiling_to_modifier(
501 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
503 image
->data
= loaderPrivate
;
504 brw_bo_unreference(image
->bo
);
505 image
->bo
= irb
->mt
->bo
;
506 brw_bo_reference(irb
->mt
->bo
);
507 image
->width
= rb
->Width
;
508 image
->height
= rb
->Height
;
509 image
->pitch
= irb
->mt
->surf
.row_pitch
;
510 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
511 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
513 rb
->NeedsFinishRenderTexture
= true;
518 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
519 unsigned texture
, int zoffset
,
525 struct brw_context
*brw
= context
->driverPrivate
;
526 struct gl_texture_object
*obj
;
527 struct intel_texture_object
*iobj
;
530 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
531 if (!obj
|| obj
->Target
!= target
) {
532 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
536 if (target
== GL_TEXTURE_CUBE_MAP
)
539 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
540 iobj
= intel_texture_object(obj
);
541 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
542 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
546 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
547 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
551 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
552 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
555 image
= calloc(1, sizeof *image
);
557 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
561 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
562 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
563 image
->modifier
= tiling_to_modifier(
564 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
565 image
->data
= loaderPrivate
;
566 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
567 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
568 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
569 if (image
->dri_format
== MESA_FORMAT_NONE
) {
570 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
575 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
580 intel_destroy_image(__DRIimage
*image
)
582 brw_bo_unreference(image
->bo
);
586 enum modifier_priority
{
587 MODIFIER_PRIORITY_INVALID
= 0,
588 MODIFIER_PRIORITY_LINEAR
,
591 MODIFIER_PRIORITY_Y_CCS
,
594 const uint64_t priority_to_modifier
[] = {
595 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
596 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
597 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
598 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
599 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
603 select_best_modifier(struct gen_device_info
*devinfo
,
605 const uint64_t *modifiers
,
606 const unsigned count
)
608 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
610 for (int i
= 0; i
< count
; i
++) {
611 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
614 switch (modifiers
[i
]) {
615 case I915_FORMAT_MOD_Y_TILED_CCS
:
616 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
618 case I915_FORMAT_MOD_Y_TILED
:
619 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
621 case I915_FORMAT_MOD_X_TILED
:
622 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
624 case DRM_FORMAT_MOD_LINEAR
:
625 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
627 case DRM_FORMAT_MOD_INVALID
:
633 return priority_to_modifier
[prio
];
637 intel_create_image_common(__DRIscreen
*dri_screen
,
638 int width
, int height
, int format
,
640 const uint64_t *modifiers
,
645 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
646 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
649 /* Callers of this may specify a modifier, or a dri usage, but not both. The
650 * newer modifier interface deprecates the older usage flags newer modifier
651 * interface deprecates the older usage flags.
653 assert(!(use
&& count
));
655 if (use
& __DRI_IMAGE_USE_CURSOR
) {
656 if (width
!= 64 || height
!= 64)
658 modifier
= DRM_FORMAT_MOD_LINEAR
;
661 if (use
& __DRI_IMAGE_USE_LINEAR
)
662 modifier
= DRM_FORMAT_MOD_LINEAR
;
664 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
666 /* User requested specific modifiers */
667 modifier
= select_best_modifier(&screen
->devinfo
, format
,
669 if (modifier
== DRM_FORMAT_MOD_INVALID
)
672 /* Historically, X-tiled was the default, and so lack of modifier means
675 modifier
= I915_FORMAT_MOD_X_TILED
;
679 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
683 const struct isl_drm_modifier_info
*mod_info
=
684 isl_drm_modifier_get_info(modifier
);
686 struct isl_surf surf
;
687 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
688 .dim
= ISL_SURF_DIM_2D
,
689 .format
= brw_isl_format_for_mesa_format(image
->format
),
696 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
697 ISL_SURF_USAGE_TEXTURE_BIT
|
698 ISL_SURF_USAGE_STORAGE_BIT
,
699 .tiling_flags
= (1 << mod_info
->tiling
));
706 struct isl_surf aux_surf
;
707 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
708 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, 0);
714 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
718 /* We request that the bufmgr zero the buffer for us for two reasons:
720 * 1) If a buffer gets re-used from the pool, we don't want to leak random
721 * garbage from our process to some other.
723 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
724 * a valid state. A CCS value of 0 indicates that the given block is
725 * in the pass-through state which is what we want.
727 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
728 surf
.size
+ aux_surf
.size
,
729 isl_tiling_to_i915_tiling(mod_info
->tiling
),
730 surf
.row_pitch
, BO_ALLOC_ZEROED
);
731 if (image
->bo
== NULL
) {
735 image
->width
= width
;
736 image
->height
= height
;
737 image
->pitch
= surf
.row_pitch
;
738 image
->modifier
= modifier
;
741 image
->aux_offset
= surf
.size
;
742 image
->aux_pitch
= aux_surf
.row_pitch
;
749 intel_create_image(__DRIscreen
*dri_screen
,
750 int width
, int height
, int format
,
754 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
759 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
760 int width
, int height
, int format
,
761 const uint64_t *modifiers
,
762 const unsigned count
,
765 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
766 modifiers
, count
, loaderPrivate
);
770 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
773 case __DRI_IMAGE_ATTRIB_STRIDE
:
774 *value
= image
->pitch
;
776 case __DRI_IMAGE_ATTRIB_HANDLE
:
777 *value
= image
->bo
->gem_handle
;
779 case __DRI_IMAGE_ATTRIB_NAME
:
780 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
781 case __DRI_IMAGE_ATTRIB_FORMAT
:
782 *value
= image
->dri_format
;
784 case __DRI_IMAGE_ATTRIB_WIDTH
:
785 *value
= image
->width
;
787 case __DRI_IMAGE_ATTRIB_HEIGHT
:
788 *value
= image
->height
;
790 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
791 if (image
->planar_format
== NULL
)
793 *value
= image
->planar_format
->components
;
795 case __DRI_IMAGE_ATTRIB_FD
:
796 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
797 case __DRI_IMAGE_ATTRIB_FOURCC
:
798 return intel_lookup_fourcc(image
->dri_format
, value
);
799 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
800 if (isl_drm_modifier_has_aux(image
->modifier
)) {
801 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
803 } else if (image
->planar_format
) {
804 *value
= image
->planar_format
->nplanes
;
809 case __DRI_IMAGE_ATTRIB_OFFSET
:
810 *value
= image
->offset
;
812 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
813 *value
= (image
->modifier
& 0xffffffff);
815 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
816 *value
= ((image
->modifier
>> 32) & 0xffffffff);
825 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
826 uint32_t fourcc
, uint64_t modifier
,
827 int attrib
, uint64_t *value
)
829 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
830 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
832 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
836 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
837 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
846 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
850 image
= calloc(1, sizeof *image
);
854 brw_bo_reference(orig_image
->bo
);
855 image
->bo
= orig_image
->bo
;
856 image
->internal_format
= orig_image
->internal_format
;
857 image
->planar_format
= orig_image
->planar_format
;
858 image
->dri_format
= orig_image
->dri_format
;
859 image
->format
= orig_image
->format
;
860 image
->modifier
= orig_image
->modifier
;
861 image
->offset
= orig_image
->offset
;
862 image
->width
= orig_image
->width
;
863 image
->height
= orig_image
->height
;
864 image
->pitch
= orig_image
->pitch
;
865 image
->tile_x
= orig_image
->tile_x
;
866 image
->tile_y
= orig_image
->tile_y
;
867 image
->has_depthstencil
= orig_image
->has_depthstencil
;
868 image
->data
= loaderPrivate
;
869 image
->dma_buf_imported
= orig_image
->dma_buf_imported
;
870 image
->aux_offset
= orig_image
->aux_offset
;
871 image
->aux_pitch
= orig_image
->aux_pitch
;
873 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
874 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
880 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
882 if (use
& __DRI_IMAGE_USE_CURSOR
) {
883 if (image
->width
!= 64 || image
->height
!= 64)
891 intel_create_image_from_names(__DRIscreen
*dri_screen
,
892 int width
, int height
, int fourcc
,
893 int *names
, int num_names
,
894 int *strides
, int *offsets
,
897 const struct intel_image_format
*f
= NULL
;
901 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
904 f
= intel_image_format_lookup(fourcc
);
908 image
= intel_create_image_from_name(dri_screen
, width
, height
,
909 __DRI_IMAGE_FORMAT_NONE
,
910 names
[0], strides
[0],
916 image
->planar_format
= f
;
917 for (i
= 0; i
< f
->nplanes
; i
++) {
918 index
= f
->planes
[i
].buffer_index
;
919 image
->offsets
[index
] = offsets
[index
];
920 image
->strides
[index
] = strides
[index
];
927 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
928 int width
, int height
, int fourcc
,
929 uint64_t modifier
, int *fds
, int num_fds
,
930 int *strides
, int *offsets
,
933 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
934 const struct intel_image_format
*f
;
939 if (fds
== NULL
|| num_fds
< 1)
942 f
= intel_image_format_lookup(fourcc
);
946 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
947 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
951 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
954 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
960 image
->width
= width
;
961 image
->height
= height
;
962 image
->pitch
= strides
[0];
964 image
->planar_format
= f
;
966 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
967 if (image
->bo
== NULL
) {
972 /* We only support all planes from the same bo.
973 * brw_bo_gem_create_from_prime() should return the same pointer for all
974 * fds received here */
975 for (i
= 1; i
< num_fds
; i
++) {
976 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
977 brw_bo_unreference(aux
);
978 if (aux
!= image
->bo
) {
979 brw_bo_unreference(image
->bo
);
985 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
986 image
->modifier
= modifier
;
988 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
990 const struct isl_drm_modifier_info
*mod_info
=
991 isl_drm_modifier_get_info(image
->modifier
);
994 struct isl_surf surf
;
995 for (i
= 0; i
< f
->nplanes
; i
++) {
996 index
= f
->planes
[i
].buffer_index
;
997 image
->offsets
[index
] = offsets
[index
];
998 image
->strides
[index
] = strides
[index
];
1000 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1002 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1003 .dim
= ISL_SURF_DIM_2D
,
1004 .format
= brw_isl_format_for_mesa_format(format
),
1005 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1006 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1011 .row_pitch
= strides
[index
],
1012 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1013 ISL_SURF_USAGE_TEXTURE_BIT
|
1014 ISL_SURF_USAGE_STORAGE_BIT
,
1015 .tiling_flags
= (1 << mod_info
->tiling
));
1017 brw_bo_unreference(image
->bo
);
1022 const int end
= offsets
[index
] + surf
.size
;
1027 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1028 /* Even though we initialize surf in the loop above, we know that
1029 * anything with CCS_E will have exactly one plane so surf is properly
1030 * initialized when we get here.
1032 assert(f
->nplanes
== 1);
1034 image
->aux_offset
= offsets
[1];
1035 image
->aux_pitch
= strides
[1];
1037 /* Scanout hardware requires that the CCS be placed after the main
1038 * surface in memory. We consider any CCS that is placed any earlier in
1039 * memory to be invalid and reject it.
1041 * At some point in the future, this restriction may be relaxed if the
1042 * hardware becomes less strict but we may need a new modifier for that.
1045 if (image
->aux_offset
< size
) {
1046 brw_bo_unreference(image
->bo
);
1051 struct isl_surf aux_surf
;
1052 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
,
1055 brw_bo_unreference(image
->bo
);
1060 const int end
= image
->aux_offset
+ aux_surf
.size
;
1064 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1067 /* Check that the requested image actually fits within the BO. 'size'
1068 * is already relative to the offsets, so we don't need to add that. */
1069 if (image
->bo
->size
== 0) {
1070 image
->bo
->size
= size
;
1071 } else if (size
> image
->bo
->size
) {
1072 brw_bo_unreference(image
->bo
);
1077 if (f
->nplanes
== 1) {
1078 image
->offset
= image
->offsets
[0];
1079 intel_image_warn_if_unaligned(image
, __func__
);
1086 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1087 int width
, int height
, int fourcc
,
1088 int *fds
, int num_fds
, int *strides
, int *offsets
,
1089 void *loaderPrivate
)
1091 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1092 DRM_FORMAT_MOD_INVALID
,
1093 fds
, num_fds
, strides
, offsets
,
1098 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1099 int width
, int height
,
1100 int fourcc
, uint64_t modifier
,
1101 int *fds
, int num_fds
,
1102 int *strides
, int *offsets
,
1103 enum __DRIYUVColorSpace yuv_color_space
,
1104 enum __DRISampleRange sample_range
,
1105 enum __DRIChromaSiting horizontal_siting
,
1106 enum __DRIChromaSiting vertical_siting
,
1108 void *loaderPrivate
)
1111 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1114 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1118 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1120 fds
, num_fds
, strides
, offsets
,
1124 * Invalid parameters and any inconsistencies between are assumed to be
1125 * checked by the caller. Therefore besides unsupported formats one can fail
1126 * only in allocation.
1129 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1133 image
->dma_buf_imported
= true;
1134 image
->yuv_color_space
= yuv_color_space
;
1135 image
->sample_range
= sample_range
;
1136 image
->horizontal_siting
= horizontal_siting
;
1137 image
->vertical_siting
= vertical_siting
;
1139 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1144 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1145 int width
, int height
, int fourcc
,
1146 int *fds
, int num_fds
,
1147 int *strides
, int *offsets
,
1148 enum __DRIYUVColorSpace yuv_color_space
,
1149 enum __DRISampleRange sample_range
,
1150 enum __DRIChromaSiting horizontal_siting
,
1151 enum __DRIChromaSiting vertical_siting
,
1153 void *loaderPrivate
)
1155 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1156 fourcc
, DRM_FORMAT_MOD_INVALID
,
1157 fds
, num_fds
, strides
, offsets
,
1167 intel_query_dma_buf_formats(__DRIscreen
*screen
, int max
,
1168 int *formats
, int *count
)
1173 *count
= ARRAY_SIZE(intel_image_formats
) - 1; /* not SARGB */
1177 for (i
= 0; i
< (ARRAY_SIZE(intel_image_formats
)) && j
< max
; i
++) {
1178 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
)
1180 formats
[j
++] = intel_image_formats
[i
].fourcc
;
1188 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1189 uint64_t *modifiers
,
1190 unsigned int *external_only
,
1193 struct intel_screen
*screen
= _screen
->driverPrivate
;
1194 const struct intel_image_format
*f
;
1195 int num_mods
= 0, i
;
1197 f
= intel_image_format_lookup(fourcc
);
1201 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1202 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1203 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1210 modifiers
[num_mods
- 1] = modifier
;
1211 if (num_mods
>= max
)
1215 if (external_only
!= NULL
) {
1216 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1217 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1218 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1219 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1220 external_only
[i
] = GL_TRUE
;
1223 external_only
[i
] = GL_FALSE
;
1233 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1235 int width
, height
, offset
, stride
, dri_format
, index
;
1236 const struct intel_image_format
*f
;
1239 if (parent
== NULL
) {
1241 } else if (parent
->planar_format
== NULL
) {
1243 isl_drm_modifier_has_aux(parent
->modifier
) && plane
== 1;
1247 width
= parent
->width
;
1248 height
= parent
->height
;
1249 dri_format
= parent
->dri_format
;
1250 offset
= parent
->aux_offset
;
1251 stride
= parent
->aux_pitch
;
1253 /* Planar formats don't support aux buffers/images */
1254 assert(!isl_drm_modifier_has_aux(parent
->modifier
));
1255 f
= parent
->planar_format
;
1257 if (plane
>= f
->nplanes
)
1260 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
1261 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
1262 dri_format
= f
->planes
[plane
].dri_format
;
1263 index
= f
->planes
[plane
].buffer_index
;
1264 offset
= parent
->offsets
[index
];
1265 stride
= parent
->strides
[index
];
1267 if (offset
+ height
* stride
> parent
->bo
->size
) {
1268 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
1273 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1277 image
->bo
= parent
->bo
;
1278 brw_bo_reference(parent
->bo
);
1279 image
->modifier
= parent
->modifier
;
1281 image
->width
= width
;
1282 image
->height
= height
;
1283 image
->pitch
= stride
;
1284 image
->offset
= offset
;
1286 intel_image_warn_if_unaligned(image
, __func__
);
1291 static const __DRIimageExtension intelImageExtension
= {
1292 .base
= { __DRI_IMAGE
, 16 },
1294 .createImageFromName
= intel_create_image_from_name
,
1295 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1296 .destroyImage
= intel_destroy_image
,
1297 .createImage
= intel_create_image
,
1298 .queryImage
= intel_query_image
,
1299 .dupImage
= intel_dup_image
,
1300 .validateUsage
= intel_validate_usage
,
1301 .createImageFromNames
= intel_create_image_from_names
,
1302 .fromPlanar
= intel_from_planar
,
1303 .createImageFromTexture
= intel_create_image_from_texture
,
1304 .createImageFromFds
= intel_create_image_from_fds
,
1305 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1307 .getCapabilities
= NULL
,
1310 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1311 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1312 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1313 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1314 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1318 get_aperture_size(int fd
)
1320 struct drm_i915_gem_get_aperture aperture
;
1322 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1325 return aperture
.aper_size
;
1329 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1330 int param
, unsigned int *value
)
1332 const struct intel_screen
*const screen
=
1333 (struct intel_screen
*) dri_screen
->driverPrivate
;
1336 case __DRI2_RENDERER_VENDOR_ID
:
1339 case __DRI2_RENDERER_DEVICE_ID
:
1340 value
[0] = screen
->deviceID
;
1342 case __DRI2_RENDERER_ACCELERATED
:
1345 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1346 /* Once a batch uses more than 75% of the maximum mappable size, we
1347 * assume that there's some fragmentation, and we start doing extra
1348 * flushing, etc. That's the big cliff apps will care about.
1350 const unsigned gpu_mappable_megabytes
=
1351 screen
->aperture_threshold
/ (1024 * 1024);
1353 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1354 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1356 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1359 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1360 * (uint64_t) system_page_size
;
1362 const unsigned system_memory_megabytes
=
1363 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1365 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1368 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1371 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1374 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1376 if (brw_hw_context_set_priority(screen
->bufmgr
,
1377 0, BRW_CONTEXT_HIGH_PRIORITY
) == 0)
1378 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1379 if (brw_hw_context_set_priority(screen
->bufmgr
,
1380 0, BRW_CONTEXT_LOW_PRIORITY
) == 0)
1381 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1382 /* reset to default last, just in case */
1383 if (brw_hw_context_set_priority(screen
->bufmgr
,
1384 0, BRW_CONTEXT_MEDIUM_PRIORITY
) == 0)
1385 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1388 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1395 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1396 int param
, const char **value
)
1398 const struct intel_screen
*screen
=
1399 (struct intel_screen
*) dri_screen
->driverPrivate
;
1402 case __DRI2_RENDERER_VENDOR_ID
:
1403 value
[0] = brw_vendor_string
;
1405 case __DRI2_RENDERER_DEVICE_ID
:
1406 value
[0] = brw_get_renderer_string(screen
);
1415 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1416 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1418 .queryInteger
= brw_query_renderer_integer
,
1419 .queryString
= brw_query_renderer_string
1422 static const __DRIrobustnessExtension dri2Robustness
= {
1423 .base
= { __DRI2_ROBUSTNESS
, 1 }
1426 static const __DRIextension
*screenExtensions
[] = {
1427 &intelTexBufferExtension
.base
,
1428 &intelFenceExtension
.base
,
1429 &intelFlushExtension
.base
,
1430 &intelImageExtension
.base
,
1431 &intelRendererQueryExtension
.base
,
1432 &dri2ConfigQueryExtension
.base
,
1433 &dri2NoErrorExtension
.base
,
1434 &dri2FlushControlExtension
.base
,
1438 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1439 &intelTexBufferExtension
.base
,
1440 &intelFenceExtension
.base
,
1441 &intelFlushExtension
.base
,
1442 &intelImageExtension
.base
,
1443 &intelRendererQueryExtension
.base
,
1444 &dri2ConfigQueryExtension
.base
,
1445 &dri2FlushControlExtension
.base
,
1446 &dri2Robustness
.base
,
1447 &dri2NoErrorExtension
.base
,
1452 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1455 struct drm_i915_getparam gp
;
1457 memset(&gp
, 0, sizeof(gp
));
1461 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1464 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1471 intel_get_boolean(struct intel_screen
*screen
, int param
)
1474 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1478 intel_get_integer(struct intel_screen
*screen
, int param
)
1482 if (intel_get_param(screen
, param
, &value
) == 0)
1489 intelDestroyScreen(__DRIscreen
* sPriv
)
1491 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1493 brw_bufmgr_destroy(screen
->bufmgr
);
1494 driDestroyOptionInfo(&screen
->optionCache
);
1496 ralloc_free(screen
);
1497 sPriv
->driverPrivate
= NULL
;
1502 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1504 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1505 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1506 * this does not allocate GPU memory.
1509 intelCreateBuffer(__DRIscreen
*dri_screen
,
1510 __DRIdrawable
* driDrawPriv
,
1511 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1513 struct intel_renderbuffer
*rb
;
1514 struct intel_screen
*screen
= (struct intel_screen
*)
1515 dri_screen
->driverPrivate
;
1516 mesa_format rgbFormat
;
1517 unsigned num_samples
=
1518 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1523 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1527 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1529 if (screen
->winsys_msaa_samples_override
!= -1) {
1530 num_samples
= screen
->winsys_msaa_samples_override
;
1531 fb
->Visual
.samples
= num_samples
;
1534 if (mesaVis
->redBits
== 5) {
1535 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1536 : MESA_FORMAT_B5G6R5_UNORM
;
1537 } else if (mesaVis
->sRGBCapable
) {
1538 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1539 : MESA_FORMAT_B8G8R8A8_SRGB
;
1540 } else if (mesaVis
->alphaBits
== 0) {
1541 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1542 : MESA_FORMAT_B8G8R8X8_UNORM
;
1544 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1545 : MESA_FORMAT_B8G8R8A8_SRGB
;
1546 fb
->Visual
.sRGBCapable
= true;
1549 /* setup the hardware-based renderbuffers */
1550 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1551 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1553 if (mesaVis
->doubleBufferMode
) {
1554 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1555 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1559 * Assert here that the gl_config has an expected depth/stencil bit
1560 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1561 * which constructs the advertised configs.)
1563 if (mesaVis
->depthBits
== 24) {
1564 assert(mesaVis
->stencilBits
== 8);
1566 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1567 rb
= intel_create_private_renderbuffer(screen
,
1568 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1570 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1571 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1573 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1576 * Use combined depth/stencil. Note that the renderbuffer is
1577 * attached to two attachment points.
1579 rb
= intel_create_private_renderbuffer(screen
,
1580 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1582 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1583 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1586 else if (mesaVis
->depthBits
== 16) {
1587 assert(mesaVis
->stencilBits
== 0);
1588 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1590 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1593 assert(mesaVis
->depthBits
== 0);
1594 assert(mesaVis
->stencilBits
== 0);
1597 /* now add any/all software-based renderbuffers we may need */
1598 _swrast_add_soft_renderbuffers(fb
,
1599 false, /* never sw color */
1600 false, /* never sw depth */
1601 false, /* never sw stencil */
1602 mesaVis
->accumRedBits
> 0,
1603 false, /* never sw alpha */
1604 false /* never sw aux */ );
1605 driDrawPriv
->driverPrivate
= fb
;
1611 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1613 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1615 _mesa_reference_framebuffer(&fb
, NULL
);
1619 intel_detect_sseu(struct intel_screen
*screen
)
1621 assert(screen
->devinfo
.gen
>= 8);
1624 screen
->subslice_total
= -1;
1625 screen
->eu_total
= -1;
1627 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1628 &screen
->subslice_total
);
1629 if (ret
< 0 && ret
!= -EINVAL
)
1632 ret
= intel_get_param(screen
,
1633 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1634 if (ret
< 0 && ret
!= -EINVAL
)
1637 /* Without this information, we cannot get the right Braswell brandstrings,
1638 * and we have to use conservative numbers for GPGPU on many platforms, but
1639 * otherwise, things will just work.
1641 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1643 "Kernel 4.1 required to properly query GPU properties.\n");
1648 screen
->subslice_total
= -1;
1649 screen
->eu_total
= -1;
1650 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1654 intel_init_bufmgr(struct intel_screen
*screen
)
1656 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1658 if (getenv("INTEL_NO_HW") != NULL
)
1659 screen
->no_hw
= true;
1661 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
);
1662 if (screen
->bufmgr
== NULL
) {
1663 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1664 __func__
, __LINE__
);
1668 if (!intel_get_boolean(screen
, I915_PARAM_HAS_WAIT_TIMEOUT
)) {
1669 fprintf(stderr
, "[%s: %u] Kernel 3.6 required.\n", __func__
, __LINE__
);
1677 intel_detect_swizzling(struct intel_screen
*screen
)
1679 struct brw_bo
*buffer
;
1681 uint32_t aligned_pitch
;
1682 uint32_t tiling
= I915_TILING_X
;
1683 uint32_t swizzle_mode
= 0;
1685 buffer
= brw_bo_alloc_tiled_2d(screen
->bufmgr
, "swizzle test",
1686 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1690 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1691 brw_bo_unreference(buffer
);
1693 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1700 intel_detect_timestamp(struct intel_screen
*screen
)
1702 uint64_t dummy
= 0, last
= 0;
1703 int upper
, lower
, loops
;
1705 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1706 * TIMESTAMP register being shifted and the low 32bits always zero.
1708 * More recent kernels offer an interface to read the full 36bits
1711 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1714 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1715 * upper 32bits for a rapidly changing timestamp.
1717 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1721 for (loops
= 0; loops
< 10; loops
++) {
1722 /* The TIMESTAMP should change every 80ns, so several round trips
1723 * through the kernel should be enough to advance it.
1725 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1728 upper
+= (dummy
>> 32) != (last
>> 32);
1729 if (upper
> 1) /* beware 32bit counter overflow */
1730 return 2; /* upper dword holds the low 32bits of the timestamp */
1732 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1734 return 1; /* timestamp is unshifted */
1739 /* No advancement? No timestamp! */
1744 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1746 * Some combinations of hardware and kernel versions allow this feature,
1747 * while others don't. Instead of trying to enumerate every case, just
1748 * try and write a register and see if works.
1751 intel_detect_pipelined_register(struct intel_screen
*screen
,
1752 int reg
, uint32_t expected_value
, bool reset
)
1757 struct brw_bo
*results
, *bo
;
1759 uint32_t offset
= 0;
1761 bool success
= false;
1763 /* Create a zero'ed temporary buffer for reading our results */
1764 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1765 if (results
== NULL
)
1768 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1772 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
1778 /* Write the register. */
1779 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1781 *batch
++ = expected_value
;
1783 /* Save the register's value back to the buffer. */
1784 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1786 struct drm_i915_gem_relocation_entry reloc
= {
1787 .offset
= (char *) batch
- (char *) map
,
1788 .delta
= offset
* sizeof(uint32_t),
1789 .target_handle
= results
->gem_handle
,
1790 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1791 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1793 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1795 /* And afterwards clear the register */
1797 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1802 *batch
++ = MI_BATCH_BUFFER_END
;
1804 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1806 .handle
= results
->gem_handle
,
1809 .handle
= bo
->gem_handle
,
1810 .relocation_count
= 1,
1811 .relocs_ptr
= (uintptr_t) &reloc
,
1815 struct drm_i915_gem_execbuffer2 execbuf
= {
1816 .buffers_ptr
= (uintptr_t) exec_objects
,
1818 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
1819 .flags
= I915_EXEC_RENDER
,
1822 /* Don't bother with error checking - if the execbuf fails, the
1823 * value won't be written and we'll just report that there's no access.
1825 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1826 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1828 /* Check whether the value got written. */
1829 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
1831 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
1832 brw_bo_unmap(results
);
1836 brw_bo_unreference(bo
);
1838 brw_bo_unreference(results
);
1844 intel_detect_pipelined_so(struct intel_screen
*screen
)
1846 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1848 /* Supposedly, Broadwell just works. */
1849 if (devinfo
->gen
>= 8)
1852 if (devinfo
->gen
<= 6)
1855 /* See the big explanation about command parser versions below */
1856 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1859 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1860 * statistics registers), and we already reset it to zero before using it.
1862 return intel_detect_pipelined_register(screen
,
1863 GEN7_SO_WRITE_OFFSET(0),
1869 * Return array of MSAA modes supported by the hardware. The array is
1870 * zero-terminated and sorted in decreasing order.
1873 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1875 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1876 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1877 static const int gen7_modes
[] = {8, 4, 0, -1};
1878 static const int gen6_modes
[] = {4, 0, -1};
1879 static const int gen4_modes
[] = {0, -1};
1881 if (screen
->devinfo
.gen
>= 9) {
1883 } else if (screen
->devinfo
.gen
>= 8) {
1885 } else if (screen
->devinfo
.gen
>= 7) {
1887 } else if (screen
->devinfo
.gen
== 6) {
1895 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
1897 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
1898 dri_screen
->dri2
.loader
->getCapability
)
1899 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
1901 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
1902 dri_screen
->image
.loader
->getCapability
)
1903 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
1908 static __DRIconfig
**
1909 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1911 static const mesa_format formats
[] = {
1912 MESA_FORMAT_B5G6R5_UNORM
,
1913 MESA_FORMAT_B8G8R8A8_UNORM
,
1914 MESA_FORMAT_B8G8R8X8_UNORM
,
1916 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
1917 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
1918 * server may disagree on which format the GLXFBConfig represents,
1919 * resulting in swapped color channels.
1921 * The problem, as of 2017-05-30:
1922 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
1923 * order and chooses the first __DRIconfig with the expected channel
1924 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
1925 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
1927 * EGL does not suffer from this problem. It correctly compares the
1928 * channel masks when matching EGLConfig to __DRIconfig.
1931 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
1932 MESA_FORMAT_R8G8B8A8_UNORM
,
1934 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
1935 MESA_FORMAT_R8G8B8X8_UNORM
,
1938 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1939 static const GLenum back_buffer_modes
[] = {
1940 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
1943 static const uint8_t singlesample_samples
[1] = {0};
1945 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1946 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1947 uint8_t depth_bits
[4], stencil_bits
[4];
1948 __DRIconfig
**configs
= NULL
;
1950 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
1951 unsigned num_formats
;
1952 if (intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
))
1953 num_formats
= ARRAY_SIZE(formats
);
1957 /* Generate singlesample configs without accumulation buffer. */
1958 for (unsigned i
= 0; i
< num_formats
; i
++) {
1959 __DRIconfig
**new_configs
;
1960 int num_depth_stencil_bits
= 2;
1962 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1963 * buffer that has a different number of bits per pixel than the color
1964 * buffer, gen >= 6 supports this.
1967 stencil_bits
[0] = 0;
1969 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1971 stencil_bits
[1] = 0;
1972 if (devinfo
->gen
>= 6) {
1974 stencil_bits
[2] = 8;
1975 num_depth_stencil_bits
= 3;
1979 stencil_bits
[1] = 8;
1982 new_configs
= driCreateConfigs(formats
[i
],
1985 num_depth_stencil_bits
,
1986 back_buffer_modes
, 2,
1987 singlesample_samples
, 1,
1989 configs
= driConcatConfigs(configs
, new_configs
);
1992 /* Generate the minimum possible set of configs that include an
1993 * accumulation buffer.
1995 for (unsigned i
= 0; i
< num_formats
; i
++) {
1996 __DRIconfig
**new_configs
;
1998 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2000 stencil_bits
[0] = 0;
2003 stencil_bits
[0] = 8;
2006 new_configs
= driCreateConfigs(formats
[i
],
2007 depth_bits
, stencil_bits
, 1,
2008 back_buffer_modes
, 1,
2009 singlesample_samples
, 1,
2011 configs
= driConcatConfigs(configs
, new_configs
);
2014 /* Generate multisample configs.
2016 * This loop breaks early, and hence is a no-op, on gen < 6.
2018 * Multisample configs must follow the singlesample configs in order to
2019 * work around an X server bug present in 1.12. The X server chooses to
2020 * associate the first listed RGBA888-Z24S8 config, regardless of its
2021 * sample count, with the 32-bit depth visual used for compositing.
2023 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2024 * supported. Singlebuffer configs are not supported because no one wants
2027 for (unsigned i
= 0; i
< num_formats
; i
++) {
2028 if (devinfo
->gen
< 6)
2031 __DRIconfig
**new_configs
;
2032 const int num_depth_stencil_bits
= 2;
2033 int num_msaa_modes
= 0;
2034 const uint8_t *multisample_samples
= NULL
;
2037 stencil_bits
[0] = 0;
2039 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2041 stencil_bits
[1] = 0;
2044 stencil_bits
[1] = 8;
2047 if (devinfo
->gen
>= 9) {
2048 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2049 multisample_samples
= multisample_samples_gen9
;
2050 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2051 } else if (devinfo
->gen
== 8) {
2052 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2053 multisample_samples
= multisample_samples_gen8
;
2054 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2055 } else if (devinfo
->gen
== 7) {
2056 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2057 multisample_samples
= multisample_samples_gen7
;
2058 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2059 } else if (devinfo
->gen
== 6) {
2060 static const uint8_t multisample_samples_gen6
[] = {4};
2061 multisample_samples
= multisample_samples_gen6
;
2062 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2065 new_configs
= driCreateConfigs(formats
[i
],
2068 num_depth_stencil_bits
,
2069 back_buffer_modes
, 1,
2070 multisample_samples
,
2073 configs
= driConcatConfigs(configs
, new_configs
);
2076 if (configs
== NULL
) {
2077 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2086 set_max_gl_versions(struct intel_screen
*screen
)
2088 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2089 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2091 switch (screen
->devinfo
.gen
) {
2095 dri_screen
->max_gl_core_version
= 45;
2096 dri_screen
->max_gl_compat_version
= 30;
2097 dri_screen
->max_gl_es1_version
= 11;
2098 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2101 dri_screen
->max_gl_core_version
= 33;
2102 if (can_do_pipelined_register_writes(screen
)) {
2103 dri_screen
->max_gl_core_version
= 42;
2104 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2105 dri_screen
->max_gl_core_version
= 43;
2106 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2107 dri_screen
->max_gl_core_version
= 45;
2109 dri_screen
->max_gl_compat_version
= 30;
2110 dri_screen
->max_gl_es1_version
= 11;
2111 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2114 dri_screen
->max_gl_core_version
= 33;
2115 dri_screen
->max_gl_compat_version
= 30;
2116 dri_screen
->max_gl_es1_version
= 11;
2117 dri_screen
->max_gl_es2_version
= 30;
2121 dri_screen
->max_gl_core_version
= 0;
2122 dri_screen
->max_gl_compat_version
= 21;
2123 dri_screen
->max_gl_es1_version
= 11;
2124 dri_screen
->max_gl_es2_version
= 20;
2127 unreachable("unrecognized intel_screen::gen");
2132 * Return the revision (generally the revid field of the PCI header) of the
2136 intel_device_get_revision(int fd
)
2138 struct drm_i915_getparam gp
;
2142 memset(&gp
, 0, sizeof(gp
));
2143 gp
.param
= I915_PARAM_REVISION
;
2144 gp
.value
= &revision
;
2146 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
2154 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2156 struct brw_context
*brw
= (struct brw_context
*)data
;
2159 va_start(args
, fmt
);
2161 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2162 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2163 MESA_DEBUG_TYPE_OTHER
,
2164 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2169 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2171 struct brw_context
*brw
= (struct brw_context
*)data
;
2174 va_start(args
, fmt
);
2176 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2178 va_copy(args_copy
, args
);
2179 vfprintf(stderr
, fmt
, args_copy
);
2183 if (brw
->perf_debug
) {
2185 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2186 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2187 MESA_DEBUG_TYPE_PERFORMANCE
,
2188 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2194 parse_devid_override(const char *devid_override
)
2196 static const struct {
2216 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
2217 if (!strcmp(name_map
[i
].name
, devid_override
))
2218 return name_map
[i
].pci_id
;
2221 return strtol(devid_override
, NULL
, 0);
2225 * Get the PCI ID for the device. This can be overridden by setting the
2226 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2228 * Returns -1 on ioctl failure.
2231 get_pci_device_id(struct intel_screen
*screen
)
2233 if (geteuid() == getuid()) {
2234 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
2235 if (devid_override
) {
2236 screen
->no_hw
= true;
2237 return parse_devid_override(devid_override
);
2241 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2245 * This is the driver specific part of the createNewScreen entry point.
2246 * Called when using DRI2.
2248 * \return the struct gl_config supported by this driver
2251 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2253 struct intel_screen
*screen
;
2255 if (dri_screen
->image
.loader
) {
2256 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2257 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2259 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2260 "support required\n");
2264 /* Allocate the private area */
2265 screen
= rzalloc(NULL
, struct intel_screen
);
2267 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2270 /* parse information in __driConfigOptions */
2271 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
2273 screen
->driScrnPriv
= dri_screen
;
2274 dri_screen
->driverPrivate
= (void *) screen
;
2276 screen
->deviceID
= get_pci_device_id(screen
);
2278 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2281 if (!intel_init_bufmgr(screen
))
2284 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2286 brw_process_intel_debug_variable();
2288 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2290 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2291 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2294 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2295 /* Theorectically unlimited! At least for individual objects...
2297 * Currently the entire (global) address space for all GTT maps is
2298 * limited to 64bits. That is all objects on the system that are
2299 * setup for GTT mmapping must fit within 64bits. An attempt to use
2300 * one that exceeds the limit with fail in brw_bo_map_gtt().
2302 * Long before we hit that limit, we will be practically limited by
2303 * that any single object must fit in physical memory (RAM). The upper
2304 * limit on the CPU's address space is currently 48bits (Skylake), of
2305 * which only 39bits can be physical memory. (The GPU itself also has
2306 * a 48bit addressable virtual space.) We can fit over 32 million
2307 * objects of the current maximum allocable size before running out
2310 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2312 /* Estimate the size of the mappable aperture into the GTT. There's an
2313 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2314 * It turns out it's basically always 256MB, though some ancient hardware
2317 uint32_t gtt_size
= 256 * 1024 * 1024;
2319 /* We don't want to map two objects such that a memcpy between them would
2320 * just fault one mapping in and then the other over and over forever. So
2321 * we would need to divide the GTT size by 2. Additionally, some GTT is
2322 * taken up by things like the framebuffer and the ringbuffer and such, so
2323 * be more conservative.
2325 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2328 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2330 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2331 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2333 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2334 screen
->hw_has_swizzling
);
2336 /* GENs prior to 8 do not support EU/Subslice info */
2337 if (devinfo
->gen
>= 8) {
2338 intel_detect_sseu(screen
);
2339 } else if (devinfo
->gen
== 7) {
2340 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2343 /* Gen7-7.5 kernel requirements / command parser saga:
2346 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2348 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2349 * all batches secure, allowing them to use any feature with no checking.
2350 * This is effectively equivalent to a command parser version of
2351 * \infinity - everything is possible.
2353 * The command parser does not exist, and querying the version will
2357 * The kernel enables the command parser by default, for systems with
2358 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2359 * hardware checker is still enabled, so Haswell and Baytrail cannot
2362 * Ivybridge goes from "everything is possible" to "only what the
2363 * command parser allows" (if the user boots with i915.cmd_parser=0,
2364 * then everything is possible again). We can only safely use features
2365 * allowed by the supported command parser version.
2367 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2368 * implemented by the kernel, even if it's turned off. So, checking
2369 * for version > 0 does not mean that you can write registers. We have
2370 * to try it and see. The version does, however, indicate the age of
2373 * Instead of matching the hardware checker's behavior of converting
2374 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2375 * -EINVAL, making it dangerous to try and use privileged features.
2377 * Effective command parser versions:
2378 * - Haswell: 0 (reporting 1, writes don't work)
2379 * - Baytrail: 0 (reporting 1, writes don't work)
2380 * - Ivybridge: 1 (enabled) or infinite (disabled)
2383 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2384 * effectively version 1 (enabled) or infinite (disabled).
2386 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2387 * Command parser v2 supports predicate writes.
2389 * - Haswell: 0 (reporting 1, writes don't work)
2390 * - Baytrail: 2 (enabled) or infinite (disabled)
2391 * - Ivybridge: 2 (enabled) or infinite (disabled)
2393 * So version >= 2 is enough to know that Ivybridge and Baytrail
2394 * will work. Haswell still can't do anything.
2396 * - v4.0: Version 3 happened. Largely not relevant.
2398 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2399 * L3 config registers are properly saved and restored as part
2400 * of the hardware context. We can approximately detect this point
2401 * in time by checking if I915_PARAM_REVISION is recognized - it
2402 * landed in a later commit, but in the same release cycle.
2404 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2405 * Command parser finally gains secure batch promotion. On Haswell,
2406 * the hardware checker gets disabled, which finally allows it to do
2407 * privileged commands.
2409 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2410 * - Haswell: 3 (enabled) or 0 (disabled)
2411 * - Baytrail: 3 (enabled) or infinite (disabled)
2412 * - Ivybridge: 3 (enabled) or infinite (disabled)
2414 * Unfortunately, detecting this point in time is tricky, because
2415 * no version bump happened when this important change occurred.
2416 * On Haswell, if we can write any register, then the kernel is at
2417 * least this new, and we can start trusting the version number.
2419 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2420 * Command parser reaches version 4, allowing access to Haswell
2421 * atomic scratch and chicken3 registers. If version >= 4, we know
2422 * the kernel is new enough to support privileged features on all
2423 * hardware. However, the user might have disabled it...and the
2424 * kernel will still report version 4. So we still have to guess
2427 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2428 * Command parser v5 whitelists indirect compute shader dispatch
2429 * registers, needed for OpenGL 4.3 and later.
2432 * Command parser v7 lets us use MI_MATH on Haswell.
2434 * Additionally, the kernel begins reporting version 0 when
2435 * the command parser is disabled, allowing us to skip the
2436 * guess-and-check step on Haswell. Unfortunately, this also
2437 * means that we can no longer use it as an indicator of the
2438 * age of the kernel.
2440 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2441 &screen
->cmd_parser_version
) < 0) {
2442 /* Command parser does not exist - getparam is unrecognized */
2443 screen
->cmd_parser_version
= 0;
2446 /* Kernel 4.13 retuired for exec object capture */
2447 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2448 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2451 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2452 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2455 if (!intel_detect_pipelined_so(screen
)) {
2456 /* We can't do anything, so the effective version is 0. */
2457 screen
->cmd_parser_version
= 0;
2459 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2462 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2463 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2465 /* Haswell requires command parser version 4 in order to have L3
2466 * atomic scratch1 and chicken3 bits
2468 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2469 screen
->kernel_features
|=
2470 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2473 /* Haswell requires command parser version 6 in order to write to the
2474 * MI_MATH GPR registers, and version 7 in order to use
2475 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2477 if (devinfo
->gen
>= 8 ||
2478 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2479 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2482 /* Gen7 needs at least command parser version 5 to support compute */
2483 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2484 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2486 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2488 screen
->winsys_msaa_samples_override
=
2489 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2490 printf("Forcing winsys sample count to %d\n",
2491 screen
->winsys_msaa_samples_override
);
2493 screen
->winsys_msaa_samples_override
= -1;
2496 set_max_gl_versions(screen
);
2498 /* Notification of GPU resets requires hardware contexts and a kernel new
2499 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2500 * supported, calling it with a context of 0 will either generate EPERM or
2501 * no error. If the ioctl is not supported, it always generate EINVAL.
2502 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2503 * extension to the loader.
2505 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2507 if (devinfo
->gen
>= 6) {
2508 struct drm_i915_reset_stats stats
;
2509 memset(&stats
, 0, sizeof(stats
));
2511 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2513 screen
->has_context_reset_notification
=
2514 (ret
!= -1 || errno
!= EINVAL
);
2517 dri_screen
->extensions
= !screen
->has_context_reset_notification
2518 ? screenExtensions
: intelRobustScreenExtensions
;
2520 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2521 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2522 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2523 screen
->compiler
->constant_buffer_0_is_relative
= true;
2524 screen
->compiler
->supports_pull_constants
= true;
2526 screen
->has_exec_fence
=
2527 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2529 intel_screen_init_surface_formats(screen
);
2531 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2532 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2534 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2535 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2536 fprintf(stderr
, " - User priority sorting enabled\n");
2537 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2538 fprintf(stderr
, " - Preemption enabled\n");
2542 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2545 struct intel_buffer
{
2550 static __DRIbuffer
*
2551 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2552 unsigned attachment
, unsigned format
,
2553 int width
, int height
)
2555 struct intel_buffer
*intelBuffer
;
2556 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2558 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2559 attachment
== __DRI_BUFFER_BACK_LEFT
);
2561 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2562 if (intelBuffer
== NULL
)
2565 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2566 * supports Y tiled and compressed buffers, but there is no way to plumb that
2567 * through to here. */
2569 int cpp
= format
/ 8;
2570 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2571 "intelAllocateBuffer",
2575 I915_TILING_X
, &pitch
,
2578 if (intelBuffer
->bo
== NULL
) {
2583 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2585 intelBuffer
->base
.attachment
= attachment
;
2586 intelBuffer
->base
.cpp
= cpp
;
2587 intelBuffer
->base
.pitch
= pitch
;
2589 return &intelBuffer
->base
;
2593 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2595 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2597 brw_bo_unreference(intelBuffer
->bo
);
2601 static const struct __DriverAPIRec brw_driver_api
= {
2602 .InitScreen
= intelInitScreen2
,
2603 .DestroyScreen
= intelDestroyScreen
,
2604 .CreateContext
= brwCreateContext
,
2605 .DestroyContext
= intelDestroyContext
,
2606 .CreateBuffer
= intelCreateBuffer
,
2607 .DestroyBuffer
= intelDestroyBuffer
,
2608 .MakeCurrent
= intelMakeCurrent
,
2609 .UnbindContext
= intelUnbindContext
,
2610 .AllocateBuffer
= intelAllocateBuffer
,
2611 .ReleaseBuffer
= intelReleaseBuffer
2614 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2615 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2616 .vtable
= &brw_driver_api
,
2619 static const __DRIextension
*brw_driver_extensions
[] = {
2620 &driCoreExtension
.base
,
2621 &driImageDriverExtension
.base
,
2622 &driDRI2Extension
.base
,
2624 &brw_config_options
.base
,
2628 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2630 globalDriverAPI
= &brw_driver_api
;
2632 return brw_driver_extensions
;