1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
31 #include "main/glheader.h"
32 #include "main/context.h"
33 #include "main/framebuffer.h"
34 #include "main/renderbuffer.h"
35 #include "main/texobj.h"
36 #include "main/hash.h"
37 #include "main/fbobject.h"
38 #include "main/version.h"
39 #include "swrast/s_renderbuffer.h"
40 #include "util/ralloc.h"
45 static const __DRIconfigOptionsExtension brw_config_options
= {
46 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
49 DRI_CONF_SECTION_PERFORMANCE
50 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
51 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
52 * DRI_CONF_BO_REUSE_ALL
54 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
55 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
56 DRI_CONF_ENUM(0, "Disable buffer object reuse")
57 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
61 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
62 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
65 DRI_CONF_OPT_BEGIN_B(disable_derivative_optimization
, "false")
66 DRI_CONF_DESC(en
, "Derivatives with finer granularity by default")
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_FORCE_S3TC_ENABLE("false")
73 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
74 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
75 "given integer. If negative, then do not clamp.")
79 DRI_CONF_SECTION_DEBUG
80 DRI_CONF_NO_RAST("false")
81 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
82 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
83 DRI_CONF_DISABLE_THROTTLING("false")
84 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
85 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
86 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
87 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
89 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
90 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
96 #include "intel_batchbuffer.h"
97 #include "intel_buffers.h"
98 #include "intel_bufmgr.h"
99 #include "intel_chipset.h"
100 #include "intel_fbo.h"
101 #include "intel_mipmap_tree.h"
102 #include "intel_screen.h"
103 #include "intel_tex.h"
104 #include "intel_image.h"
106 #include "brw_context.h"
108 #include "i915_drm.h"
111 * For debugging purposes, this returns a time in seconds.
118 clock_gettime(CLOCK_MONOTONIC
, &tp
);
120 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
124 aub_dump_bmp(struct gl_context
*ctx
)
126 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
128 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
129 struct intel_renderbuffer
*irb
=
130 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
132 if (irb
&& irb
->mt
) {
133 enum aub_dump_bmp_format format
;
135 switch (irb
->Base
.Base
.Format
) {
136 case MESA_FORMAT_B8G8R8A8_UNORM
:
137 case MESA_FORMAT_B8G8R8X8_UNORM
:
138 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
144 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
147 irb
->Base
.Base
.Width
,
148 irb
->Base
.Base
.Height
,
156 static const __DRItexBufferExtension intelTexBufferExtension
= {
157 .base
= { __DRI_TEX_BUFFER
, 3 },
159 .setTexBuffer
= intelSetTexBuffer
,
160 .setTexBuffer2
= intelSetTexBuffer2
,
161 .releaseTexBuffer
= NULL
,
165 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
166 __DRIdrawable
*dPriv
,
168 enum __DRI2throttleReason reason
)
170 struct brw_context
*brw
= cPriv
->driverPrivate
;
175 struct gl_context
*ctx
= &brw
->ctx
;
177 FLUSH_VERTICES(ctx
, 0);
179 if (flags
& __DRI2_FLUSH_DRAWABLE
)
180 intel_resolve_for_dri2_flush(brw
, dPriv
);
182 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
||
183 reason
== __DRI2_THROTTLE_FLUSHFRONT
) {
184 brw
->need_throttle
= true;
187 intel_batchbuffer_flush(brw
);
189 if (INTEL_DEBUG
& DEBUG_AUB
) {
195 * Provides compatibility with loaders that only support the older (version
196 * 1-3) flush interface.
198 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
201 intel_dri2_flush(__DRIdrawable
*drawable
)
203 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
204 __DRI2_FLUSH_DRAWABLE
,
205 __DRI2_THROTTLE_SWAPBUFFER
);
208 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
209 .base
= { __DRI2_FLUSH
, 4 },
211 .flush
= intel_dri2_flush
,
212 .invalidate
= dri2InvalidateDrawable
,
213 .flush_with_flags
= intel_dri2_flush_with_flags
,
216 static struct intel_image_format intel_image_formats
[] = {
217 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
218 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
220 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
221 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
223 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
224 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
226 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
227 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
229 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
230 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
231 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
232 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
234 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
236 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
237 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
239 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
241 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
242 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
244 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
245 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
246 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
247 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
249 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
250 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
254 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
255 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
258 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
259 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
262 /* For YUYV buffers, we set up two overlapping DRI images and treat
263 * them as planar buffers in the compositors. Plane 0 is GR88 and
264 * samples YU or YV pairs and places Y into the R component, while
265 * plane 1 is ARGB and samples YUYV clusters and places pairs and
266 * places U into the G component and V into A. This lets the
267 * texture sampler interpolate the Y components correctly when
268 * sampling from plane 0, and interpolate U and V correctly when
269 * sampling from plane 1. */
270 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
271 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
272 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
276 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
278 uint32_t tiling
, swizzle
;
279 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
281 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
282 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
283 func
, image
->offset
);
287 static struct intel_image_format
*
288 intel_image_format_lookup(int fourcc
)
290 struct intel_image_format
*f
= NULL
;
292 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
293 if (intel_image_formats
[i
].fourcc
== fourcc
) {
294 f
= &intel_image_formats
[i
];
303 intel_allocate_image(int dri_format
, void *loaderPrivate
)
307 image
= calloc(1, sizeof *image
);
311 image
->dri_format
= dri_format
;
314 image
->format
= driImageFormatToGLFormat(dri_format
);
315 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
316 image
->format
== MESA_FORMAT_NONE
) {
321 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
322 image
->data
= loaderPrivate
;
328 * Sets up a DRIImage structure to point to a slice out of a miptree.
331 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
332 struct intel_mipmap_tree
*mt
, GLuint level
,
335 intel_miptree_make_shareable(brw
, mt
);
337 intel_miptree_check_level_layer(mt
, level
, zoffset
);
339 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
340 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
341 image
->pitch
= mt
->pitch
;
343 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
347 drm_intel_bo_unreference(image
->bo
);
349 drm_intel_bo_reference(mt
->bo
);
353 intel_create_image_from_name(__DRIscreen
*screen
,
354 int width
, int height
, int format
,
355 int name
, int pitch
, void *loaderPrivate
)
357 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
361 image
= intel_allocate_image(format
, loaderPrivate
);
365 if (image
->format
== MESA_FORMAT_NONE
)
368 cpp
= _mesa_get_format_bytes(image
->format
);
370 image
->width
= width
;
371 image
->height
= height
;
372 image
->pitch
= pitch
* cpp
;
373 image
->bo
= drm_intel_bo_gem_create_from_name(intelScreen
->bufmgr
, "image",
384 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
385 int renderbuffer
, void *loaderPrivate
)
388 struct brw_context
*brw
= context
->driverPrivate
;
389 struct gl_context
*ctx
= &brw
->ctx
;
390 struct gl_renderbuffer
*rb
;
391 struct intel_renderbuffer
*irb
;
393 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
395 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
399 irb
= intel_renderbuffer(rb
);
400 intel_miptree_make_shareable(brw
, irb
->mt
);
401 image
= calloc(1, sizeof *image
);
405 image
->internal_format
= rb
->InternalFormat
;
406 image
->format
= rb
->Format
;
408 image
->data
= loaderPrivate
;
409 drm_intel_bo_unreference(image
->bo
);
410 image
->bo
= irb
->mt
->bo
;
411 drm_intel_bo_reference(irb
->mt
->bo
);
412 image
->width
= rb
->Width
;
413 image
->height
= rb
->Height
;
414 image
->pitch
= irb
->mt
->pitch
;
415 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
416 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
418 rb
->NeedsFinishRenderTexture
= true;
423 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
424 unsigned texture
, int zoffset
,
430 struct brw_context
*brw
= context
->driverPrivate
;
431 struct gl_texture_object
*obj
;
432 struct intel_texture_object
*iobj
;
435 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
436 if (!obj
|| obj
->Target
!= target
) {
437 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
441 if (target
== GL_TEXTURE_CUBE_MAP
)
444 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
445 iobj
= intel_texture_object(obj
);
446 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
447 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
451 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
452 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
456 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
457 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
460 image
= calloc(1, sizeof *image
);
462 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
466 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
467 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
468 image
->data
= loaderPrivate
;
469 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
470 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
471 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
472 if (image
->dri_format
== MESA_FORMAT_NONE
) {
473 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
478 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
483 intel_destroy_image(__DRIimage
*image
)
485 drm_intel_bo_unreference(image
->bo
);
490 intel_create_image(__DRIscreen
*screen
,
491 int width
, int height
, int format
,
496 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
501 tiling
= I915_TILING_X
;
502 if (use
& __DRI_IMAGE_USE_CURSOR
) {
503 if (width
!= 64 || height
!= 64)
505 tiling
= I915_TILING_NONE
;
508 if (use
& __DRI_IMAGE_USE_LINEAR
)
509 tiling
= I915_TILING_NONE
;
511 image
= intel_allocate_image(format
, loaderPrivate
);
516 cpp
= _mesa_get_format_bytes(image
->format
);
517 image
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
, "image",
518 width
, height
, cpp
, &tiling
,
520 if (image
->bo
== NULL
) {
524 image
->width
= width
;
525 image
->height
= height
;
526 image
->pitch
= pitch
;
532 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
535 case __DRI_IMAGE_ATTRIB_STRIDE
:
536 *value
= image
->pitch
;
538 case __DRI_IMAGE_ATTRIB_HANDLE
:
539 *value
= image
->bo
->handle
;
541 case __DRI_IMAGE_ATTRIB_NAME
:
542 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
543 case __DRI_IMAGE_ATTRIB_FORMAT
:
544 *value
= image
->dri_format
;
546 case __DRI_IMAGE_ATTRIB_WIDTH
:
547 *value
= image
->width
;
549 case __DRI_IMAGE_ATTRIB_HEIGHT
:
550 *value
= image
->height
;
552 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
553 if (image
->planar_format
== NULL
)
555 *value
= image
->planar_format
->components
;
557 case __DRI_IMAGE_ATTRIB_FD
:
558 if (drm_intel_bo_gem_export_to_prime(image
->bo
, value
) == 0)
567 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
571 image
= calloc(1, sizeof *image
);
575 drm_intel_bo_reference(orig_image
->bo
);
576 image
->bo
= orig_image
->bo
;
577 image
->internal_format
= orig_image
->internal_format
;
578 image
->planar_format
= orig_image
->planar_format
;
579 image
->dri_format
= orig_image
->dri_format
;
580 image
->format
= orig_image
->format
;
581 image
->offset
= orig_image
->offset
;
582 image
->width
= orig_image
->width
;
583 image
->height
= orig_image
->height
;
584 image
->pitch
= orig_image
->pitch
;
585 image
->tile_x
= orig_image
->tile_x
;
586 image
->tile_y
= orig_image
->tile_y
;
587 image
->has_depthstencil
= orig_image
->has_depthstencil
;
588 image
->data
= loaderPrivate
;
590 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
591 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
597 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
599 if (use
& __DRI_IMAGE_USE_CURSOR
) {
600 if (image
->width
!= 64 || image
->height
!= 64)
608 intel_create_image_from_names(__DRIscreen
*screen
,
609 int width
, int height
, int fourcc
,
610 int *names
, int num_names
,
611 int *strides
, int *offsets
,
614 struct intel_image_format
*f
= NULL
;
618 if (screen
== NULL
|| names
== NULL
|| num_names
!= 1)
621 f
= intel_image_format_lookup(fourcc
);
625 image
= intel_create_image_from_name(screen
, width
, height
,
626 __DRI_IMAGE_FORMAT_NONE
,
627 names
[0], strides
[0],
633 image
->planar_format
= f
;
634 for (i
= 0; i
< f
->nplanes
; i
++) {
635 index
= f
->planes
[i
].buffer_index
;
636 image
->offsets
[index
] = offsets
[index
];
637 image
->strides
[index
] = strides
[index
];
644 intel_create_image_from_fds(__DRIscreen
*screen
,
645 int width
, int height
, int fourcc
,
646 int *fds
, int num_fds
, int *strides
, int *offsets
,
649 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
650 struct intel_image_format
*f
;
654 if (fds
== NULL
|| num_fds
!= 1)
657 f
= intel_image_format_lookup(fourcc
);
662 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
664 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
669 image
->bo
= drm_intel_bo_gem_create_from_prime(intelScreen
->bufmgr
,
671 height
* strides
[0]);
672 if (image
->bo
== NULL
) {
676 image
->width
= width
;
677 image
->height
= height
;
678 image
->pitch
= strides
[0];
680 image
->planar_format
= f
;
681 for (i
= 0; i
< f
->nplanes
; i
++) {
682 index
= f
->planes
[i
].buffer_index
;
683 image
->offsets
[index
] = offsets
[index
];
684 image
->strides
[index
] = strides
[index
];
687 if (f
->nplanes
== 1) {
688 image
->offset
= image
->offsets
[0];
689 intel_image_warn_if_unaligned(image
, __FUNCTION__
);
696 intel_create_image_from_dma_bufs(__DRIscreen
*screen
,
697 int width
, int height
, int fourcc
,
698 int *fds
, int num_fds
,
699 int *strides
, int *offsets
,
700 enum __DRIYUVColorSpace yuv_color_space
,
701 enum __DRISampleRange sample_range
,
702 enum __DRIChromaSiting horizontal_siting
,
703 enum __DRIChromaSiting vertical_siting
,
708 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
710 /* For now only packed formats that have native sampling are supported. */
711 if (!f
|| f
->nplanes
!= 1) {
712 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
716 image
= intel_create_image_from_fds(screen
, width
, height
, fourcc
, fds
,
717 num_fds
, strides
, offsets
,
721 * Invalid parameters and any inconsistencies between are assumed to be
722 * checked by the caller. Therefore besides unsupported formats one can fail
723 * only in allocation.
726 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
730 image
->dma_buf_imported
= true;
731 image
->yuv_color_space
= yuv_color_space
;
732 image
->sample_range
= sample_range
;
733 image
->horizontal_siting
= horizontal_siting
;
734 image
->vertical_siting
= vertical_siting
;
736 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
741 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
743 int width
, height
, offset
, stride
, dri_format
, index
;
744 struct intel_image_format
*f
;
747 if (parent
== NULL
|| parent
->planar_format
== NULL
)
750 f
= parent
->planar_format
;
752 if (plane
>= f
->nplanes
)
755 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
756 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
757 dri_format
= f
->planes
[plane
].dri_format
;
758 index
= f
->planes
[plane
].buffer_index
;
759 offset
= parent
->offsets
[index
];
760 stride
= parent
->strides
[index
];
762 image
= intel_allocate_image(dri_format
, loaderPrivate
);
766 if (offset
+ height
* stride
> parent
->bo
->size
) {
767 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
772 image
->bo
= parent
->bo
;
773 drm_intel_bo_reference(parent
->bo
);
775 image
->width
= width
;
776 image
->height
= height
;
777 image
->pitch
= stride
;
778 image
->offset
= offset
;
780 intel_image_warn_if_unaligned(image
, __FUNCTION__
);
785 static const __DRIimageExtension intelImageExtension
= {
786 .base
= { __DRI_IMAGE
, 8 },
788 .createImageFromName
= intel_create_image_from_name
,
789 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
790 .destroyImage
= intel_destroy_image
,
791 .createImage
= intel_create_image
,
792 .queryImage
= intel_query_image
,
793 .dupImage
= intel_dup_image
,
794 .validateUsage
= intel_validate_usage
,
795 .createImageFromNames
= intel_create_image_from_names
,
796 .fromPlanar
= intel_from_planar
,
797 .createImageFromTexture
= intel_create_image_from_texture
,
798 .createImageFromFds
= intel_create_image_from_fds
,
799 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
803 brw_query_renderer_integer(__DRIscreen
*psp
, int param
, unsigned int *value
)
805 const struct intel_screen
*const intelScreen
=
806 (struct intel_screen
*) psp
->driverPrivate
;
809 case __DRI2_RENDERER_VENDOR_ID
:
812 case __DRI2_RENDERER_DEVICE_ID
:
813 value
[0] = intelScreen
->deviceID
;
815 case __DRI2_RENDERER_ACCELERATED
:
818 case __DRI2_RENDERER_VIDEO_MEMORY
: {
819 /* Once a batch uses more than 75% of the maximum mappable size, we
820 * assume that there's some fragmentation, and we start doing extra
821 * flushing, etc. That's the big cliff apps will care about.
824 size_t mappable_size
;
826 drm_intel_get_aperture_sizes(psp
->fd
, &mappable_size
, &aper_size
);
828 const unsigned gpu_mappable_megabytes
=
829 (aper_size
/ (1024 * 1024)) * 3 / 4;
831 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
832 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
834 if (system_memory_pages
<= 0 || system_page_size
<= 0)
837 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
838 * (uint64_t) system_page_size
;
840 const unsigned system_memory_megabytes
=
841 (unsigned) (system_memory_bytes
/ (1024 * 1024));
843 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
846 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
850 return driQueryRendererIntegerCommon(psp
, param
, value
);
857 brw_query_renderer_string(__DRIscreen
*psp
, int param
, const char **value
)
859 const struct intel_screen
*intelScreen
=
860 (struct intel_screen
*) psp
->driverPrivate
;
863 case __DRI2_RENDERER_VENDOR_ID
:
864 value
[0] = brw_vendor_string
;
866 case __DRI2_RENDERER_DEVICE_ID
:
867 value
[0] = brw_get_renderer_string(intelScreen
->deviceID
);
876 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
877 .base
= { __DRI2_RENDERER_QUERY
, 1 },
879 .queryInteger
= brw_query_renderer_integer
,
880 .queryString
= brw_query_renderer_string
883 static const __DRIrobustnessExtension dri2Robustness
= {
884 .base
= { __DRI2_ROBUSTNESS
, 1 }
887 static const __DRIextension
*intelScreenExtensions
[] = {
888 &intelTexBufferExtension
.base
,
889 &intelFlushExtension
.base
,
890 &intelImageExtension
.base
,
891 &intelRendererQueryExtension
.base
,
892 &dri2ConfigQueryExtension
.base
,
896 static const __DRIextension
*intelRobustScreenExtensions
[] = {
897 &intelTexBufferExtension
.base
,
898 &intelFlushExtension
.base
,
899 &intelImageExtension
.base
,
900 &intelRendererQueryExtension
.base
,
901 &dri2ConfigQueryExtension
.base
,
902 &dri2Robustness
.base
,
907 intel_get_param(__DRIscreen
*psp
, int param
, int *value
)
910 struct drm_i915_getparam gp
;
912 memset(&gp
, 0, sizeof(gp
));
916 ret
= drmCommandWriteRead(psp
->fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
919 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
927 intel_get_boolean(__DRIscreen
*psp
, int param
)
930 return intel_get_param(psp
, param
, &value
) && value
;
934 intelDestroyScreen(__DRIscreen
* sPriv
)
936 struct intel_screen
*intelScreen
= sPriv
->driverPrivate
;
938 dri_bufmgr_destroy(intelScreen
->bufmgr
);
939 driDestroyOptionInfo(&intelScreen
->optionCache
);
941 ralloc_free(intelScreen
);
942 sPriv
->driverPrivate
= NULL
;
947 * This is called when we need to set up GL rendering to a new X window.
950 intelCreateBuffer(__DRIscreen
* driScrnPriv
,
951 __DRIdrawable
* driDrawPriv
,
952 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
954 struct intel_renderbuffer
*rb
;
955 struct intel_screen
*screen
= (struct intel_screen
*) driScrnPriv
->driverPrivate
;
956 mesa_format rgbFormat
;
957 unsigned num_samples
= intel_quantize_num_samples(screen
, mesaVis
->samples
);
958 struct gl_framebuffer
*fb
;
963 fb
= CALLOC_STRUCT(gl_framebuffer
);
967 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
969 if (screen
->winsys_msaa_samples_override
!= -1) {
970 num_samples
= screen
->winsys_msaa_samples_override
;
971 fb
->Visual
.samples
= num_samples
;
974 if (mesaVis
->redBits
== 5)
975 rgbFormat
= MESA_FORMAT_B5G6R5_UNORM
;
976 else if (mesaVis
->sRGBCapable
)
977 rgbFormat
= MESA_FORMAT_B8G8R8A8_SRGB
;
978 else if (mesaVis
->alphaBits
== 0)
979 rgbFormat
= MESA_FORMAT_B8G8R8X8_UNORM
;
981 rgbFormat
= MESA_FORMAT_B8G8R8A8_SRGB
;
982 fb
->Visual
.sRGBCapable
= true;
985 /* setup the hardware-based renderbuffers */
986 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
987 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
989 if (mesaVis
->doubleBufferMode
) {
990 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
991 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
995 * Assert here that the gl_config has an expected depth/stencil bit
996 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
997 * which constructs the advertised configs.)
999 if (mesaVis
->depthBits
== 24) {
1000 assert(mesaVis
->stencilBits
== 8);
1002 if (screen
->devinfo
->has_hiz_and_separate_stencil
) {
1003 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1005 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1006 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1008 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1011 * Use combined depth/stencil. Note that the renderbuffer is
1012 * attached to two attachment points.
1014 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1016 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1017 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1020 else if (mesaVis
->depthBits
== 16) {
1021 assert(mesaVis
->stencilBits
== 0);
1022 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1024 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1027 assert(mesaVis
->depthBits
== 0);
1028 assert(mesaVis
->stencilBits
== 0);
1031 /* now add any/all software-based renderbuffers we may need */
1032 _swrast_add_soft_renderbuffers(fb
,
1033 false, /* never sw color */
1034 false, /* never sw depth */
1035 false, /* never sw stencil */
1036 mesaVis
->accumRedBits
> 0,
1037 false, /* never sw alpha */
1038 false /* never sw aux */ );
1039 driDrawPriv
->driverPrivate
= fb
;
1045 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1047 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1049 _mesa_reference_framebuffer(&fb
, NULL
);
1053 intel_init_bufmgr(struct intel_screen
*intelScreen
)
1055 __DRIscreen
*spriv
= intelScreen
->driScrnPriv
;
1057 intelScreen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1059 intelScreen
->bufmgr
= intel_bufmgr_gem_init(spriv
->fd
, BATCH_SZ
);
1060 if (intelScreen
->bufmgr
== NULL
) {
1061 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1062 __func__
, __LINE__
);
1066 drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen
->bufmgr
);
1068 if (!intel_get_boolean(spriv
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1069 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1077 intel_detect_swizzling(struct intel_screen
*screen
)
1079 drm_intel_bo
*buffer
;
1080 unsigned long flags
= 0;
1081 unsigned long aligned_pitch
;
1082 uint32_t tiling
= I915_TILING_X
;
1083 uint32_t swizzle_mode
= 0;
1085 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1087 &tiling
, &aligned_pitch
, flags
);
1091 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1092 drm_intel_bo_unreference(buffer
);
1094 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1101 * Return array of MSAA modes supported by the hardware. The array is
1102 * zero-terminated and sorted in decreasing order.
1105 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1107 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1108 static const int gen7_modes
[] = {8, 4, 0, -1};
1109 static const int gen6_modes
[] = {4, 0, -1};
1110 static const int gen4_modes
[] = {0, -1};
1112 if (screen
->devinfo
->gen
>= 8) {
1114 } else if (screen
->devinfo
->gen
>= 7) {
1116 } else if (screen
->devinfo
->gen
== 6) {
1123 static __DRIconfig
**
1124 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1126 static const mesa_format formats
[] = {
1127 MESA_FORMAT_B5G6R5_UNORM
,
1128 MESA_FORMAT_B8G8R8A8_UNORM
1131 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1132 static const GLenum back_buffer_modes
[] = {
1133 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1136 static const uint8_t singlesample_samples
[1] = {0};
1137 static const uint8_t multisample_samples
[2] = {4, 8};
1139 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1140 const struct brw_device_info
*devinfo
= screen
->devinfo
;
1141 uint8_t depth_bits
[4], stencil_bits
[4];
1142 __DRIconfig
**configs
= NULL
;
1144 /* Generate singlesample configs without accumulation buffer. */
1145 for (int i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1146 __DRIconfig
**new_configs
;
1147 int num_depth_stencil_bits
= 2;
1149 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1150 * buffer that has a different number of bits per pixel than the color
1151 * buffer, gen >= 6 supports this.
1154 stencil_bits
[0] = 0;
1156 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1158 stencil_bits
[1] = 0;
1159 if (devinfo
->gen
>= 6) {
1161 stencil_bits
[2] = 8;
1162 num_depth_stencil_bits
= 3;
1166 stencil_bits
[1] = 8;
1169 new_configs
= driCreateConfigs(formats
[i
],
1172 num_depth_stencil_bits
,
1173 back_buffer_modes
, 2,
1174 singlesample_samples
, 1,
1176 configs
= driConcatConfigs(configs
, new_configs
);
1179 /* Generate the minimum possible set of configs that include an
1180 * accumulation buffer.
1182 for (int i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1183 __DRIconfig
**new_configs
;
1185 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1187 stencil_bits
[0] = 0;
1190 stencil_bits
[0] = 8;
1193 new_configs
= driCreateConfigs(formats
[i
],
1194 depth_bits
, stencil_bits
, 1,
1195 back_buffer_modes
, 1,
1196 singlesample_samples
, 1,
1198 configs
= driConcatConfigs(configs
, new_configs
);
1201 /* Generate multisample configs.
1203 * This loop breaks early, and hence is a no-op, on gen < 6.
1205 * Multisample configs must follow the singlesample configs in order to
1206 * work around an X server bug present in 1.12. The X server chooses to
1207 * associate the first listed RGBA888-Z24S8 config, regardless of its
1208 * sample count, with the 32-bit depth visual used for compositing.
1210 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1211 * supported. Singlebuffer configs are not supported because no one wants
1214 for (int i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1215 if (devinfo
->gen
< 6)
1218 __DRIconfig
**new_configs
;
1219 const int num_depth_stencil_bits
= 2;
1220 int num_msaa_modes
= 0;
1223 stencil_bits
[0] = 0;
1225 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1227 stencil_bits
[1] = 0;
1230 stencil_bits
[1] = 8;
1233 if (devinfo
->gen
>= 7)
1235 else if (devinfo
->gen
== 6)
1238 new_configs
= driCreateConfigs(formats
[i
],
1241 num_depth_stencil_bits
,
1242 back_buffer_modes
, 1,
1243 multisample_samples
,
1246 configs
= driConcatConfigs(configs
, new_configs
);
1249 if (configs
== NULL
) {
1250 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1259 set_max_gl_versions(struct intel_screen
*screen
)
1261 __DRIscreen
*psp
= screen
->driScrnPriv
;
1263 switch (screen
->devinfo
->gen
) {
1266 psp
->max_gl_core_version
= 33;
1267 psp
->max_gl_compat_version
= 30;
1268 psp
->max_gl_es1_version
= 11;
1269 psp
->max_gl_es2_version
= 30;
1272 psp
->max_gl_core_version
= 31;
1273 psp
->max_gl_compat_version
= 30;
1274 psp
->max_gl_es1_version
= 11;
1275 psp
->max_gl_es2_version
= 30;
1279 psp
->max_gl_core_version
= 0;
1280 psp
->max_gl_compat_version
= 21;
1281 psp
->max_gl_es1_version
= 11;
1282 psp
->max_gl_es2_version
= 20;
1285 unreachable("unrecognized intel_screen::gen");
1290 * This is the driver specific part of the createNewScreen entry point.
1291 * Called when using DRI2.
1293 * \return the struct gl_config supported by this driver
1296 __DRIconfig
**intelInitScreen2(__DRIscreen
*psp
)
1298 struct intel_screen
*intelScreen
;
1300 if (psp
->image
.loader
) {
1301 } else if (psp
->dri2
.loader
->base
.version
<= 2 ||
1302 psp
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1304 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1305 "support required\n");
1309 /* Allocate the private area */
1310 intelScreen
= rzalloc(NULL
, struct intel_screen
);
1312 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1315 /* parse information in __driConfigOptions */
1316 driParseOptionInfo(&intelScreen
->optionCache
, brw_config_options
.xml
);
1318 intelScreen
->driScrnPriv
= psp
;
1319 psp
->driverPrivate
= (void *) intelScreen
;
1321 if (!intel_init_bufmgr(intelScreen
))
1324 intelScreen
->deviceID
= drm_intel_bufmgr_gem_get_devid(intelScreen
->bufmgr
);
1325 intelScreen
->devinfo
= brw_get_device_info(intelScreen
->deviceID
);
1326 if (!intelScreen
->devinfo
)
1329 intelScreen
->hw_must_use_separate_stencil
= intelScreen
->devinfo
->gen
>= 7;
1331 intelScreen
->hw_has_swizzling
= intel_detect_swizzling(intelScreen
);
1333 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1335 intelScreen
->winsys_msaa_samples_override
=
1336 intel_quantize_num_samples(intelScreen
, atoi(force_msaa
));
1337 printf("Forcing winsys sample count to %d\n",
1338 intelScreen
->winsys_msaa_samples_override
);
1340 intelScreen
->winsys_msaa_samples_override
= -1;
1343 set_max_gl_versions(intelScreen
);
1345 /* Notification of GPU resets requires hardware contexts and a kernel new
1346 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1347 * supported, calling it with a context of 0 will either generate EPERM or
1348 * no error. If the ioctl is not supported, it always generate EINVAL.
1349 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1350 * extension to the loader.
1352 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1354 if (intelScreen
->devinfo
->gen
>= 6) {
1355 struct drm_i915_reset_stats stats
;
1356 memset(&stats
, 0, sizeof(stats
));
1358 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1360 intelScreen
->has_context_reset_notification
=
1361 (ret
!= -1 || errno
!= EINVAL
);
1364 psp
->extensions
= !intelScreen
->has_context_reset_notification
1365 ? intelScreenExtensions
: intelRobustScreenExtensions
;
1367 brw_fs_alloc_reg_sets(intelScreen
);
1368 brw_vec4_alloc_reg_set(intelScreen
);
1370 return (const __DRIconfig
**) intel_screen_make_configs(psp
);
1373 struct intel_buffer
{
1378 static __DRIbuffer
*
1379 intelAllocateBuffer(__DRIscreen
*screen
,
1380 unsigned attachment
, unsigned format
,
1381 int width
, int height
)
1383 struct intel_buffer
*intelBuffer
;
1384 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
1386 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1387 attachment
== __DRI_BUFFER_BACK_LEFT
);
1389 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1390 if (intelBuffer
== NULL
)
1393 /* The front and back buffers are color buffers, which are X tiled. */
1394 uint32_t tiling
= I915_TILING_X
;
1395 unsigned long pitch
;
1396 int cpp
= format
/ 8;
1397 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
,
1398 "intelAllocateBuffer",
1403 BO_ALLOC_FOR_RENDER
);
1405 if (intelBuffer
->bo
== NULL
) {
1410 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1412 intelBuffer
->base
.attachment
= attachment
;
1413 intelBuffer
->base
.cpp
= cpp
;
1414 intelBuffer
->base
.pitch
= pitch
;
1416 return &intelBuffer
->base
;
1420 intelReleaseBuffer(__DRIscreen
*screen
, __DRIbuffer
*buffer
)
1422 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1424 drm_intel_bo_unreference(intelBuffer
->bo
);
1428 static const struct __DriverAPIRec brw_driver_api
= {
1429 .InitScreen
= intelInitScreen2
,
1430 .DestroyScreen
= intelDestroyScreen
,
1431 .CreateContext
= brwCreateContext
,
1432 .DestroyContext
= intelDestroyContext
,
1433 .CreateBuffer
= intelCreateBuffer
,
1434 .DestroyBuffer
= intelDestroyBuffer
,
1435 .MakeCurrent
= intelMakeCurrent
,
1436 .UnbindContext
= intelUnbindContext
,
1437 .AllocateBuffer
= intelAllocateBuffer
,
1438 .ReleaseBuffer
= intelReleaseBuffer
1441 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1442 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1443 .vtable
= &brw_driver_api
,
1446 static const __DRIextension
*brw_driver_extensions
[] = {
1447 &driCoreExtension
.base
,
1448 &driImageDriverExtension
.base
,
1449 &driDRI2Extension
.base
,
1451 &brw_config_options
.base
,
1455 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1457 globalDriverAPI
= &brw_driver_api
;
1459 return brw_driver_extensions
;