2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "compiler/nir/nir.h"
45 #ifndef DRM_FORMAT_MOD_INVALID
46 #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
49 #ifndef DRM_FORMAT_MOD_LINEAR
50 #define DRM_FORMAT_MOD_LINEAR 0
53 static const __DRIconfigOptionsExtension brw_config_options
= {
54 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
57 DRI_CONF_SECTION_PERFORMANCE
58 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
59 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
60 * DRI_CONF_BO_REUSE_ALL
62 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
63 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
64 DRI_CONF_ENUM(0, "Disable buffer object reuse")
65 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_FORCE_S3TC_ENABLE("false")
73 DRI_CONF_PRECISE_TRIG("false")
75 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
76 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
77 "given integer. If negative, then do not clamp.")
81 DRI_CONF_SECTION_DEBUG
82 DRI_CONF_NO_RAST("false")
83 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
84 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
85 DRI_CONF_DISABLE_THROTTLING("false")
86 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
87 DRI_CONF_FORCE_GLSL_VERSION(0)
88 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
89 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
90 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
91 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
92 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
93 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
95 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
96 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
100 DRI_CONF_SECTION_MISCELLANEOUS
101 DRI_CONF_GLSL_ZERO_INIT("false")
106 #include "intel_batchbuffer.h"
107 #include "intel_buffers.h"
108 #include "brw_bufmgr.h"
109 #include "intel_fbo.h"
110 #include "intel_mipmap_tree.h"
111 #include "intel_screen.h"
112 #include "intel_tex.h"
113 #include "intel_image.h"
115 #include "brw_context.h"
117 #include "i915_drm.h"
120 * For debugging purposes, this returns a time in seconds.
127 clock_gettime(CLOCK_MONOTONIC
, &tp
);
129 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
132 static const __DRItexBufferExtension intelTexBufferExtension
= {
133 .base
= { __DRI_TEX_BUFFER
, 3 },
135 .setTexBuffer
= intelSetTexBuffer
,
136 .setTexBuffer2
= intelSetTexBuffer2
,
137 .releaseTexBuffer
= NULL
,
141 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
142 __DRIdrawable
*dPriv
,
144 enum __DRI2throttleReason reason
)
146 struct brw_context
*brw
= cPriv
->driverPrivate
;
151 struct gl_context
*ctx
= &brw
->ctx
;
153 FLUSH_VERTICES(ctx
, 0);
155 if (flags
& __DRI2_FLUSH_DRAWABLE
)
156 intel_resolve_for_dri2_flush(brw
, dPriv
);
158 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
159 brw
->need_swap_throttle
= true;
160 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
161 brw
->need_flush_throttle
= true;
163 intel_batchbuffer_flush(brw
);
167 * Provides compatibility with loaders that only support the older (version
168 * 1-3) flush interface.
170 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
173 intel_dri2_flush(__DRIdrawable
*drawable
)
175 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
176 __DRI2_FLUSH_DRAWABLE
,
177 __DRI2_THROTTLE_SWAPBUFFER
);
180 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
181 .base
= { __DRI2_FLUSH
, 4 },
183 .flush
= intel_dri2_flush
,
184 .invalidate
= dri2InvalidateDrawable
,
185 .flush_with_flags
= intel_dri2_flush_with_flags
,
188 static struct intel_image_format intel_image_formats
[] = {
189 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
190 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
192 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
193 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
195 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
198 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
201 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
204 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
207 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
210 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
213 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
216 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
219 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
222 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
224 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
225 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
227 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
229 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
230 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
232 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
233 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
234 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
235 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
237 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
240 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
242 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
247 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
248 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
252 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
253 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
257 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
258 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
262 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
263 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
267 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
268 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
272 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
273 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
276 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
280 /* For YUYV buffers, we set up two overlapping DRI images and treat
281 * them as planar buffers in the compositors. Plane 0 is GR88 and
282 * samples YU or YV pairs and places Y into the R component, while
283 * plane 1 is ARGB and samples YUYV clusters and places pairs and
284 * places U into the G component and V into A. This lets the
285 * texture sampler interpolate the Y components correctly when
286 * sampling from plane 0, and interpolate U and V correctly when
287 * sampling from plane 1. */
288 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
289 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
290 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
293 static const struct {
296 } tiling_modifier_map
[] = {
297 { .tiling
= I915_TILING_NONE
, .modifier
= DRM_FORMAT_MOD_LINEAR
},
298 { .tiling
= I915_TILING_X
, .modifier
= I915_FORMAT_MOD_X_TILED
},
299 { .tiling
= I915_TILING_Y
, .modifier
= I915_FORMAT_MOD_Y_TILED
},
303 modifier_to_tiling(uint64_t modifier
)
307 for (i
= 0; i
< ARRAY_SIZE(tiling_modifier_map
); i
++) {
308 if (tiling_modifier_map
[i
].modifier
== modifier
)
309 return tiling_modifier_map
[i
].tiling
;
312 unreachable("modifier_to_tiling should only receive known modifiers");
316 tiling_to_modifier(uint32_t tiling
)
320 for (i
= 0; i
< ARRAY_SIZE(tiling_modifier_map
); i
++) {
321 if (tiling_modifier_map
[i
].tiling
== tiling
)
322 return tiling_modifier_map
[i
].modifier
;
325 unreachable("tiling_to_modifier received unknown tiling mode");
329 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
331 uint32_t tiling
, swizzle
;
332 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
334 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
335 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
336 func
, image
->offset
);
340 static struct intel_image_format
*
341 intel_image_format_lookup(int fourcc
)
343 struct intel_image_format
*f
= NULL
;
345 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
346 if (intel_image_formats
[i
].fourcc
== fourcc
) {
347 f
= &intel_image_formats
[i
];
355 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
357 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
358 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
359 *fourcc
= intel_image_formats
[i
].fourcc
;
367 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
372 image
= calloc(1, sizeof *image
);
376 image
->screen
= screen
;
377 image
->dri_format
= dri_format
;
380 image
->format
= driImageFormatToGLFormat(dri_format
);
381 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
382 image
->format
== MESA_FORMAT_NONE
) {
387 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
388 image
->data
= loaderPrivate
;
394 * Sets up a DRIImage structure to point to a slice out of a miptree.
397 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
398 struct intel_mipmap_tree
*mt
, GLuint level
,
401 intel_miptree_make_shareable(brw
, mt
);
403 intel_miptree_check_level_layer(mt
, level
, zoffset
);
405 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
406 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
407 image
->pitch
= mt
->pitch
;
409 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
413 brw_bo_unreference(image
->bo
);
415 brw_bo_reference(mt
->bo
);
419 intel_create_image_from_name(__DRIscreen
*dri_screen
,
420 int width
, int height
, int format
,
421 int name
, int pitch
, void *loaderPrivate
)
423 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
427 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
431 if (image
->format
== MESA_FORMAT_NONE
)
434 cpp
= _mesa_get_format_bytes(image
->format
);
436 image
->width
= width
;
437 image
->height
= height
;
438 image
->pitch
= pitch
* cpp
;
439 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
445 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
451 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
452 int renderbuffer
, void *loaderPrivate
)
455 struct brw_context
*brw
= context
->driverPrivate
;
456 struct gl_context
*ctx
= &brw
->ctx
;
457 struct gl_renderbuffer
*rb
;
458 struct intel_renderbuffer
*irb
;
460 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
462 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
466 irb
= intel_renderbuffer(rb
);
467 intel_miptree_make_shareable(brw
, irb
->mt
);
468 image
= calloc(1, sizeof *image
);
472 image
->internal_format
= rb
->InternalFormat
;
473 image
->format
= rb
->Format
;
474 image
->modifier
= tiling_to_modifier(irb
->mt
->tiling
);
476 image
->data
= loaderPrivate
;
477 brw_bo_unreference(image
->bo
);
478 image
->bo
= irb
->mt
->bo
;
479 brw_bo_reference(irb
->mt
->bo
);
480 image
->width
= rb
->Width
;
481 image
->height
= rb
->Height
;
482 image
->pitch
= irb
->mt
->pitch
;
483 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
484 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
486 rb
->NeedsFinishRenderTexture
= true;
491 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
492 unsigned texture
, int zoffset
,
498 struct brw_context
*brw
= context
->driverPrivate
;
499 struct gl_texture_object
*obj
;
500 struct intel_texture_object
*iobj
;
503 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
504 if (!obj
|| obj
->Target
!= target
) {
505 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
509 if (target
== GL_TEXTURE_CUBE_MAP
)
512 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
513 iobj
= intel_texture_object(obj
);
514 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
515 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
519 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
520 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
524 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
525 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
528 image
= calloc(1, sizeof *image
);
530 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
534 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
535 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
536 image
->modifier
= tiling_to_modifier(iobj
->mt
->tiling
);
537 image
->data
= loaderPrivate
;
538 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
539 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
540 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
541 if (image
->dri_format
== MESA_FORMAT_NONE
) {
542 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
547 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
552 intel_destroy_image(__DRIimage
*image
)
554 brw_bo_unreference(image
->bo
);
558 enum modifier_priority
{
559 MODIFIER_PRIORITY_INVALID
= 0,
560 MODIFIER_PRIORITY_LINEAR
,
565 const uint64_t priority_to_modifier
[] = {
566 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
567 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
568 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
569 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
573 select_best_modifier(struct gen_device_info
*devinfo
,
574 const uint64_t *modifiers
,
575 const unsigned count
)
577 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
579 for (int i
= 0; i
< count
; i
++) {
580 switch (modifiers
[i
]) {
581 case I915_FORMAT_MOD_Y_TILED
:
582 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
584 case I915_FORMAT_MOD_X_TILED
:
585 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
587 case DRM_FORMAT_MOD_LINEAR
:
588 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
590 case DRM_FORMAT_MOD_INVALID
:
596 return priority_to_modifier
[prio
];
600 intel_create_image_common(__DRIscreen
*dri_screen
,
601 int width
, int height
, int format
,
603 const uint64_t *modifiers
,
608 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
612 /* Callers of this may specify a modifier, or a dri usage, but not both. The
613 * newer modifier interface deprecates the older usage flags newer modifier
614 * interface deprecates the older usage flags.
616 assert(!(use
&& count
));
618 uint64_t modifier
= select_best_modifier(&screen
->devinfo
, modifiers
, count
);
619 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
620 /* User requested specific modifiers, none of which work */
624 /* Historically, X-tiled was the default, and so lack of modifier means
627 tiling
= I915_TILING_X
;
629 /* select_best_modifier has found a modifier we support */
630 tiling
= modifier_to_tiling(modifier
);
633 if (use
& __DRI_IMAGE_USE_CURSOR
) {
634 if (width
!= 64 || height
!= 64)
636 tiling
= I915_TILING_NONE
;
639 if (use
& __DRI_IMAGE_USE_LINEAR
)
640 tiling
= I915_TILING_NONE
;
642 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
646 cpp
= _mesa_get_format_bytes(image
->format
);
647 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
648 width
, height
, cpp
, tiling
,
650 if (image
->bo
== NULL
) {
654 image
->width
= width
;
655 image
->height
= height
;
656 image
->modifier
= modifier
;
662 intel_create_image(__DRIscreen
*dri_screen
,
663 int width
, int height
, int format
,
667 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
672 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
673 int width
, int height
, int format
,
674 const uint64_t *modifiers
,
675 const unsigned count
,
678 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
679 modifiers
, count
, loaderPrivate
);
683 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
686 case __DRI_IMAGE_ATTRIB_STRIDE
:
687 *value
= image
->pitch
;
689 case __DRI_IMAGE_ATTRIB_HANDLE
:
690 *value
= image
->bo
->gem_handle
;
692 case __DRI_IMAGE_ATTRIB_NAME
:
693 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
694 case __DRI_IMAGE_ATTRIB_FORMAT
:
695 *value
= image
->dri_format
;
697 case __DRI_IMAGE_ATTRIB_WIDTH
:
698 *value
= image
->width
;
700 case __DRI_IMAGE_ATTRIB_HEIGHT
:
701 *value
= image
->height
;
703 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
704 if (image
->planar_format
== NULL
)
706 *value
= image
->planar_format
->components
;
708 case __DRI_IMAGE_ATTRIB_FD
:
709 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
710 case __DRI_IMAGE_ATTRIB_FOURCC
:
711 return intel_lookup_fourcc(image
->dri_format
, value
);
712 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
715 case __DRI_IMAGE_ATTRIB_OFFSET
:
716 *value
= image
->offset
;
718 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
719 *value
= (image
->modifier
& 0xffffffff);
721 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
722 *value
= ((image
->modifier
>> 32) & 0xffffffff);
731 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
735 image
= calloc(1, sizeof *image
);
739 brw_bo_reference(orig_image
->bo
);
740 image
->bo
= orig_image
->bo
;
741 image
->internal_format
= orig_image
->internal_format
;
742 image
->planar_format
= orig_image
->planar_format
;
743 image
->dri_format
= orig_image
->dri_format
;
744 image
->format
= orig_image
->format
;
745 image
->modifier
= orig_image
->modifier
;
746 image
->offset
= orig_image
->offset
;
747 image
->width
= orig_image
->width
;
748 image
->height
= orig_image
->height
;
749 image
->pitch
= orig_image
->pitch
;
750 image
->tile_x
= orig_image
->tile_x
;
751 image
->tile_y
= orig_image
->tile_y
;
752 image
->has_depthstencil
= orig_image
->has_depthstencil
;
753 image
->data
= loaderPrivate
;
755 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
756 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
762 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
764 if (use
& __DRI_IMAGE_USE_CURSOR
) {
765 if (image
->width
!= 64 || image
->height
!= 64)
773 intel_create_image_from_names(__DRIscreen
*dri_screen
,
774 int width
, int height
, int fourcc
,
775 int *names
, int num_names
,
776 int *strides
, int *offsets
,
779 struct intel_image_format
*f
= NULL
;
783 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
786 f
= intel_image_format_lookup(fourcc
);
790 image
= intel_create_image_from_name(dri_screen
, width
, height
,
791 __DRI_IMAGE_FORMAT_NONE
,
792 names
[0], strides
[0],
798 image
->planar_format
= f
;
799 for (i
= 0; i
< f
->nplanes
; i
++) {
800 index
= f
->planes
[i
].buffer_index
;
801 image
->offsets
[index
] = offsets
[index
];
802 image
->strides
[index
] = strides
[index
];
809 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
810 int width
, int height
, int fourcc
,
811 int *fds
, int num_fds
, int *strides
, int *offsets
,
814 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
815 struct intel_image_format
*f
;
819 if (fds
== NULL
|| num_fds
< 1)
822 /* We only support all planes from the same bo */
823 for (i
= 0; i
< num_fds
; i
++)
824 if (fds
[0] != fds
[i
])
827 f
= intel_image_format_lookup(fourcc
);
832 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
835 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
841 image
->width
= width
;
842 image
->height
= height
;
843 image
->pitch
= strides
[0];
845 image
->planar_format
= f
;
847 for (i
= 0; i
< f
->nplanes
; i
++) {
848 index
= f
->planes
[i
].buffer_index
;
849 image
->offsets
[index
] = offsets
[index
];
850 image
->strides
[index
] = strides
[index
];
852 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
853 const int end
= offsets
[index
] + plane_height
* strides
[index
];
858 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
,
860 if (image
->bo
== NULL
) {
864 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
866 if (f
->nplanes
== 1) {
867 image
->offset
= image
->offsets
[0];
868 intel_image_warn_if_unaligned(image
, __func__
);
875 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
876 int width
, int height
, int fourcc
,
877 int *fds
, int num_fds
,
878 int *strides
, int *offsets
,
879 enum __DRIYUVColorSpace yuv_color_space
,
880 enum __DRISampleRange sample_range
,
881 enum __DRIChromaSiting horizontal_siting
,
882 enum __DRIChromaSiting vertical_siting
,
887 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
890 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
894 image
= intel_create_image_from_fds(dri_screen
, width
, height
, fourcc
, fds
,
895 num_fds
, strides
, offsets
,
899 * Invalid parameters and any inconsistencies between are assumed to be
900 * checked by the caller. Therefore besides unsupported formats one can fail
901 * only in allocation.
904 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
908 image
->dma_buf_imported
= true;
909 image
->yuv_color_space
= yuv_color_space
;
910 image
->sample_range
= sample_range
;
911 image
->horizontal_siting
= horizontal_siting
;
912 image
->vertical_siting
= vertical_siting
;
914 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
919 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
921 int width
, height
, offset
, stride
, dri_format
, index
;
922 struct intel_image_format
*f
;
925 if (parent
== NULL
|| parent
->planar_format
== NULL
)
928 f
= parent
->planar_format
;
930 if (plane
>= f
->nplanes
)
933 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
934 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
935 dri_format
= f
->planes
[plane
].dri_format
;
936 index
= f
->planes
[plane
].buffer_index
;
937 offset
= parent
->offsets
[index
];
938 stride
= parent
->strides
[index
];
940 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
944 if (offset
+ height
* stride
> parent
->bo
->size
) {
945 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
950 image
->bo
= parent
->bo
;
951 brw_bo_reference(parent
->bo
);
952 image
->modifier
= parent
->modifier
;
954 image
->width
= width
;
955 image
->height
= height
;
956 image
->pitch
= stride
;
957 image
->offset
= offset
;
959 intel_image_warn_if_unaligned(image
, __func__
);
964 static const __DRIimageExtension intelImageExtension
= {
965 .base
= { __DRI_IMAGE
, 14 },
967 .createImageFromName
= intel_create_image_from_name
,
968 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
969 .destroyImage
= intel_destroy_image
,
970 .createImage
= intel_create_image
,
971 .queryImage
= intel_query_image
,
972 .dupImage
= intel_dup_image
,
973 .validateUsage
= intel_validate_usage
,
974 .createImageFromNames
= intel_create_image_from_names
,
975 .fromPlanar
= intel_from_planar
,
976 .createImageFromTexture
= intel_create_image_from_texture
,
977 .createImageFromFds
= intel_create_image_from_fds
,
978 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
980 .getCapabilities
= NULL
,
983 .createImageWithModifiers
= intel_create_image_with_modifiers
,
987 get_aperture_size(int fd
)
989 struct drm_i915_gem_get_aperture aperture
;
991 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
994 return aperture
.aper_size
;
998 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
999 int param
, unsigned int *value
)
1001 const struct intel_screen
*const screen
=
1002 (struct intel_screen
*) dri_screen
->driverPrivate
;
1005 case __DRI2_RENDERER_VENDOR_ID
:
1008 case __DRI2_RENDERER_DEVICE_ID
:
1009 value
[0] = screen
->deviceID
;
1011 case __DRI2_RENDERER_ACCELERATED
:
1014 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1015 /* Once a batch uses more than 75% of the maximum mappable size, we
1016 * assume that there's some fragmentation, and we start doing extra
1017 * flushing, etc. That's the big cliff apps will care about.
1019 const unsigned gpu_mappable_megabytes
=
1020 screen
->aperture_threshold
/ (1024 * 1024);
1022 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1023 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1025 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1028 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1029 * (uint64_t) system_page_size
;
1031 const unsigned system_memory_megabytes
=
1032 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1034 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1037 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1040 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1044 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1051 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1052 int param
, const char **value
)
1054 const struct intel_screen
*screen
=
1055 (struct intel_screen
*) dri_screen
->driverPrivate
;
1058 case __DRI2_RENDERER_VENDOR_ID
:
1059 value
[0] = brw_vendor_string
;
1061 case __DRI2_RENDERER_DEVICE_ID
:
1062 value
[0] = brw_get_renderer_string(screen
);
1071 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1072 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1074 .queryInteger
= brw_query_renderer_integer
,
1075 .queryString
= brw_query_renderer_string
1078 static const __DRIrobustnessExtension dri2Robustness
= {
1079 .base
= { __DRI2_ROBUSTNESS
, 1 }
1082 static const __DRIextension
*screenExtensions
[] = {
1083 &intelTexBufferExtension
.base
,
1084 &intelFenceExtension
.base
,
1085 &intelFlushExtension
.base
,
1086 &intelImageExtension
.base
,
1087 &intelRendererQueryExtension
.base
,
1088 &dri2ConfigQueryExtension
.base
,
1092 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1093 &intelTexBufferExtension
.base
,
1094 &intelFenceExtension
.base
,
1095 &intelFlushExtension
.base
,
1096 &intelImageExtension
.base
,
1097 &intelRendererQueryExtension
.base
,
1098 &dri2ConfigQueryExtension
.base
,
1099 &dri2Robustness
.base
,
1104 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1107 struct drm_i915_getparam gp
;
1109 memset(&gp
, 0, sizeof(gp
));
1113 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1116 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1123 intel_get_boolean(struct intel_screen
*screen
, int param
)
1126 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1130 intel_get_integer(struct intel_screen
*screen
, int param
)
1134 if (intel_get_param(screen
, param
, &value
) == 0)
1141 intelDestroyScreen(__DRIscreen
* sPriv
)
1143 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1145 brw_bufmgr_destroy(screen
->bufmgr
);
1146 driDestroyOptionInfo(&screen
->optionCache
);
1148 ralloc_free(screen
);
1149 sPriv
->driverPrivate
= NULL
;
1154 * This is called when we need to set up GL rendering to a new X window.
1157 intelCreateBuffer(__DRIscreen
*dri_screen
,
1158 __DRIdrawable
* driDrawPriv
,
1159 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1161 struct intel_renderbuffer
*rb
;
1162 struct intel_screen
*screen
= (struct intel_screen
*)
1163 dri_screen
->driverPrivate
;
1164 mesa_format rgbFormat
;
1165 unsigned num_samples
=
1166 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1167 struct gl_framebuffer
*fb
;
1172 fb
= CALLOC_STRUCT(gl_framebuffer
);
1176 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1178 if (screen
->winsys_msaa_samples_override
!= -1) {
1179 num_samples
= screen
->winsys_msaa_samples_override
;
1180 fb
->Visual
.samples
= num_samples
;
1183 if (mesaVis
->redBits
== 5) {
1184 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1185 : MESA_FORMAT_B5G6R5_UNORM
;
1186 } else if (mesaVis
->sRGBCapable
) {
1187 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1188 : MESA_FORMAT_B8G8R8A8_SRGB
;
1189 } else if (mesaVis
->alphaBits
== 0) {
1190 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1191 : MESA_FORMAT_B8G8R8X8_UNORM
;
1193 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1194 : MESA_FORMAT_B8G8R8A8_SRGB
;
1195 fb
->Visual
.sRGBCapable
= true;
1198 /* setup the hardware-based renderbuffers */
1199 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1200 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1202 if (mesaVis
->doubleBufferMode
) {
1203 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1204 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1208 * Assert here that the gl_config has an expected depth/stencil bit
1209 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1210 * which constructs the advertised configs.)
1212 if (mesaVis
->depthBits
== 24) {
1213 assert(mesaVis
->stencilBits
== 8);
1215 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1216 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1218 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1219 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1221 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1224 * Use combined depth/stencil. Note that the renderbuffer is
1225 * attached to two attachment points.
1227 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1229 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1230 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1233 else if (mesaVis
->depthBits
== 16) {
1234 assert(mesaVis
->stencilBits
== 0);
1235 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1237 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1240 assert(mesaVis
->depthBits
== 0);
1241 assert(mesaVis
->stencilBits
== 0);
1244 /* now add any/all software-based renderbuffers we may need */
1245 _swrast_add_soft_renderbuffers(fb
,
1246 false, /* never sw color */
1247 false, /* never sw depth */
1248 false, /* never sw stencil */
1249 mesaVis
->accumRedBits
> 0,
1250 false, /* never sw alpha */
1251 false /* never sw aux */ );
1252 driDrawPriv
->driverPrivate
= fb
;
1258 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1260 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1262 _mesa_reference_framebuffer(&fb
, NULL
);
1266 intel_detect_sseu(struct intel_screen
*screen
)
1268 assert(screen
->devinfo
.gen
>= 8);
1271 screen
->subslice_total
= -1;
1272 screen
->eu_total
= -1;
1274 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1275 &screen
->subslice_total
);
1276 if (ret
< 0 && ret
!= -EINVAL
)
1279 ret
= intel_get_param(screen
,
1280 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1281 if (ret
< 0 && ret
!= -EINVAL
)
1284 /* Without this information, we cannot get the right Braswell brandstrings,
1285 * and we have to use conservative numbers for GPGPU on many platforms, but
1286 * otherwise, things will just work.
1288 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1290 "Kernel 4.1 required to properly query GPU properties.\n");
1295 screen
->subslice_total
= -1;
1296 screen
->eu_total
= -1;
1297 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1301 intel_init_bufmgr(struct intel_screen
*screen
)
1303 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1305 if (getenv("INTEL_NO_HW") != NULL
)
1306 screen
->no_hw
= true;
1308 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
, BATCH_SZ
);
1309 if (screen
->bufmgr
== NULL
) {
1310 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1311 __func__
, __LINE__
);
1315 if (!intel_get_boolean(screen
, I915_PARAM_HAS_WAIT_TIMEOUT
)) {
1316 fprintf(stderr
, "[%s: %u] Kernel 3.6 required.\n", __func__
, __LINE__
);
1324 intel_detect_swizzling(struct intel_screen
*screen
)
1326 struct brw_bo
*buffer
;
1328 uint32_t aligned_pitch
;
1329 uint32_t tiling
= I915_TILING_X
;
1330 uint32_t swizzle_mode
= 0;
1332 buffer
= brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1333 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1337 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1338 brw_bo_unreference(buffer
);
1340 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1347 intel_detect_timestamp(struct intel_screen
*screen
)
1349 uint64_t dummy
= 0, last
= 0;
1350 int upper
, lower
, loops
;
1352 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1353 * TIMESTAMP register being shifted and the low 32bits always zero.
1355 * More recent kernels offer an interface to read the full 36bits
1358 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1361 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1362 * upper 32bits for a rapidly changing timestamp.
1364 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1368 for (loops
= 0; loops
< 10; loops
++) {
1369 /* The TIMESTAMP should change every 80ns, so several round trips
1370 * through the kernel should be enough to advance it.
1372 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1375 upper
+= (dummy
>> 32) != (last
>> 32);
1376 if (upper
> 1) /* beware 32bit counter overflow */
1377 return 2; /* upper dword holds the low 32bits of the timestamp */
1379 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1381 return 1; /* timestamp is unshifted */
1386 /* No advancement? No timestamp! */
1391 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1393 * Some combinations of hardware and kernel versions allow this feature,
1394 * while others don't. Instead of trying to enumerate every case, just
1395 * try and write a register and see if works.
1398 intel_detect_pipelined_register(struct intel_screen
*screen
,
1399 int reg
, uint32_t expected_value
, bool reset
)
1404 struct brw_bo
*results
, *bo
;
1406 uint32_t offset
= 0;
1407 bool success
= false;
1409 /* Create a zero'ed temporary buffer for reading our results */
1410 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1411 if (results
== NULL
)
1414 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1418 if (brw_bo_map(NULL
, bo
, 1))
1421 batch
= bo
->virtual;
1423 /* Write the register. */
1424 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1426 *batch
++ = expected_value
;
1428 /* Save the register's value back to the buffer. */
1429 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1431 struct drm_i915_gem_relocation_entry reloc
= {
1432 .offset
= (char *) batch
- (char *) bo
->virtual,
1433 .delta
= offset
* sizeof(uint32_t),
1434 .target_handle
= results
->gem_handle
,
1435 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1436 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1438 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1440 /* And afterwards clear the register */
1442 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1447 *batch
++ = MI_BATCH_BUFFER_END
;
1449 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1451 .handle
= results
->gem_handle
,
1454 .handle
= bo
->gem_handle
,
1455 .relocation_count
= 1,
1456 .relocs_ptr
= (uintptr_t) &reloc
,
1460 struct drm_i915_gem_execbuffer2 execbuf
= {
1461 .buffers_ptr
= (uintptr_t) exec_objects
,
1463 .batch_len
= ALIGN((char *) batch
- (char *) bo
->virtual, 8),
1464 .flags
= I915_EXEC_RENDER
,
1467 /* Don't bother with error checking - if the execbuf fails, the
1468 * value won't be written and we'll just report that there's no access.
1470 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1471 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1473 /* Check whether the value got written. */
1474 if (brw_bo_map(NULL
, results
, false) == 0) {
1475 success
= *((uint32_t *)results
->virtual + offset
) == expected_value
;
1476 brw_bo_unmap(results
);
1480 brw_bo_unreference(bo
);
1482 brw_bo_unreference(results
);
1488 intel_detect_pipelined_so(struct intel_screen
*screen
)
1490 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1492 /* Supposedly, Broadwell just works. */
1493 if (devinfo
->gen
>= 8)
1496 if (devinfo
->gen
<= 6)
1499 /* See the big explanation about command parser versions below */
1500 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1503 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1504 * statistics registers), and we already reset it to zero before using it.
1506 return intel_detect_pipelined_register(screen
,
1507 GEN7_SO_WRITE_OFFSET(0),
1513 * Return array of MSAA modes supported by the hardware. The array is
1514 * zero-terminated and sorted in decreasing order.
1517 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1519 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1520 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1521 static const int gen7_modes
[] = {8, 4, 0, -1};
1522 static const int gen6_modes
[] = {4, 0, -1};
1523 static const int gen4_modes
[] = {0, -1};
1525 if (screen
->devinfo
.gen
>= 9) {
1527 } else if (screen
->devinfo
.gen
>= 8) {
1529 } else if (screen
->devinfo
.gen
>= 7) {
1531 } else if (screen
->devinfo
.gen
== 6) {
1538 static __DRIconfig
**
1539 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1541 static const mesa_format formats
[] = {
1542 MESA_FORMAT_B5G6R5_UNORM
,
1543 MESA_FORMAT_B8G8R8A8_UNORM
,
1544 MESA_FORMAT_B8G8R8X8_UNORM
1547 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1548 static const GLenum back_buffer_modes
[] = {
1549 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1552 static const uint8_t singlesample_samples
[1] = {0};
1553 static const uint8_t multisample_samples
[2] = {4, 8};
1555 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1556 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1557 uint8_t depth_bits
[4], stencil_bits
[4];
1558 __DRIconfig
**configs
= NULL
;
1560 /* Generate singlesample configs without accumulation buffer. */
1561 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1562 __DRIconfig
**new_configs
;
1563 int num_depth_stencil_bits
= 2;
1565 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1566 * buffer that has a different number of bits per pixel than the color
1567 * buffer, gen >= 6 supports this.
1570 stencil_bits
[0] = 0;
1572 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1574 stencil_bits
[1] = 0;
1575 if (devinfo
->gen
>= 6) {
1577 stencil_bits
[2] = 8;
1578 num_depth_stencil_bits
= 3;
1582 stencil_bits
[1] = 8;
1585 new_configs
= driCreateConfigs(formats
[i
],
1588 num_depth_stencil_bits
,
1589 back_buffer_modes
, 2,
1590 singlesample_samples
, 1,
1592 configs
= driConcatConfigs(configs
, new_configs
);
1595 /* Generate the minimum possible set of configs that include an
1596 * accumulation buffer.
1598 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1599 __DRIconfig
**new_configs
;
1601 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1603 stencil_bits
[0] = 0;
1606 stencil_bits
[0] = 8;
1609 new_configs
= driCreateConfigs(formats
[i
],
1610 depth_bits
, stencil_bits
, 1,
1611 back_buffer_modes
, 1,
1612 singlesample_samples
, 1,
1614 configs
= driConcatConfigs(configs
, new_configs
);
1617 /* Generate multisample configs.
1619 * This loop breaks early, and hence is a no-op, on gen < 6.
1621 * Multisample configs must follow the singlesample configs in order to
1622 * work around an X server bug present in 1.12. The X server chooses to
1623 * associate the first listed RGBA888-Z24S8 config, regardless of its
1624 * sample count, with the 32-bit depth visual used for compositing.
1626 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1627 * supported. Singlebuffer configs are not supported because no one wants
1630 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1631 if (devinfo
->gen
< 6)
1634 __DRIconfig
**new_configs
;
1635 const int num_depth_stencil_bits
= 2;
1636 int num_msaa_modes
= 0;
1639 stencil_bits
[0] = 0;
1641 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1643 stencil_bits
[1] = 0;
1646 stencil_bits
[1] = 8;
1649 if (devinfo
->gen
>= 7)
1651 else if (devinfo
->gen
== 6)
1654 new_configs
= driCreateConfigs(formats
[i
],
1657 num_depth_stencil_bits
,
1658 back_buffer_modes
, 1,
1659 multisample_samples
,
1662 configs
= driConcatConfigs(configs
, new_configs
);
1665 if (configs
== NULL
) {
1666 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1675 set_max_gl_versions(struct intel_screen
*screen
)
1677 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1678 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1680 switch (screen
->devinfo
.gen
) {
1683 dri_screen
->max_gl_core_version
= 45;
1684 dri_screen
->max_gl_compat_version
= 30;
1685 dri_screen
->max_gl_es1_version
= 11;
1686 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1689 dri_screen
->max_gl_core_version
= 33;
1690 if (can_do_pipelined_register_writes(screen
)) {
1691 dri_screen
->max_gl_core_version
= 42;
1692 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
1693 dri_screen
->max_gl_core_version
= 43;
1694 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
1695 dri_screen
->max_gl_core_version
= 45;
1697 dri_screen
->max_gl_compat_version
= 30;
1698 dri_screen
->max_gl_es1_version
= 11;
1699 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1702 dri_screen
->max_gl_core_version
= 33;
1703 dri_screen
->max_gl_compat_version
= 30;
1704 dri_screen
->max_gl_es1_version
= 11;
1705 dri_screen
->max_gl_es2_version
= 30;
1709 dri_screen
->max_gl_core_version
= 0;
1710 dri_screen
->max_gl_compat_version
= 21;
1711 dri_screen
->max_gl_es1_version
= 11;
1712 dri_screen
->max_gl_es2_version
= 20;
1715 unreachable("unrecognized intel_screen::gen");
1720 * Return the revision (generally the revid field of the PCI header) of the
1723 * XXX: This function is useful to keep around even if it is not currently in
1724 * use. It is necessary for new platforms and revision specific workarounds or
1725 * features. Please don't remove it so that we know it at least continues to
1728 static __attribute__((__unused__
)) int
1729 brw_get_revision(int fd
)
1731 struct drm_i915_getparam gp
;
1735 memset(&gp
, 0, sizeof(gp
));
1736 gp
.param
= I915_PARAM_REVISION
;
1737 gp
.value
= &revision
;
1739 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1747 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1749 struct brw_context
*brw
= (struct brw_context
*)data
;
1752 va_start(args
, fmt
);
1754 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1755 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1756 MESA_DEBUG_TYPE_OTHER
,
1757 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1762 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1764 struct brw_context
*brw
= (struct brw_context
*)data
;
1767 va_start(args
, fmt
);
1769 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1771 va_copy(args_copy
, args
);
1772 vfprintf(stderr
, fmt
, args_copy
);
1776 if (brw
->perf_debug
) {
1778 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1779 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1780 MESA_DEBUG_TYPE_PERFORMANCE
,
1781 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1787 parse_devid_override(const char *devid_override
)
1789 static const struct {
1805 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
1806 if (!strcmp(name_map
[i
].name
, devid_override
))
1807 return name_map
[i
].pci_id
;
1810 return strtod(devid_override
, NULL
);
1814 * Get the PCI ID for the device. This can be overridden by setting the
1815 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
1817 * Returns -1 on ioctl failure.
1820 get_pci_device_id(struct intel_screen
*screen
)
1822 if (geteuid() == getuid()) {
1823 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
1824 if (devid_override
) {
1825 screen
->no_hw
= true;
1826 return parse_devid_override(devid_override
);
1830 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
1834 * This is the driver specific part of the createNewScreen entry point.
1835 * Called when using DRI2.
1837 * \return the struct gl_config supported by this driver
1840 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
1842 struct intel_screen
*screen
;
1844 if (dri_screen
->image
.loader
) {
1845 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
1846 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1848 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1849 "support required\n");
1853 /* Allocate the private area */
1854 screen
= rzalloc(NULL
, struct intel_screen
);
1856 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1859 /* parse information in __driConfigOptions */
1860 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
1862 screen
->driScrnPriv
= dri_screen
;
1863 dri_screen
->driverPrivate
= (void *) screen
;
1865 screen
->deviceID
= get_pci_device_id(screen
);
1867 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
1870 if (!intel_init_bufmgr(screen
))
1873 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1875 brw_process_intel_debug_variable();
1877 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
1879 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1880 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1883 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1884 /* Theorectically unlimited! At least for individual objects...
1886 * Currently the entire (global) address space for all GTT maps is
1887 * limited to 64bits. That is all objects on the system that are
1888 * setup for GTT mmapping must fit within 64bits. An attempt to use
1889 * one that exceeds the limit with fail in brw_bo_map_gtt().
1891 * Long before we hit that limit, we will be practically limited by
1892 * that any single object must fit in physical memory (RAM). The upper
1893 * limit on the CPU's address space is currently 48bits (Skylake), of
1894 * which only 39bits can be physical memory. (The GPU itself also has
1895 * a 48bit addressable virtual space.) We can fit over 32 million
1896 * objects of the current maximum allocable size before running out
1899 screen
->max_gtt_map_object_size
= UINT64_MAX
;
1901 /* Estimate the size of the mappable aperture into the GTT. There's an
1902 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1903 * It turns out it's basically always 256MB, though some ancient hardware
1906 uint32_t gtt_size
= 256 * 1024 * 1024;
1908 /* We don't want to map two objects such that a memcpy between them would
1909 * just fault one mapping in and then the other over and over forever. So
1910 * we would need to divide the GTT size by 2. Additionally, some GTT is
1911 * taken up by things like the framebuffer and the ringbuffer and such, so
1912 * be more conservative.
1914 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
1917 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
1919 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
1920 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
1922 /* GENs prior to 8 do not support EU/Subslice info */
1923 if (devinfo
->gen
>= 8) {
1924 intel_detect_sseu(screen
);
1925 } else if (devinfo
->gen
== 7) {
1926 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
1929 /* Gen7-7.5 kernel requirements / command parser saga:
1932 * Haswell and Baytrail cannot use any privileged batchbuffer features.
1934 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
1935 * all batches secure, allowing them to use any feature with no checking.
1936 * This is effectively equivalent to a command parser version of
1937 * \infinity - everything is possible.
1939 * The command parser does not exist, and querying the version will
1943 * The kernel enables the command parser by default, for systems with
1944 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
1945 * hardware checker is still enabled, so Haswell and Baytrail cannot
1948 * Ivybridge goes from "everything is possible" to "only what the
1949 * command parser allows" (if the user boots with i915.cmd_parser=0,
1950 * then everything is possible again). We can only safely use features
1951 * allowed by the supported command parser version.
1953 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
1954 * implemented by the kernel, even if it's turned off. So, checking
1955 * for version > 0 does not mean that you can write registers. We have
1956 * to try it and see. The version does, however, indicate the age of
1959 * Instead of matching the hardware checker's behavior of converting
1960 * privileged commands to MI_NOOP, it makes execbuf2 start returning
1961 * -EINVAL, making it dangerous to try and use privileged features.
1963 * Effective command parser versions:
1964 * - Haswell: 0 (reporting 1, writes don't work)
1965 * - Baytrail: 0 (reporting 1, writes don't work)
1966 * - Ivybridge: 1 (enabled) or infinite (disabled)
1969 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
1970 * effectively version 1 (enabled) or infinite (disabled).
1972 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
1973 * Command parser v2 supports predicate writes.
1975 * - Haswell: 0 (reporting 1, writes don't work)
1976 * - Baytrail: 2 (enabled) or infinite (disabled)
1977 * - Ivybridge: 2 (enabled) or infinite (disabled)
1979 * So version >= 2 is enough to know that Ivybridge and Baytrail
1980 * will work. Haswell still can't do anything.
1982 * - v4.0: Version 3 happened. Largely not relevant.
1984 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
1985 * L3 config registers are properly saved and restored as part
1986 * of the hardware context. We can approximately detect this point
1987 * in time by checking if I915_PARAM_REVISION is recognized - it
1988 * landed in a later commit, but in the same release cycle.
1990 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
1991 * Command parser finally gains secure batch promotion. On Haswell,
1992 * the hardware checker gets disabled, which finally allows it to do
1993 * privileged commands.
1995 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
1996 * - Haswell: 3 (enabled) or 0 (disabled)
1997 * - Baytrail: 3 (enabled) or infinite (disabled)
1998 * - Ivybridge: 3 (enabled) or infinite (disabled)
2000 * Unfortunately, detecting this point in time is tricky, because
2001 * no version bump happened when this important change occurred.
2002 * On Haswell, if we can write any register, then the kernel is at
2003 * least this new, and we can start trusting the version number.
2005 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2006 * Command parser reaches version 4, allowing access to Haswell
2007 * atomic scratch and chicken3 registers. If version >= 4, we know
2008 * the kernel is new enough to support privileged features on all
2009 * hardware. However, the user might have disabled it...and the
2010 * kernel will still report version 4. So we still have to guess
2013 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2014 * Command parser v5 whitelists indirect compute shader dispatch
2015 * registers, needed for OpenGL 4.3 and later.
2018 * Command parser v7 lets us use MI_MATH on Haswell.
2020 * Additionally, the kernel begins reporting version 0 when
2021 * the command parser is disabled, allowing us to skip the
2022 * guess-and-check step on Haswell. Unfortunately, this also
2023 * means that we can no longer use it as an indicator of the
2024 * age of the kernel.
2026 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2027 &screen
->cmd_parser_version
) < 0) {
2028 /* Command parser does not exist - getparam is unrecognized */
2029 screen
->cmd_parser_version
= 0;
2032 /* Kernel 4.13 retuired for exec object capture */
2033 #ifndef I915_PARAM_HAS_EXEC_CAPTURE
2034 #define I915_PARAM_HAS_EXEC_CAPTURE 45
2036 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2037 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2040 if (!intel_detect_pipelined_so(screen
)) {
2041 /* We can't do anything, so the effective version is 0. */
2042 screen
->cmd_parser_version
= 0;
2044 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2047 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2048 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2050 /* Haswell requires command parser version 4 in order to have L3
2051 * atomic scratch1 and chicken3 bits
2053 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2054 screen
->kernel_features
|=
2055 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2058 /* Haswell requires command parser version 6 in order to write to the
2059 * MI_MATH GPR registers, and version 7 in order to use
2060 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2062 if (devinfo
->gen
>= 8 ||
2063 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2064 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2067 /* Gen7 needs at least command parser version 5 to support compute */
2068 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2069 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2071 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2073 screen
->winsys_msaa_samples_override
=
2074 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2075 printf("Forcing winsys sample count to %d\n",
2076 screen
->winsys_msaa_samples_override
);
2078 screen
->winsys_msaa_samples_override
= -1;
2081 set_max_gl_versions(screen
);
2083 /* Notification of GPU resets requires hardware contexts and a kernel new
2084 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2085 * supported, calling it with a context of 0 will either generate EPERM or
2086 * no error. If the ioctl is not supported, it always generate EINVAL.
2087 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2088 * extension to the loader.
2090 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2092 if (devinfo
->gen
>= 6) {
2093 struct drm_i915_reset_stats stats
;
2094 memset(&stats
, 0, sizeof(stats
));
2096 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2098 screen
->has_context_reset_notification
=
2099 (ret
!= -1 || errno
!= EINVAL
);
2102 dri_screen
->extensions
= !screen
->has_context_reset_notification
2103 ? screenExtensions
: intelRobustScreenExtensions
;
2105 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2106 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2107 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2108 screen
->program_id
= 1;
2110 screen
->has_exec_fence
=
2111 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2113 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2116 struct intel_buffer
{
2121 static __DRIbuffer
*
2122 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2123 unsigned attachment
, unsigned format
,
2124 int width
, int height
)
2126 struct intel_buffer
*intelBuffer
;
2127 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2129 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2130 attachment
== __DRI_BUFFER_BACK_LEFT
);
2132 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2133 if (intelBuffer
== NULL
)
2136 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2137 * supports Y tiled and compressed buffers, but there is no way to plumb that
2138 * through to here. */
2140 int cpp
= format
/ 8;
2141 intelBuffer
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
,
2142 "intelAllocateBuffer",
2146 I915_TILING_X
, &pitch
,
2147 BO_ALLOC_FOR_RENDER
);
2149 if (intelBuffer
->bo
== NULL
) {
2154 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2156 intelBuffer
->base
.attachment
= attachment
;
2157 intelBuffer
->base
.cpp
= cpp
;
2158 intelBuffer
->base
.pitch
= pitch
;
2160 return &intelBuffer
->base
;
2164 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2166 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2168 brw_bo_unreference(intelBuffer
->bo
);
2172 static const struct __DriverAPIRec brw_driver_api
= {
2173 .InitScreen
= intelInitScreen2
,
2174 .DestroyScreen
= intelDestroyScreen
,
2175 .CreateContext
= brwCreateContext
,
2176 .DestroyContext
= intelDestroyContext
,
2177 .CreateBuffer
= intelCreateBuffer
,
2178 .DestroyBuffer
= intelDestroyBuffer
,
2179 .MakeCurrent
= intelMakeCurrent
,
2180 .UnbindContext
= intelUnbindContext
,
2181 .AllocateBuffer
= intelAllocateBuffer
,
2182 .ReleaseBuffer
= intelReleaseBuffer
2185 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2186 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2187 .vtable
= &brw_driver_api
,
2190 static const __DRIextension
*brw_driver_extensions
[] = {
2191 &driCoreExtension
.base
,
2192 &driImageDriverExtension
.base
,
2193 &driDRI2Extension
.base
,
2195 &brw_config_options
.base
,
2199 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2201 globalDriverAPI
= &brw_driver_api
;
2203 return brw_driver_extensions
;