2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/context.h"
30 #include "main/framebuffer.h"
31 #include "main/renderbuffer.h"
32 #include "main/texobj.h"
33 #include "main/hash.h"
34 #include "main/fbobject.h"
35 #include "main/version.h"
36 #include "swrast/s_renderbuffer.h"
37 #include "util/ralloc.h"
38 #include "brw_shader.h"
39 #include "compiler/nir/nir.h"
44 static const __DRIconfigOptionsExtension brw_config_options
= {
45 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
48 DRI_CONF_SECTION_PERFORMANCE
49 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
50 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
51 * DRI_CONF_BO_REUSE_ALL
53 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
54 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
55 DRI_CONF_ENUM(0, "Disable buffer object reuse")
56 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
61 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_FORCE_S3TC_ENABLE("false")
68 DRI_CONF_PRECISE_TRIG("false")
70 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
71 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
72 "given integer. If negative, then do not clamp.")
76 DRI_CONF_SECTION_DEBUG
77 DRI_CONF_NO_RAST("false")
78 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
79 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
80 DRI_CONF_DISABLE_THROTTLING("false")
81 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
82 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
83 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
84 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
85 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
87 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
88 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
92 DRI_CONF_SECTION_MISCELLANEOUS
93 DRI_CONF_GLSL_ZERO_INIT("false")
98 #include "intel_batchbuffer.h"
99 #include "intel_buffers.h"
100 #include "intel_bufmgr.h"
101 #include "intel_fbo.h"
102 #include "intel_mipmap_tree.h"
103 #include "intel_screen.h"
104 #include "intel_tex.h"
105 #include "intel_image.h"
107 #include "brw_context.h"
109 #include "i915_drm.h"
112 * For debugging purposes, this returns a time in seconds.
119 clock_gettime(CLOCK_MONOTONIC
, &tp
);
121 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
125 aub_dump_bmp(struct gl_context
*ctx
)
127 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
129 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
130 struct intel_renderbuffer
*irb
=
131 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
133 if (irb
&& irb
->mt
) {
134 enum aub_dump_bmp_format format
;
136 switch (irb
->Base
.Base
.Format
) {
137 case MESA_FORMAT_B8G8R8A8_UNORM
:
138 case MESA_FORMAT_B8G8R8X8_UNORM
:
139 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
145 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
148 irb
->Base
.Base
.Width
,
149 irb
->Base
.Base
.Height
,
157 static const __DRItexBufferExtension intelTexBufferExtension
= {
158 .base
= { __DRI_TEX_BUFFER
, 3 },
160 .setTexBuffer
= intelSetTexBuffer
,
161 .setTexBuffer2
= intelSetTexBuffer2
,
162 .releaseTexBuffer
= NULL
,
166 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
167 __DRIdrawable
*dPriv
,
169 enum __DRI2throttleReason reason
)
171 struct brw_context
*brw
= cPriv
->driverPrivate
;
176 struct gl_context
*ctx
= &brw
->ctx
;
178 FLUSH_VERTICES(ctx
, 0);
180 if (flags
& __DRI2_FLUSH_DRAWABLE
)
181 intel_resolve_for_dri2_flush(brw
, dPriv
);
183 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
184 brw
->need_swap_throttle
= true;
185 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
186 brw
->need_flush_throttle
= true;
188 intel_batchbuffer_flush(brw
);
190 if (INTEL_DEBUG
& DEBUG_AUB
) {
196 * Provides compatibility with loaders that only support the older (version
197 * 1-3) flush interface.
199 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
202 intel_dri2_flush(__DRIdrawable
*drawable
)
204 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
205 __DRI2_FLUSH_DRAWABLE
,
206 __DRI2_THROTTLE_SWAPBUFFER
);
209 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
210 .base
= { __DRI2_FLUSH
, 4 },
212 .flush
= intel_dri2_flush
,
213 .invalidate
= dri2InvalidateDrawable
,
214 .flush_with_flags
= intel_dri2_flush_with_flags
,
217 static struct intel_image_format intel_image_formats
[] = {
218 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
221 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
224 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
227 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
230 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
233 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
236 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
239 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
242 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
247 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
248 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
252 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
253 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
257 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
258 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
262 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
263 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
267 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
268 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
272 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
273 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
275 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
277 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
278 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
279 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
280 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
282 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
283 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
284 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
285 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
287 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
288 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
289 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
290 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
292 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
293 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
294 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
296 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
297 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
298 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
300 /* For YUYV buffers, we set up two overlapping DRI images and treat
301 * them as planar buffers in the compositors. Plane 0 is GR88 and
302 * samples YU or YV pairs and places Y into the R component, while
303 * plane 1 is ARGB and samples YUYV clusters and places pairs and
304 * places U into the G component and V into A. This lets the
305 * texture sampler interpolate the Y components correctly when
306 * sampling from plane 0, and interpolate U and V correctly when
307 * sampling from plane 1. */
308 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
309 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
310 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
314 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
316 uint32_t tiling
, swizzle
;
317 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
319 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
320 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
321 func
, image
->offset
);
325 static struct intel_image_format
*
326 intel_image_format_lookup(int fourcc
)
328 struct intel_image_format
*f
= NULL
;
330 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
331 if (intel_image_formats
[i
].fourcc
== fourcc
) {
332 f
= &intel_image_formats
[i
];
340 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
342 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
343 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
344 *fourcc
= intel_image_formats
[i
].fourcc
;
352 intel_allocate_image(int dri_format
, void *loaderPrivate
)
356 image
= calloc(1, sizeof *image
);
360 image
->dri_format
= dri_format
;
363 image
->format
= driImageFormatToGLFormat(dri_format
);
364 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
365 image
->format
== MESA_FORMAT_NONE
) {
370 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
371 image
->data
= loaderPrivate
;
377 * Sets up a DRIImage structure to point to a slice out of a miptree.
380 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
381 struct intel_mipmap_tree
*mt
, GLuint level
,
384 intel_miptree_make_shareable(brw
, mt
);
386 intel_miptree_check_level_layer(mt
, level
, zoffset
);
388 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
389 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
390 image
->pitch
= mt
->pitch
;
392 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
396 drm_intel_bo_unreference(image
->bo
);
398 drm_intel_bo_reference(mt
->bo
);
402 intel_create_image_from_name(__DRIscreen
*dri_screen
,
403 int width
, int height
, int format
,
404 int name
, int pitch
, void *loaderPrivate
)
406 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
410 image
= intel_allocate_image(format
, loaderPrivate
);
414 if (image
->format
== MESA_FORMAT_NONE
)
417 cpp
= _mesa_get_format_bytes(image
->format
);
419 image
->width
= width
;
420 image
->height
= height
;
421 image
->pitch
= pitch
* cpp
;
422 image
->bo
= drm_intel_bo_gem_create_from_name(screen
->bufmgr
, "image",
433 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
434 int renderbuffer
, void *loaderPrivate
)
437 struct brw_context
*brw
= context
->driverPrivate
;
438 struct gl_context
*ctx
= &brw
->ctx
;
439 struct gl_renderbuffer
*rb
;
440 struct intel_renderbuffer
*irb
;
442 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
444 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
448 irb
= intel_renderbuffer(rb
);
449 intel_miptree_make_shareable(brw
, irb
->mt
);
450 image
= calloc(1, sizeof *image
);
454 image
->internal_format
= rb
->InternalFormat
;
455 image
->format
= rb
->Format
;
457 image
->data
= loaderPrivate
;
458 drm_intel_bo_unreference(image
->bo
);
459 image
->bo
= irb
->mt
->bo
;
460 drm_intel_bo_reference(irb
->mt
->bo
);
461 image
->width
= rb
->Width
;
462 image
->height
= rb
->Height
;
463 image
->pitch
= irb
->mt
->pitch
;
464 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
465 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
467 rb
->NeedsFinishRenderTexture
= true;
472 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
473 unsigned texture
, int zoffset
,
479 struct brw_context
*brw
= context
->driverPrivate
;
480 struct gl_texture_object
*obj
;
481 struct intel_texture_object
*iobj
;
484 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
485 if (!obj
|| obj
->Target
!= target
) {
486 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
490 if (target
== GL_TEXTURE_CUBE_MAP
)
493 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
494 iobj
= intel_texture_object(obj
);
495 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
496 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
500 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
501 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
505 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
506 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
509 image
= calloc(1, sizeof *image
);
511 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
515 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
516 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
517 image
->data
= loaderPrivate
;
518 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
519 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
520 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
521 if (image
->dri_format
== MESA_FORMAT_NONE
) {
522 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
527 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
532 intel_destroy_image(__DRIimage
*image
)
534 drm_intel_bo_unreference(image
->bo
);
539 intel_create_image(__DRIscreen
*dri_screen
,
540 int width
, int height
, int format
,
545 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
550 tiling
= I915_TILING_X
;
551 if (use
& __DRI_IMAGE_USE_CURSOR
) {
552 if (width
!= 64 || height
!= 64)
554 tiling
= I915_TILING_NONE
;
557 if (use
& __DRI_IMAGE_USE_LINEAR
)
558 tiling
= I915_TILING_NONE
;
560 image
= intel_allocate_image(format
, loaderPrivate
);
564 cpp
= _mesa_get_format_bytes(image
->format
);
565 image
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "image",
566 width
, height
, cpp
, &tiling
,
568 if (image
->bo
== NULL
) {
572 image
->width
= width
;
573 image
->height
= height
;
574 image
->pitch
= pitch
;
580 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
583 case __DRI_IMAGE_ATTRIB_STRIDE
:
584 *value
= image
->pitch
;
586 case __DRI_IMAGE_ATTRIB_HANDLE
:
587 *value
= image
->bo
->handle
;
589 case __DRI_IMAGE_ATTRIB_NAME
:
590 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
591 case __DRI_IMAGE_ATTRIB_FORMAT
:
592 *value
= image
->dri_format
;
594 case __DRI_IMAGE_ATTRIB_WIDTH
:
595 *value
= image
->width
;
597 case __DRI_IMAGE_ATTRIB_HEIGHT
:
598 *value
= image
->height
;
600 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
601 if (image
->planar_format
== NULL
)
603 *value
= image
->planar_format
->components
;
605 case __DRI_IMAGE_ATTRIB_FD
:
606 return !drm_intel_bo_gem_export_to_prime(image
->bo
, value
);
607 case __DRI_IMAGE_ATTRIB_FOURCC
:
608 return intel_lookup_fourcc(image
->dri_format
, value
);
609 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
612 case __DRI_IMAGE_ATTRIB_OFFSET
:
613 *value
= image
->offset
;
622 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
626 image
= calloc(1, sizeof *image
);
630 drm_intel_bo_reference(orig_image
->bo
);
631 image
->bo
= orig_image
->bo
;
632 image
->internal_format
= orig_image
->internal_format
;
633 image
->planar_format
= orig_image
->planar_format
;
634 image
->dri_format
= orig_image
->dri_format
;
635 image
->format
= orig_image
->format
;
636 image
->offset
= orig_image
->offset
;
637 image
->width
= orig_image
->width
;
638 image
->height
= orig_image
->height
;
639 image
->pitch
= orig_image
->pitch
;
640 image
->tile_x
= orig_image
->tile_x
;
641 image
->tile_y
= orig_image
->tile_y
;
642 image
->has_depthstencil
= orig_image
->has_depthstencil
;
643 image
->data
= loaderPrivate
;
645 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
646 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
652 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
654 if (use
& __DRI_IMAGE_USE_CURSOR
) {
655 if (image
->width
!= 64 || image
->height
!= 64)
663 intel_create_image_from_names(__DRIscreen
*dri_screen
,
664 int width
, int height
, int fourcc
,
665 int *names
, int num_names
,
666 int *strides
, int *offsets
,
669 struct intel_image_format
*f
= NULL
;
673 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
676 f
= intel_image_format_lookup(fourcc
);
680 image
= intel_create_image_from_name(dri_screen
, width
, height
,
681 __DRI_IMAGE_FORMAT_NONE
,
682 names
[0], strides
[0],
688 image
->planar_format
= f
;
689 for (i
= 0; i
< f
->nplanes
; i
++) {
690 index
= f
->planes
[i
].buffer_index
;
691 image
->offsets
[index
] = offsets
[index
];
692 image
->strides
[index
] = strides
[index
];
699 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
700 int width
, int height
, int fourcc
,
701 int *fds
, int num_fds
, int *strides
, int *offsets
,
704 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
705 struct intel_image_format
*f
;
709 if (fds
== NULL
|| num_fds
< 1)
712 /* We only support all planes from the same bo */
713 for (i
= 0; i
< num_fds
; i
++)
714 if (fds
[0] != fds
[i
])
717 f
= intel_image_format_lookup(fourcc
);
722 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
724 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
729 image
->width
= width
;
730 image
->height
= height
;
731 image
->pitch
= strides
[0];
733 image
->planar_format
= f
;
735 for (i
= 0; i
< f
->nplanes
; i
++) {
736 index
= f
->planes
[i
].buffer_index
;
737 image
->offsets
[index
] = offsets
[index
];
738 image
->strides
[index
] = strides
[index
];
740 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
741 const int end
= offsets
[index
] + plane_height
* strides
[index
];
746 image
->bo
= drm_intel_bo_gem_create_from_prime(screen
->bufmgr
,
748 if (image
->bo
== NULL
) {
753 if (f
->nplanes
== 1) {
754 image
->offset
= image
->offsets
[0];
755 intel_image_warn_if_unaligned(image
, __func__
);
762 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
763 int width
, int height
, int fourcc
,
764 int *fds
, int num_fds
,
765 int *strides
, int *offsets
,
766 enum __DRIYUVColorSpace yuv_color_space
,
767 enum __DRISampleRange sample_range
,
768 enum __DRIChromaSiting horizontal_siting
,
769 enum __DRIChromaSiting vertical_siting
,
774 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
777 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
781 image
= intel_create_image_from_fds(dri_screen
, width
, height
, fourcc
, fds
,
782 num_fds
, strides
, offsets
,
786 * Invalid parameters and any inconsistencies between are assumed to be
787 * checked by the caller. Therefore besides unsupported formats one can fail
788 * only in allocation.
791 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
795 image
->dma_buf_imported
= true;
796 image
->yuv_color_space
= yuv_color_space
;
797 image
->sample_range
= sample_range
;
798 image
->horizontal_siting
= horizontal_siting
;
799 image
->vertical_siting
= vertical_siting
;
801 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
806 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
808 int width
, height
, offset
, stride
, dri_format
, index
;
809 struct intel_image_format
*f
;
812 if (parent
== NULL
|| parent
->planar_format
== NULL
)
815 f
= parent
->planar_format
;
817 if (plane
>= f
->nplanes
)
820 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
821 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
822 dri_format
= f
->planes
[plane
].dri_format
;
823 index
= f
->planes
[plane
].buffer_index
;
824 offset
= parent
->offsets
[index
];
825 stride
= parent
->strides
[index
];
827 image
= intel_allocate_image(dri_format
, loaderPrivate
);
831 if (offset
+ height
* stride
> parent
->bo
->size
) {
832 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
837 image
->bo
= parent
->bo
;
838 drm_intel_bo_reference(parent
->bo
);
840 image
->width
= width
;
841 image
->height
= height
;
842 image
->pitch
= stride
;
843 image
->offset
= offset
;
845 intel_image_warn_if_unaligned(image
, __func__
);
850 static const __DRIimageExtension intelImageExtension
= {
851 .base
= { __DRI_IMAGE
, 13 },
853 .createImageFromName
= intel_create_image_from_name
,
854 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
855 .destroyImage
= intel_destroy_image
,
856 .createImage
= intel_create_image
,
857 .queryImage
= intel_query_image
,
858 .dupImage
= intel_dup_image
,
859 .validateUsage
= intel_validate_usage
,
860 .createImageFromNames
= intel_create_image_from_names
,
861 .fromPlanar
= intel_from_planar
,
862 .createImageFromTexture
= intel_create_image_from_texture
,
863 .createImageFromFds
= intel_create_image_from_fds
,
864 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
866 .getCapabilities
= NULL
,
872 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
873 int param
, unsigned int *value
)
875 const struct intel_screen
*const screen
=
876 (struct intel_screen
*) dri_screen
->driverPrivate
;
879 case __DRI2_RENDERER_VENDOR_ID
:
882 case __DRI2_RENDERER_DEVICE_ID
:
883 value
[0] = screen
->deviceID
;
885 case __DRI2_RENDERER_ACCELERATED
:
888 case __DRI2_RENDERER_VIDEO_MEMORY
: {
889 /* Once a batch uses more than 75% of the maximum mappable size, we
890 * assume that there's some fragmentation, and we start doing extra
891 * flushing, etc. That's the big cliff apps will care about.
894 size_t mappable_size
;
896 drm_intel_get_aperture_sizes(dri_screen
->fd
, &mappable_size
, &aper_size
);
898 const unsigned gpu_mappable_megabytes
=
899 (aper_size
/ (1024 * 1024)) * 3 / 4;
901 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
902 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
904 if (system_memory_pages
<= 0 || system_page_size
<= 0)
907 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
908 * (uint64_t) system_page_size
;
910 const unsigned system_memory_megabytes
=
911 (unsigned) (system_memory_bytes
/ (1024 * 1024));
913 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
916 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
920 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
927 brw_query_renderer_string(__DRIscreen
*dri_screen
,
928 int param
, const char **value
)
930 const struct intel_screen
*screen
=
931 (struct intel_screen
*) dri_screen
->driverPrivate
;
934 case __DRI2_RENDERER_VENDOR_ID
:
935 value
[0] = brw_vendor_string
;
937 case __DRI2_RENDERER_DEVICE_ID
:
938 value
[0] = brw_get_renderer_string(screen
);
947 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
948 .base
= { __DRI2_RENDERER_QUERY
, 1 },
950 .queryInteger
= brw_query_renderer_integer
,
951 .queryString
= brw_query_renderer_string
954 static const __DRIrobustnessExtension dri2Robustness
= {
955 .base
= { __DRI2_ROBUSTNESS
, 1 }
958 static const __DRIextension
*screenExtensions
[] = {
959 &intelTexBufferExtension
.base
,
960 &intelFenceExtension
.base
,
961 &intelFlushExtension
.base
,
962 &intelImageExtension
.base
,
963 &intelRendererQueryExtension
.base
,
964 &dri2ConfigQueryExtension
.base
,
968 static const __DRIextension
*intelRobustScreenExtensions
[] = {
969 &intelTexBufferExtension
.base
,
970 &intelFenceExtension
.base
,
971 &intelFlushExtension
.base
,
972 &intelImageExtension
.base
,
973 &intelRendererQueryExtension
.base
,
974 &dri2ConfigQueryExtension
.base
,
975 &dri2Robustness
.base
,
980 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
983 struct drm_i915_getparam gp
;
985 memset(&gp
, 0, sizeof(gp
));
989 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
992 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
999 intel_get_boolean(struct intel_screen
*screen
, int param
)
1002 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1006 intel_get_integer(struct intel_screen
*screen
, int param
)
1010 if (intel_get_param(screen
, param
, &value
) == 0)
1017 intelDestroyScreen(__DRIscreen
* sPriv
)
1019 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1021 dri_bufmgr_destroy(screen
->bufmgr
);
1022 driDestroyOptionInfo(&screen
->optionCache
);
1024 ralloc_free(screen
);
1025 sPriv
->driverPrivate
= NULL
;
1030 * This is called when we need to set up GL rendering to a new X window.
1033 intelCreateBuffer(__DRIscreen
*dri_screen
,
1034 __DRIdrawable
* driDrawPriv
,
1035 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1037 struct intel_renderbuffer
*rb
;
1038 struct intel_screen
*screen
= (struct intel_screen
*)
1039 dri_screen
->driverPrivate
;
1040 mesa_format rgbFormat
;
1041 unsigned num_samples
=
1042 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1043 struct gl_framebuffer
*fb
;
1048 fb
= CALLOC_STRUCT(gl_framebuffer
);
1052 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1054 if (screen
->winsys_msaa_samples_override
!= -1) {
1055 num_samples
= screen
->winsys_msaa_samples_override
;
1056 fb
->Visual
.samples
= num_samples
;
1059 if (mesaVis
->redBits
== 5) {
1060 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1061 : MESA_FORMAT_B5G6R5_UNORM
;
1062 } else if (mesaVis
->sRGBCapable
) {
1063 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1064 : MESA_FORMAT_B8G8R8A8_SRGB
;
1065 } else if (mesaVis
->alphaBits
== 0) {
1066 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1067 : MESA_FORMAT_B8G8R8X8_UNORM
;
1069 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1070 : MESA_FORMAT_B8G8R8A8_SRGB
;
1071 fb
->Visual
.sRGBCapable
= true;
1074 /* setup the hardware-based renderbuffers */
1075 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1076 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1078 if (mesaVis
->doubleBufferMode
) {
1079 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1080 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1084 * Assert here that the gl_config has an expected depth/stencil bit
1085 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1086 * which constructs the advertised configs.)
1088 if (mesaVis
->depthBits
== 24) {
1089 assert(mesaVis
->stencilBits
== 8);
1091 if (screen
->devinfo
->has_hiz_and_separate_stencil
) {
1092 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1094 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1095 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1097 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1100 * Use combined depth/stencil. Note that the renderbuffer is
1101 * attached to two attachment points.
1103 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1105 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1106 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1109 else if (mesaVis
->depthBits
== 16) {
1110 assert(mesaVis
->stencilBits
== 0);
1111 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1113 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1116 assert(mesaVis
->depthBits
== 0);
1117 assert(mesaVis
->stencilBits
== 0);
1120 /* now add any/all software-based renderbuffers we may need */
1121 _swrast_add_soft_renderbuffers(fb
,
1122 false, /* never sw color */
1123 false, /* never sw depth */
1124 false, /* never sw stencil */
1125 mesaVis
->accumRedBits
> 0,
1126 false, /* never sw alpha */
1127 false /* never sw aux */ );
1128 driDrawPriv
->driverPrivate
= fb
;
1134 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1136 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1138 _mesa_reference_framebuffer(&fb
, NULL
);
1142 intel_detect_sseu(struct intel_screen
*screen
)
1144 assert(screen
->devinfo
->gen
>= 8);
1147 screen
->subslice_total
= -1;
1148 screen
->eu_total
= -1;
1150 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1151 &screen
->subslice_total
);
1152 if (ret
< 0 && ret
!= -EINVAL
)
1155 ret
= intel_get_param(screen
,
1156 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1157 if (ret
< 0 && ret
!= -EINVAL
)
1160 /* Without this information, we cannot get the right Braswell brandstrings,
1161 * and we have to use conservative numbers for GPGPU on many platforms, but
1162 * otherwise, things will just work.
1164 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1166 "Kernel 4.1 required to properly query GPU properties.\n");
1171 screen
->subslice_total
= -1;
1172 screen
->eu_total
= -1;
1173 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1177 intel_init_bufmgr(struct intel_screen
*screen
)
1179 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1181 screen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1183 screen
->bufmgr
= intel_bufmgr_gem_init(dri_screen
->fd
, BATCH_SZ
);
1184 if (screen
->bufmgr
== NULL
) {
1185 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1186 __func__
, __LINE__
);
1190 drm_intel_bufmgr_gem_enable_fenced_relocs(screen
->bufmgr
);
1192 if (!intel_get_boolean(screen
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1193 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1201 intel_detect_swizzling(struct intel_screen
*screen
)
1203 drm_intel_bo
*buffer
;
1204 unsigned long flags
= 0;
1205 unsigned long aligned_pitch
;
1206 uint32_t tiling
= I915_TILING_X
;
1207 uint32_t swizzle_mode
= 0;
1209 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1211 &tiling
, &aligned_pitch
, flags
);
1215 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1216 drm_intel_bo_unreference(buffer
);
1218 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1225 intel_detect_timestamp(struct intel_screen
*screen
)
1227 uint64_t dummy
= 0, last
= 0;
1228 int upper
, lower
, loops
;
1230 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1231 * TIMESTAMP register being shifted and the low 32bits always zero.
1233 * More recent kernels offer an interface to read the full 36bits
1236 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1239 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1240 * upper 32bits for a rapidly changing timestamp.
1242 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1246 for (loops
= 0; loops
< 10; loops
++) {
1247 /* The TIMESTAMP should change every 80ns, so several round trips
1248 * through the kernel should be enough to advance it.
1250 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1253 upper
+= (dummy
>> 32) != (last
>> 32);
1254 if (upper
> 1) /* beware 32bit counter overflow */
1255 return 2; /* upper dword holds the low 32bits of the timestamp */
1257 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1259 return 1; /* timestamp is unshifted */
1264 /* No advancement? No timestamp! */
1269 * Return array of MSAA modes supported by the hardware. The array is
1270 * zero-terminated and sorted in decreasing order.
1273 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1275 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1276 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1277 static const int gen7_modes
[] = {8, 4, 0, -1};
1278 static const int gen6_modes
[] = {4, 0, -1};
1279 static const int gen4_modes
[] = {0, -1};
1281 if (screen
->devinfo
->gen
>= 9) {
1283 } else if (screen
->devinfo
->gen
>= 8) {
1285 } else if (screen
->devinfo
->gen
>= 7) {
1287 } else if (screen
->devinfo
->gen
== 6) {
1294 static __DRIconfig
**
1295 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1297 static const mesa_format formats
[] = {
1298 MESA_FORMAT_B5G6R5_UNORM
,
1299 MESA_FORMAT_B8G8R8A8_UNORM
,
1300 MESA_FORMAT_B8G8R8X8_UNORM
1303 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1304 static const GLenum back_buffer_modes
[] = {
1305 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1308 static const uint8_t singlesample_samples
[1] = {0};
1309 static const uint8_t multisample_samples
[2] = {4, 8};
1311 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1312 const struct gen_device_info
*devinfo
= screen
->devinfo
;
1313 uint8_t depth_bits
[4], stencil_bits
[4];
1314 __DRIconfig
**configs
= NULL
;
1316 /* Generate singlesample configs without accumulation buffer. */
1317 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1318 __DRIconfig
**new_configs
;
1319 int num_depth_stencil_bits
= 2;
1321 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1322 * buffer that has a different number of bits per pixel than the color
1323 * buffer, gen >= 6 supports this.
1326 stencil_bits
[0] = 0;
1328 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1330 stencil_bits
[1] = 0;
1331 if (devinfo
->gen
>= 6) {
1333 stencil_bits
[2] = 8;
1334 num_depth_stencil_bits
= 3;
1338 stencil_bits
[1] = 8;
1341 new_configs
= driCreateConfigs(formats
[i
],
1344 num_depth_stencil_bits
,
1345 back_buffer_modes
, 2,
1346 singlesample_samples
, 1,
1348 configs
= driConcatConfigs(configs
, new_configs
);
1351 /* Generate the minimum possible set of configs that include an
1352 * accumulation buffer.
1354 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1355 __DRIconfig
**new_configs
;
1357 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1359 stencil_bits
[0] = 0;
1362 stencil_bits
[0] = 8;
1365 new_configs
= driCreateConfigs(formats
[i
],
1366 depth_bits
, stencil_bits
, 1,
1367 back_buffer_modes
, 1,
1368 singlesample_samples
, 1,
1370 configs
= driConcatConfigs(configs
, new_configs
);
1373 /* Generate multisample configs.
1375 * This loop breaks early, and hence is a no-op, on gen < 6.
1377 * Multisample configs must follow the singlesample configs in order to
1378 * work around an X server bug present in 1.12. The X server chooses to
1379 * associate the first listed RGBA888-Z24S8 config, regardless of its
1380 * sample count, with the 32-bit depth visual used for compositing.
1382 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1383 * supported. Singlebuffer configs are not supported because no one wants
1386 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1387 if (devinfo
->gen
< 6)
1390 __DRIconfig
**new_configs
;
1391 const int num_depth_stencil_bits
= 2;
1392 int num_msaa_modes
= 0;
1395 stencil_bits
[0] = 0;
1397 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1399 stencil_bits
[1] = 0;
1402 stencil_bits
[1] = 8;
1405 if (devinfo
->gen
>= 7)
1407 else if (devinfo
->gen
== 6)
1410 new_configs
= driCreateConfigs(formats
[i
],
1413 num_depth_stencil_bits
,
1414 back_buffer_modes
, 1,
1415 multisample_samples
,
1418 configs
= driConcatConfigs(configs
, new_configs
);
1421 if (configs
== NULL
) {
1422 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1431 set_max_gl_versions(struct intel_screen
*screen
)
1433 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1434 const bool has_astc
= screen
->devinfo
->gen
>= 9;
1436 switch (screen
->devinfo
->gen
) {
1439 dri_screen
->max_gl_core_version
= 44;
1440 dri_screen
->max_gl_compat_version
= 30;
1441 dri_screen
->max_gl_es1_version
= 11;
1442 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1445 dri_screen
->max_gl_core_version
= 33;
1446 dri_screen
->max_gl_compat_version
= 30;
1447 dri_screen
->max_gl_es1_version
= 11;
1448 dri_screen
->max_gl_es2_version
= screen
->devinfo
->is_haswell
? 31 : 30;
1451 dri_screen
->max_gl_core_version
= 33;
1452 dri_screen
->max_gl_compat_version
= 30;
1453 dri_screen
->max_gl_es1_version
= 11;
1454 dri_screen
->max_gl_es2_version
= 30;
1458 dri_screen
->max_gl_core_version
= 0;
1459 dri_screen
->max_gl_compat_version
= 21;
1460 dri_screen
->max_gl_es1_version
= 11;
1461 dri_screen
->max_gl_es2_version
= 20;
1464 unreachable("unrecognized intel_screen::gen");
1469 * Return the revision (generally the revid field of the PCI header) of the
1472 * XXX: This function is useful to keep around even if it is not currently in
1473 * use. It is necessary for new platforms and revision specific workarounds or
1474 * features. Please don't remove it so that we know it at least continues to
1477 static __attribute__((__unused__
)) int
1478 brw_get_revision(int fd
)
1480 struct drm_i915_getparam gp
;
1484 memset(&gp
, 0, sizeof(gp
));
1485 gp
.param
= I915_PARAM_REVISION
;
1486 gp
.value
= &revision
;
1488 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1495 /* Drop when RS headers get pulled to libdrm */
1496 #ifndef I915_PARAM_HAS_RESOURCE_STREAMER
1497 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
1501 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1503 struct brw_context
*brw
= (struct brw_context
*)data
;
1506 va_start(args
, fmt
);
1508 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1509 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1510 MESA_DEBUG_TYPE_OTHER
,
1511 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1516 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1518 struct brw_context
*brw
= (struct brw_context
*)data
;
1521 va_start(args
, fmt
);
1523 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1525 va_copy(args_copy
, args
);
1526 vfprintf(stderr
, fmt
, args_copy
);
1530 if (brw
->perf_debug
) {
1532 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1533 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1534 MESA_DEBUG_TYPE_PERFORMANCE
,
1535 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1541 * This is the driver specific part of the createNewScreen entry point.
1542 * Called when using DRI2.
1544 * \return the struct gl_config supported by this driver
1547 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
1549 struct intel_screen
*screen
;
1551 if (dri_screen
->image
.loader
) {
1552 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
1553 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1555 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1556 "support required\n");
1560 /* Allocate the private area */
1561 screen
= rzalloc(NULL
, struct intel_screen
);
1563 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1566 /* parse information in __driConfigOptions */
1567 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
1569 screen
->driScrnPriv
= dri_screen
;
1570 dri_screen
->driverPrivate
= (void *) screen
;
1572 if (!intel_init_bufmgr(screen
))
1575 screen
->deviceID
= drm_intel_bufmgr_gem_get_devid(screen
->bufmgr
);
1576 screen
->devinfo
= gen_get_device_info(screen
->deviceID
);
1577 if (!screen
->devinfo
)
1580 brw_process_intel_debug_variable();
1582 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1583 dri_bufmgr_set_debug(screen
->bufmgr
, true);
1585 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && screen
->devinfo
->gen
< 7) {
1587 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1588 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1591 if (INTEL_DEBUG
& DEBUG_AUB
)
1592 drm_intel_bufmgr_gem_set_aub_dump(screen
->bufmgr
, true);
1594 #ifndef I915_PARAM_MMAP_GTT_VERSION
1595 #define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */
1597 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1598 /* Theorectically unlimited! At least for individual objects...
1600 * Currently the entire (global) address space for all GTT maps is
1601 * limited to 64bits. That is all objects on the system that are
1602 * setup for GTT mmapping must fit within 64bits. An attempt to use
1603 * one that exceeds the limit with fail in drm_intel_bo_map_gtt().
1605 * Long before we hit that limit, we will be practically limited by
1606 * that any single object must fit in physical memory (RAM). The upper
1607 * limit on the CPU's address space is currently 48bits (Skylake), of
1608 * which only 39bits can be physical memory. (The GPU itself also has
1609 * a 48bit addressable virtual space.) We can fit over 32 million
1610 * objects of the current maximum allocable size before running out
1613 screen
->max_gtt_map_object_size
= UINT64_MAX
;
1615 /* Estimate the size of the mappable aperture into the GTT. There's an
1616 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1617 * It turns out it's basically always 256MB, though some ancient hardware
1620 uint32_t gtt_size
= 256 * 1024 * 1024;
1622 /* We don't want to map two objects such that a memcpy between them would
1623 * just fault one mapping in and then the other over and over forever. So
1624 * we would need to divide the GTT size by 2. Additionally, some GTT is
1625 * taken up by things like the framebuffer and the ringbuffer and such, so
1626 * be more conservative.
1628 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
1631 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
1632 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
1634 /* GENs prior to 8 do not support EU/Subslice info */
1635 if (screen
->devinfo
->gen
>= 8) {
1636 intel_detect_sseu(screen
);
1637 } else if (screen
->devinfo
->gen
== 7) {
1638 screen
->subslice_total
= 1 << (screen
->devinfo
->gt
- 1);
1641 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1643 screen
->winsys_msaa_samples_override
=
1644 intel_quantize_num_samples(screen
, atoi(force_msaa
));
1645 printf("Forcing winsys sample count to %d\n",
1646 screen
->winsys_msaa_samples_override
);
1648 screen
->winsys_msaa_samples_override
= -1;
1651 set_max_gl_versions(screen
);
1653 /* Notification of GPU resets requires hardware contexts and a kernel new
1654 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1655 * supported, calling it with a context of 0 will either generate EPERM or
1656 * no error. If the ioctl is not supported, it always generate EINVAL.
1657 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1658 * extension to the loader.
1660 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1662 if (screen
->devinfo
->gen
>= 6) {
1663 struct drm_i915_reset_stats stats
;
1664 memset(&stats
, 0, sizeof(stats
));
1666 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1668 screen
->has_context_reset_notification
=
1669 (ret
!= -1 || errno
!= EINVAL
);
1672 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
1673 &screen
->cmd_parser_version
) < 0) {
1674 screen
->cmd_parser_version
= 0;
1677 /* Haswell requires command parser version 6 in order to write to the
1678 * MI_MATH GPR registers, and version 7 in order to use
1679 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
1681 screen
->has_mi_math_and_lrr
= screen
->devinfo
->gen
>= 8 ||
1682 (screen
->devinfo
->is_haswell
&&
1683 screen
->cmd_parser_version
>= 7);
1685 dri_screen
->extensions
= !screen
->has_context_reset_notification
1686 ? screenExtensions
: intelRobustScreenExtensions
;
1688 screen
->compiler
= brw_compiler_create(screen
,
1690 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
1691 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
1692 screen
->program_id
= 1;
1694 if (screen
->devinfo
->has_resource_streamer
) {
1695 screen
->has_resource_streamer
=
1696 intel_get_boolean(screen
, I915_PARAM_HAS_RESOURCE_STREAMER
);
1699 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
1702 struct intel_buffer
{
1707 static __DRIbuffer
*
1708 intelAllocateBuffer(__DRIscreen
*dri_screen
,
1709 unsigned attachment
, unsigned format
,
1710 int width
, int height
)
1712 struct intel_buffer
*intelBuffer
;
1713 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1715 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1716 attachment
== __DRI_BUFFER_BACK_LEFT
);
1718 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1719 if (intelBuffer
== NULL
)
1722 /* The front and back buffers are color buffers, which are X tiled. */
1723 uint32_t tiling
= I915_TILING_X
;
1724 unsigned long pitch
;
1725 int cpp
= format
/ 8;
1726 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
,
1727 "intelAllocateBuffer",
1732 BO_ALLOC_FOR_RENDER
);
1734 if (intelBuffer
->bo
== NULL
) {
1739 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1741 intelBuffer
->base
.attachment
= attachment
;
1742 intelBuffer
->base
.cpp
= cpp
;
1743 intelBuffer
->base
.pitch
= pitch
;
1745 return &intelBuffer
->base
;
1749 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
1751 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1753 drm_intel_bo_unreference(intelBuffer
->bo
);
1757 static const struct __DriverAPIRec brw_driver_api
= {
1758 .InitScreen
= intelInitScreen2
,
1759 .DestroyScreen
= intelDestroyScreen
,
1760 .CreateContext
= brwCreateContext
,
1761 .DestroyContext
= intelDestroyContext
,
1762 .CreateBuffer
= intelCreateBuffer
,
1763 .DestroyBuffer
= intelDestroyBuffer
,
1764 .MakeCurrent
= intelMakeCurrent
,
1765 .UnbindContext
= intelUnbindContext
,
1766 .AllocateBuffer
= intelAllocateBuffer
,
1767 .ReleaseBuffer
= intelReleaseBuffer
1770 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1771 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1772 .vtable
= &brw_driver_api
,
1775 static const __DRIextension
*brw_driver_extensions
[] = {
1776 &driCoreExtension
.base
,
1777 &driImageDriverExtension
.base
,
1778 &driDRI2Extension
.base
,
1780 &brw_config_options
.base
,
1784 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1786 globalDriverAPI
= &brw_driver_api
;
1788 return brw_driver_extensions
;