2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "util/disk_cache.h"
40 #include "brw_defines.h"
41 #include "brw_state.h"
42 #include "compiler/nir/nir.h"
45 #include "util/disk_cache.h"
46 #include "util/xmlpool.h"
48 static const __DRIconfigOptionsExtension brw_config_options
= {
49 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
52 DRI_CONF_SECTION_PERFORMANCE
53 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
54 * DRI_CONF_BO_REUSE_ALL
56 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
57 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
58 DRI_CONF_ENUM(0, "Disable buffer object reuse")
59 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
62 DRI_CONF_MESA_NO_ERROR("false")
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_PRECISE_TRIG("false")
68 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
69 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
70 "given integer. If negative, then do not clamp.")
74 DRI_CONF_SECTION_DEBUG
75 DRI_CONF_NO_RAST("false")
76 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
77 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
78 DRI_CONF_DISABLE_THROTTLING("false")
79 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
80 DRI_CONF_FORCE_GLSL_VERSION(0)
81 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
82 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
83 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
84 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
85 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
86 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
87 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
88 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
90 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
91 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
95 DRI_CONF_SECTION_MISCELLANEOUS
96 DRI_CONF_GLSL_ZERO_INIT("false")
97 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
102 #include "intel_batchbuffer.h"
103 #include "intel_buffers.h"
104 #include "brw_bufmgr.h"
105 #include "intel_fbo.h"
106 #include "intel_mipmap_tree.h"
107 #include "intel_screen.h"
108 #include "intel_tex.h"
109 #include "intel_image.h"
111 #include "brw_context.h"
113 #include "i915_drm.h"
116 * For debugging purposes, this returns a time in seconds.
123 clock_gettime(CLOCK_MONOTONIC
, &tp
);
125 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
128 static const __DRItexBufferExtension intelTexBufferExtension
= {
129 .base
= { __DRI_TEX_BUFFER
, 3 },
131 .setTexBuffer
= intelSetTexBuffer
,
132 .setTexBuffer2
= intelSetTexBuffer2
,
133 .releaseTexBuffer
= NULL
,
137 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
138 __DRIdrawable
*dPriv
,
140 enum __DRI2throttleReason reason
)
142 struct brw_context
*brw
= cPriv
->driverPrivate
;
147 struct gl_context
*ctx
= &brw
->ctx
;
149 FLUSH_VERTICES(ctx
, 0);
151 if (flags
& __DRI2_FLUSH_DRAWABLE
)
152 intel_resolve_for_dri2_flush(brw
, dPriv
);
154 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
155 brw
->need_swap_throttle
= true;
156 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
157 brw
->need_flush_throttle
= true;
159 intel_batchbuffer_flush(brw
);
163 * Provides compatibility with loaders that only support the older (version
164 * 1-3) flush interface.
166 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
169 intel_dri2_flush(__DRIdrawable
*drawable
)
171 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
172 __DRI2_FLUSH_DRAWABLE
,
173 __DRI2_THROTTLE_SWAPBUFFER
);
176 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
177 .base
= { __DRI2_FLUSH
, 4 },
179 .flush
= intel_dri2_flush
,
180 .invalidate
= dri2InvalidateDrawable
,
181 .flush_with_flags
= intel_dri2_flush_with_flags
,
184 static const struct intel_image_format intel_image_formats
[] = {
185 { __DRI_IMAGE_FOURCC_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
186 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
188 { __DRI_IMAGE_FOURCC_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
189 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
191 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
192 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
194 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
195 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
197 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
198 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
200 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
201 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
203 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
204 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
206 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
207 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
209 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
210 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
212 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
215 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
218 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
221 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
224 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
226 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
227 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
229 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
230 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
231 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
232 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
234 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
236 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
237 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
239 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
241 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
242 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
244 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
245 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
246 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
247 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
249 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
250 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
254 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
255 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
259 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
260 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
264 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
265 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
269 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
270 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
271 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
274 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
275 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
276 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
278 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
279 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
280 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
282 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
283 * and treat them as planar buffers in the compositors.
284 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
285 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
286 * clusters and places pairs and places U into the G component and
287 * V into A. This lets the texture sampler interpolate the Y
288 * components correctly when sampling from plane 0, and interpolate
289 * U and V correctly when sampling from plane 1. */
290 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
291 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
292 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
293 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
294 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
295 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
298 static const struct {
301 } supported_modifiers
[] = {
302 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
303 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
304 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
305 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
309 modifier_is_supported(const struct gen_device_info
*devinfo
,
310 const struct intel_image_format
*fmt
, int dri_format
,
313 const struct isl_drm_modifier_info
*modinfo
=
314 isl_drm_modifier_get_info(modifier
);
317 /* ISL had better know about the modifier */
321 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
322 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
323 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
326 /* CCS_E is not supported for planar images */
327 if (fmt
&& fmt
->nplanes
> 1)
331 assert(dri_format
== 0);
332 dri_format
= fmt
->planes
[0].dri_format
;
335 mesa_format format
= driImageFormatToGLFormat(dri_format
);
336 format
= _mesa_get_srgb_format_linear(format
);
337 if (!isl_format_supports_ccs_e(devinfo
,
338 brw_isl_format_for_mesa_format(format
)))
342 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
343 if (supported_modifiers
[i
].modifier
!= modifier
)
346 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
353 tiling_to_modifier(uint32_t tiling
)
355 static const uint64_t map
[] = {
356 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
357 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
358 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
361 assert(tiling
< ARRAY_SIZE(map
));
367 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
369 uint32_t tiling
, swizzle
;
370 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
372 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
373 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
374 func
, image
->offset
);
378 static const struct intel_image_format
*
379 intel_image_format_lookup(int fourcc
)
381 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
382 if (intel_image_formats
[i
].fourcc
== fourcc
)
383 return &intel_image_formats
[i
];
389 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
391 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
392 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
393 *fourcc
= intel_image_formats
[i
].fourcc
;
401 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
406 image
= calloc(1, sizeof *image
);
410 image
->screen
= screen
;
411 image
->dri_format
= dri_format
;
414 image
->format
= driImageFormatToGLFormat(dri_format
);
415 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
416 image
->format
== MESA_FORMAT_NONE
) {
421 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
422 image
->data
= loaderPrivate
;
428 * Sets up a DRIImage structure to point to a slice out of a miptree.
431 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
432 struct intel_mipmap_tree
*mt
, GLuint level
,
435 intel_miptree_make_shareable(brw
, mt
);
437 intel_miptree_check_level_layer(mt
, level
, zoffset
);
439 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
440 level
- mt
->first_level
);
441 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
442 level
- mt
->first_level
);
443 image
->pitch
= mt
->surf
.row_pitch
;
445 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
449 brw_bo_unreference(image
->bo
);
451 brw_bo_reference(mt
->bo
);
455 intel_create_image_from_name(__DRIscreen
*dri_screen
,
456 int width
, int height
, int format
,
457 int name
, int pitch
, void *loaderPrivate
)
459 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
463 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
467 if (image
->format
== MESA_FORMAT_NONE
)
470 cpp
= _mesa_get_format_bytes(image
->format
);
472 image
->width
= width
;
473 image
->height
= height
;
474 image
->pitch
= pitch
* cpp
;
475 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
481 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
487 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
488 int renderbuffer
, void *loaderPrivate
)
491 struct brw_context
*brw
= context
->driverPrivate
;
492 struct gl_context
*ctx
= &brw
->ctx
;
493 struct gl_renderbuffer
*rb
;
494 struct intel_renderbuffer
*irb
;
496 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
498 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
502 irb
= intel_renderbuffer(rb
);
503 intel_miptree_make_shareable(brw
, irb
->mt
);
504 image
= calloc(1, sizeof *image
);
508 image
->internal_format
= rb
->InternalFormat
;
509 image
->format
= rb
->Format
;
510 image
->modifier
= tiling_to_modifier(
511 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
513 image
->data
= loaderPrivate
;
514 brw_bo_unreference(image
->bo
);
515 image
->bo
= irb
->mt
->bo
;
516 brw_bo_reference(irb
->mt
->bo
);
517 image
->width
= rb
->Width
;
518 image
->height
= rb
->Height
;
519 image
->pitch
= irb
->mt
->surf
.row_pitch
;
520 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
521 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
523 rb
->NeedsFinishRenderTexture
= true;
528 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
529 unsigned texture
, int zoffset
,
535 struct brw_context
*brw
= context
->driverPrivate
;
536 struct gl_texture_object
*obj
;
537 struct intel_texture_object
*iobj
;
540 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
541 if (!obj
|| obj
->Target
!= target
) {
542 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
546 if (target
== GL_TEXTURE_CUBE_MAP
)
549 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
550 iobj
= intel_texture_object(obj
);
551 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
552 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
556 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
557 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
561 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
562 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
565 image
= calloc(1, sizeof *image
);
567 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
571 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
572 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
573 image
->modifier
= tiling_to_modifier(
574 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
575 image
->data
= loaderPrivate
;
576 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
577 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
578 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
579 if (image
->dri_format
== MESA_FORMAT_NONE
) {
580 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
585 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
590 intel_destroy_image(__DRIimage
*image
)
592 brw_bo_unreference(image
->bo
);
596 enum modifier_priority
{
597 MODIFIER_PRIORITY_INVALID
= 0,
598 MODIFIER_PRIORITY_LINEAR
,
601 MODIFIER_PRIORITY_Y_CCS
,
604 const uint64_t priority_to_modifier
[] = {
605 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
606 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
607 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
608 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
609 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
613 select_best_modifier(struct gen_device_info
*devinfo
,
615 const uint64_t *modifiers
,
616 const unsigned count
)
618 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
620 for (int i
= 0; i
< count
; i
++) {
621 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
624 switch (modifiers
[i
]) {
625 case I915_FORMAT_MOD_Y_TILED_CCS
:
626 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
628 case I915_FORMAT_MOD_Y_TILED
:
629 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
631 case I915_FORMAT_MOD_X_TILED
:
632 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
634 case DRM_FORMAT_MOD_LINEAR
:
635 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
637 case DRM_FORMAT_MOD_INVALID
:
643 return priority_to_modifier
[prio
];
647 intel_create_image_common(__DRIscreen
*dri_screen
,
648 int width
, int height
, int format
,
650 const uint64_t *modifiers
,
655 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
656 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
659 /* Callers of this may specify a modifier, or a dri usage, but not both. The
660 * newer modifier interface deprecates the older usage flags newer modifier
661 * interface deprecates the older usage flags.
663 assert(!(use
&& count
));
665 if (use
& __DRI_IMAGE_USE_CURSOR
) {
666 if (width
!= 64 || height
!= 64)
668 modifier
= DRM_FORMAT_MOD_LINEAR
;
671 if (use
& __DRI_IMAGE_USE_LINEAR
)
672 modifier
= DRM_FORMAT_MOD_LINEAR
;
674 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
676 /* User requested specific modifiers */
677 modifier
= select_best_modifier(&screen
->devinfo
, format
,
679 if (modifier
== DRM_FORMAT_MOD_INVALID
)
682 /* Historically, X-tiled was the default, and so lack of modifier means
685 modifier
= I915_FORMAT_MOD_X_TILED
;
689 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
693 const struct isl_drm_modifier_info
*mod_info
=
694 isl_drm_modifier_get_info(modifier
);
696 struct isl_surf surf
;
697 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
698 .dim
= ISL_SURF_DIM_2D
,
699 .format
= brw_isl_format_for_mesa_format(image
->format
),
706 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
707 ISL_SURF_USAGE_TEXTURE_BIT
|
708 ISL_SURF_USAGE_STORAGE_BIT
,
709 .tiling_flags
= (1 << mod_info
->tiling
));
716 struct isl_surf aux_surf
;
717 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
718 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, 0);
724 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
728 /* We request that the bufmgr zero the buffer for us for two reasons:
730 * 1) If a buffer gets re-used from the pool, we don't want to leak random
731 * garbage from our process to some other.
733 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
734 * a valid state. A CCS value of 0 indicates that the given block is
735 * in the pass-through state which is what we want.
737 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
738 surf
.size
+ aux_surf
.size
,
739 isl_tiling_to_i915_tiling(mod_info
->tiling
),
740 surf
.row_pitch
, BO_ALLOC_ZEROED
);
741 if (image
->bo
== NULL
) {
745 image
->width
= width
;
746 image
->height
= height
;
747 image
->pitch
= surf
.row_pitch
;
748 image
->modifier
= modifier
;
751 image
->aux_offset
= surf
.size
;
752 image
->aux_pitch
= aux_surf
.row_pitch
;
753 image
->aux_size
= aux_surf
.size
;
760 intel_create_image(__DRIscreen
*dri_screen
,
761 int width
, int height
, int format
,
765 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
770 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
771 int x0
, int y0
, int width
, int height
,
772 unsigned int flags
, int *stride
, void **map_info
)
774 struct brw_context
*brw
= NULL
;
775 struct brw_bo
*bo
= NULL
;
776 void *raw_data
= NULL
;
781 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
784 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
787 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
790 if (flags
& MAP_INTERNAL_MASK
)
793 brw
= context
->driverPrivate
;
799 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
800 raw_data
= brw_bo_map(brw
, bo
, flags
);
804 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
805 pix_bytes
= _mesa_get_format_bytes(image
->format
);
809 assert(pix_bytes
> 0);
811 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
813 brw_bo_reference(bo
);
815 *stride
= image
->pitch
;
822 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
824 struct brw_bo
*bo
= map_info
;
827 brw_bo_unreference(bo
);
831 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
832 int width
, int height
, int format
,
833 const uint64_t *modifiers
,
834 const unsigned count
,
837 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
838 modifiers
, count
, loaderPrivate
);
842 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
845 case __DRI_IMAGE_ATTRIB_STRIDE
:
846 *value
= image
->pitch
;
848 case __DRI_IMAGE_ATTRIB_HANDLE
:
849 *value
= brw_bo_export_gem_handle(image
->bo
);
851 case __DRI_IMAGE_ATTRIB_NAME
:
852 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
853 case __DRI_IMAGE_ATTRIB_FORMAT
:
854 *value
= image
->dri_format
;
856 case __DRI_IMAGE_ATTRIB_WIDTH
:
857 *value
= image
->width
;
859 case __DRI_IMAGE_ATTRIB_HEIGHT
:
860 *value
= image
->height
;
862 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
863 if (image
->planar_format
== NULL
)
865 *value
= image
->planar_format
->components
;
867 case __DRI_IMAGE_ATTRIB_FD
:
868 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
869 case __DRI_IMAGE_ATTRIB_FOURCC
:
870 return intel_lookup_fourcc(image
->dri_format
, value
);
871 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
872 if (isl_drm_modifier_has_aux(image
->modifier
)) {
873 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
875 } else if (image
->planar_format
) {
876 *value
= image
->planar_format
->nplanes
;
881 case __DRI_IMAGE_ATTRIB_OFFSET
:
882 *value
= image
->offset
;
884 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
885 *value
= (image
->modifier
& 0xffffffff);
887 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
888 *value
= ((image
->modifier
>> 32) & 0xffffffff);
897 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
898 uint32_t fourcc
, uint64_t modifier
,
899 int attrib
, uint64_t *value
)
901 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
902 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
904 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
908 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
909 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
918 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
922 image
= calloc(1, sizeof *image
);
926 brw_bo_reference(orig_image
->bo
);
927 image
->bo
= orig_image
->bo
;
928 image
->internal_format
= orig_image
->internal_format
;
929 image
->planar_format
= orig_image
->planar_format
;
930 image
->dri_format
= orig_image
->dri_format
;
931 image
->format
= orig_image
->format
;
932 image
->modifier
= orig_image
->modifier
;
933 image
->offset
= orig_image
->offset
;
934 image
->width
= orig_image
->width
;
935 image
->height
= orig_image
->height
;
936 image
->pitch
= orig_image
->pitch
;
937 image
->tile_x
= orig_image
->tile_x
;
938 image
->tile_y
= orig_image
->tile_y
;
939 image
->has_depthstencil
= orig_image
->has_depthstencil
;
940 image
->data
= loaderPrivate
;
941 image
->dma_buf_imported
= orig_image
->dma_buf_imported
;
942 image
->aux_offset
= orig_image
->aux_offset
;
943 image
->aux_pitch
= orig_image
->aux_pitch
;
945 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
946 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
952 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
954 if (use
& __DRI_IMAGE_USE_CURSOR
) {
955 if (image
->width
!= 64 || image
->height
!= 64)
963 intel_create_image_from_names(__DRIscreen
*dri_screen
,
964 int width
, int height
, int fourcc
,
965 int *names
, int num_names
,
966 int *strides
, int *offsets
,
969 const struct intel_image_format
*f
= NULL
;
973 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
976 f
= intel_image_format_lookup(fourcc
);
980 image
= intel_create_image_from_name(dri_screen
, width
, height
,
981 __DRI_IMAGE_FORMAT_NONE
,
982 names
[0], strides
[0],
988 image
->planar_format
= f
;
989 for (i
= 0; i
< f
->nplanes
; i
++) {
990 index
= f
->planes
[i
].buffer_index
;
991 image
->offsets
[index
] = offsets
[index
];
992 image
->strides
[index
] = strides
[index
];
999 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1000 int width
, int height
, int fourcc
,
1001 uint64_t modifier
, int *fds
, int num_fds
,
1002 int *strides
, int *offsets
,
1003 void *loaderPrivate
)
1005 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1006 const struct intel_image_format
*f
;
1011 if (fds
== NULL
|| num_fds
< 1)
1014 f
= intel_image_format_lookup(fourcc
);
1018 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1019 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1022 if (f
->nplanes
== 1)
1023 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1026 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1032 image
->width
= width
;
1033 image
->height
= height
;
1034 image
->pitch
= strides
[0];
1036 image
->planar_format
= f
;
1038 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1039 const struct isl_drm_modifier_info
*mod_info
=
1040 isl_drm_modifier_get_info(modifier
);
1041 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1042 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1043 tiling
, strides
[0]);
1045 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1048 if (image
->bo
== NULL
) {
1053 /* We only support all planes from the same bo.
1054 * brw_bo_gem_create_from_prime() should return the same pointer for all
1055 * fds received here */
1056 for (i
= 1; i
< num_fds
; i
++) {
1057 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1058 brw_bo_unreference(aux
);
1059 if (aux
!= image
->bo
) {
1060 brw_bo_unreference(image
->bo
);
1066 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1067 image
->modifier
= modifier
;
1069 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1071 const struct isl_drm_modifier_info
*mod_info
=
1072 isl_drm_modifier_get_info(image
->modifier
);
1075 struct isl_surf surf
;
1076 for (i
= 0; i
< f
->nplanes
; i
++) {
1077 index
= f
->planes
[i
].buffer_index
;
1078 image
->offsets
[index
] = offsets
[index
];
1079 image
->strides
[index
] = strides
[index
];
1081 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1083 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1084 .dim
= ISL_SURF_DIM_2D
,
1085 .format
= brw_isl_format_for_mesa_format(format
),
1086 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1087 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1092 .row_pitch
= strides
[index
],
1093 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1094 ISL_SURF_USAGE_TEXTURE_BIT
|
1095 ISL_SURF_USAGE_STORAGE_BIT
,
1096 .tiling_flags
= (1 << mod_info
->tiling
));
1098 brw_bo_unreference(image
->bo
);
1103 const int end
= offsets
[index
] + surf
.size
;
1108 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1109 /* Even though we initialize surf in the loop above, we know that
1110 * anything with CCS_E will have exactly one plane so surf is properly
1111 * initialized when we get here.
1113 assert(f
->nplanes
== 1);
1115 image
->aux_offset
= offsets
[1];
1116 image
->aux_pitch
= strides
[1];
1118 /* Scanout hardware requires that the CCS be placed after the main
1119 * surface in memory. We consider any CCS that is placed any earlier in
1120 * memory to be invalid and reject it.
1122 * At some point in the future, this restriction may be relaxed if the
1123 * hardware becomes less strict but we may need a new modifier for that.
1126 if (image
->aux_offset
< size
) {
1127 brw_bo_unreference(image
->bo
);
1132 struct isl_surf aux_surf
;
1133 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
,
1136 brw_bo_unreference(image
->bo
);
1141 image
->aux_size
= aux_surf
.size
;
1143 const int end
= image
->aux_offset
+ aux_surf
.size
;
1147 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1150 /* Check that the requested image actually fits within the BO. 'size'
1151 * is already relative to the offsets, so we don't need to add that. */
1152 if (image
->bo
->size
== 0) {
1153 image
->bo
->size
= size
;
1154 } else if (size
> image
->bo
->size
) {
1155 brw_bo_unreference(image
->bo
);
1160 if (f
->nplanes
== 1) {
1161 image
->offset
= image
->offsets
[0];
1162 intel_image_warn_if_unaligned(image
, __func__
);
1169 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1170 int width
, int height
, int fourcc
,
1171 int *fds
, int num_fds
, int *strides
, int *offsets
,
1172 void *loaderPrivate
)
1174 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1175 DRM_FORMAT_MOD_INVALID
,
1176 fds
, num_fds
, strides
, offsets
,
1181 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1182 int width
, int height
,
1183 int fourcc
, uint64_t modifier
,
1184 int *fds
, int num_fds
,
1185 int *strides
, int *offsets
,
1186 enum __DRIYUVColorSpace yuv_color_space
,
1187 enum __DRISampleRange sample_range
,
1188 enum __DRIChromaSiting horizontal_siting
,
1189 enum __DRIChromaSiting vertical_siting
,
1191 void *loaderPrivate
)
1194 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1197 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1201 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1203 fds
, num_fds
, strides
, offsets
,
1207 * Invalid parameters and any inconsistencies between are assumed to be
1208 * checked by the caller. Therefore besides unsupported formats one can fail
1209 * only in allocation.
1212 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1216 image
->dma_buf_imported
= true;
1217 image
->yuv_color_space
= yuv_color_space
;
1218 image
->sample_range
= sample_range
;
1219 image
->horizontal_siting
= horizontal_siting
;
1220 image
->vertical_siting
= vertical_siting
;
1222 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1227 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1228 int width
, int height
, int fourcc
,
1229 int *fds
, int num_fds
,
1230 int *strides
, int *offsets
,
1231 enum __DRIYUVColorSpace yuv_color_space
,
1232 enum __DRISampleRange sample_range
,
1233 enum __DRIChromaSiting horizontal_siting
,
1234 enum __DRIChromaSiting vertical_siting
,
1236 void *loaderPrivate
)
1238 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1239 fourcc
, DRM_FORMAT_MOD_INVALID
,
1240 fds
, num_fds
, strides
, offsets
,
1250 intel_query_dma_buf_formats(__DRIscreen
*screen
, int max
,
1251 int *formats
, int *count
)
1256 *count
= ARRAY_SIZE(intel_image_formats
) - 1; /* not SARGB */
1260 for (i
= 0; i
< (ARRAY_SIZE(intel_image_formats
)) && j
< max
; i
++) {
1261 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
)
1263 formats
[j
++] = intel_image_formats
[i
].fourcc
;
1271 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1272 uint64_t *modifiers
,
1273 unsigned int *external_only
,
1276 struct intel_screen
*screen
= _screen
->driverPrivate
;
1277 const struct intel_image_format
*f
;
1278 int num_mods
= 0, i
;
1280 f
= intel_image_format_lookup(fourcc
);
1284 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1285 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1286 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1293 modifiers
[num_mods
- 1] = modifier
;
1294 if (num_mods
>= max
)
1298 if (external_only
!= NULL
) {
1299 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1300 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1301 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1302 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1303 external_only
[i
] = GL_TRUE
;
1306 external_only
[i
] = GL_FALSE
;
1316 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1318 int width
, height
, offset
, stride
, size
, dri_format
;
1324 width
= parent
->width
;
1325 height
= parent
->height
;
1327 const struct intel_image_format
*f
= parent
->planar_format
;
1329 if (f
&& plane
< f
->nplanes
) {
1330 /* Use the planar format definition. */
1331 width
>>= f
->planes
[plane
].width_shift
;
1332 height
>>= f
->planes
[plane
].height_shift
;
1333 dri_format
= f
->planes
[plane
].dri_format
;
1334 int index
= f
->planes
[plane
].buffer_index
;
1335 offset
= parent
->offsets
[index
];
1336 stride
= parent
->strides
[index
];
1337 size
= height
* stride
;
1338 } else if (plane
== 0) {
1339 /* The only plane of a non-planar image: copy the parent definition
1341 dri_format
= parent
->dri_format
;
1342 offset
= parent
->offset
;
1343 stride
= parent
->pitch
;
1344 size
= height
* stride
;
1345 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1346 isl_drm_modifier_has_aux(parent
->modifier
)) {
1347 /* Auxiliary plane */
1348 dri_format
= parent
->dri_format
;
1349 offset
= parent
->aux_offset
;
1350 stride
= parent
->aux_pitch
;
1351 size
= parent
->aux_size
;
1356 if (offset
+ size
> parent
->bo
->size
) {
1357 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1361 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1365 image
->bo
= parent
->bo
;
1366 brw_bo_reference(parent
->bo
);
1367 image
->modifier
= parent
->modifier
;
1369 image
->width
= width
;
1370 image
->height
= height
;
1371 image
->pitch
= stride
;
1372 image
->offset
= offset
;
1374 intel_image_warn_if_unaligned(image
, __func__
);
1379 static const __DRIimageExtension intelImageExtension
= {
1380 .base
= { __DRI_IMAGE
, 16 },
1382 .createImageFromName
= intel_create_image_from_name
,
1383 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1384 .destroyImage
= intel_destroy_image
,
1385 .createImage
= intel_create_image
,
1386 .queryImage
= intel_query_image
,
1387 .dupImage
= intel_dup_image
,
1388 .validateUsage
= intel_validate_usage
,
1389 .createImageFromNames
= intel_create_image_from_names
,
1390 .fromPlanar
= intel_from_planar
,
1391 .createImageFromTexture
= intel_create_image_from_texture
,
1392 .createImageFromFds
= intel_create_image_from_fds
,
1393 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1395 .getCapabilities
= NULL
,
1396 .mapImage
= intel_map_image
,
1397 .unmapImage
= intel_unmap_image
,
1398 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1399 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1400 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1401 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1402 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1406 get_aperture_size(int fd
)
1408 struct drm_i915_gem_get_aperture aperture
;
1410 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1413 return aperture
.aper_size
;
1417 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1418 int param
, unsigned int *value
)
1420 const struct intel_screen
*const screen
=
1421 (struct intel_screen
*) dri_screen
->driverPrivate
;
1424 case __DRI2_RENDERER_VENDOR_ID
:
1427 case __DRI2_RENDERER_DEVICE_ID
:
1428 value
[0] = screen
->deviceID
;
1430 case __DRI2_RENDERER_ACCELERATED
:
1433 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1434 /* Once a batch uses more than 75% of the maximum mappable size, we
1435 * assume that there's some fragmentation, and we start doing extra
1436 * flushing, etc. That's the big cliff apps will care about.
1438 const unsigned gpu_mappable_megabytes
=
1439 screen
->aperture_threshold
/ (1024 * 1024);
1441 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1442 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1444 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1447 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1448 * (uint64_t) system_page_size
;
1450 const unsigned system_memory_megabytes
=
1451 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1453 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1456 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1459 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1462 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1464 if (brw_hw_context_set_priority(screen
->bufmgr
,
1465 0, BRW_CONTEXT_HIGH_PRIORITY
) == 0)
1466 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1467 if (brw_hw_context_set_priority(screen
->bufmgr
,
1468 0, BRW_CONTEXT_LOW_PRIORITY
) == 0)
1469 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1470 /* reset to default last, just in case */
1471 if (brw_hw_context_set_priority(screen
->bufmgr
,
1472 0, BRW_CONTEXT_MEDIUM_PRIORITY
) == 0)
1473 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1475 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1479 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1486 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1487 int param
, const char **value
)
1489 const struct intel_screen
*screen
=
1490 (struct intel_screen
*) dri_screen
->driverPrivate
;
1493 case __DRI2_RENDERER_VENDOR_ID
:
1494 value
[0] = brw_vendor_string
;
1496 case __DRI2_RENDERER_DEVICE_ID
:
1497 value
[0] = brw_get_renderer_string(screen
);
1507 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1508 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1510 const struct intel_screen
*const screen
=
1511 (struct intel_screen
*) dri_screen
->driverPrivate
;
1513 if (!screen
->disk_cache
)
1516 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1519 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1520 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1522 .queryInteger
= brw_query_renderer_integer
,
1523 .queryString
= brw_query_renderer_string
1526 static const __DRIrobustnessExtension dri2Robustness
= {
1527 .base
= { __DRI2_ROBUSTNESS
, 1 }
1530 static const __DRI2blobExtension intelBlobExtension
= {
1531 .base
= { __DRI2_BLOB
, 1 },
1532 .set_cache_funcs
= brw_set_cache_funcs
1535 static const __DRIextension
*screenExtensions
[] = {
1536 &intelTexBufferExtension
.base
,
1537 &intelFenceExtension
.base
,
1538 &intelFlushExtension
.base
,
1539 &intelImageExtension
.base
,
1540 &intelRendererQueryExtension
.base
,
1541 &dri2ConfigQueryExtension
.base
,
1542 &dri2NoErrorExtension
.base
,
1543 &intelBlobExtension
.base
,
1547 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1548 &intelTexBufferExtension
.base
,
1549 &intelFenceExtension
.base
,
1550 &intelFlushExtension
.base
,
1551 &intelImageExtension
.base
,
1552 &intelRendererQueryExtension
.base
,
1553 &dri2ConfigQueryExtension
.base
,
1554 &dri2Robustness
.base
,
1555 &dri2NoErrorExtension
.base
,
1556 &intelBlobExtension
.base
,
1561 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1564 struct drm_i915_getparam gp
;
1566 memset(&gp
, 0, sizeof(gp
));
1570 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1573 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1580 intel_get_boolean(struct intel_screen
*screen
, int param
)
1583 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1587 intel_get_integer(struct intel_screen
*screen
, int param
)
1591 if (intel_get_param(screen
, param
, &value
) == 0)
1598 intelDestroyScreen(__DRIscreen
* sPriv
)
1600 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1602 brw_bufmgr_destroy(screen
->bufmgr
);
1603 driDestroyOptionInfo(&screen
->optionCache
);
1605 disk_cache_destroy(screen
->disk_cache
);
1607 ralloc_free(screen
);
1608 sPriv
->driverPrivate
= NULL
;
1613 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1615 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1616 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1617 * this does not allocate GPU memory.
1620 intelCreateBuffer(__DRIscreen
*dri_screen
,
1621 __DRIdrawable
* driDrawPriv
,
1622 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1624 struct intel_renderbuffer
*rb
;
1625 struct intel_screen
*screen
= (struct intel_screen
*)
1626 dri_screen
->driverPrivate
;
1627 mesa_format rgbFormat
;
1628 unsigned num_samples
=
1629 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1634 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1638 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1640 if (screen
->winsys_msaa_samples_override
!= -1) {
1641 num_samples
= screen
->winsys_msaa_samples_override
;
1642 fb
->Visual
.samples
= num_samples
;
1645 if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1646 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1647 : MESA_FORMAT_R10G10B10A2_UNORM
;
1648 } else if (mesaVis
->redBits
== 10) {
1649 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1650 : MESA_FORMAT_R10G10B10X2_UNORM
;
1651 } else if (mesaVis
->redBits
== 5) {
1652 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1653 : MESA_FORMAT_B5G6R5_UNORM
;
1654 } else if (mesaVis
->sRGBCapable
) {
1655 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1656 : MESA_FORMAT_B8G8R8A8_SRGB
;
1657 } else if (mesaVis
->alphaBits
== 0) {
1658 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1659 : MESA_FORMAT_B8G8R8X8_UNORM
;
1661 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1662 : MESA_FORMAT_B8G8R8A8_SRGB
;
1663 fb
->Visual
.sRGBCapable
= true;
1666 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1667 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1669 /* setup the hardware-based renderbuffers */
1670 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1671 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1672 rb
->need_srgb
= srgb_cap_set
;
1674 if (mesaVis
->doubleBufferMode
) {
1675 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1676 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1677 rb
->need_srgb
= srgb_cap_set
;
1681 * Assert here that the gl_config has an expected depth/stencil bit
1682 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1683 * which constructs the advertised configs.)
1685 if (mesaVis
->depthBits
== 24) {
1686 assert(mesaVis
->stencilBits
== 8);
1688 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1689 rb
= intel_create_private_renderbuffer(screen
,
1690 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1692 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1693 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1695 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1698 * Use combined depth/stencil. Note that the renderbuffer is
1699 * attached to two attachment points.
1701 rb
= intel_create_private_renderbuffer(screen
,
1702 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1704 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1705 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1708 else if (mesaVis
->depthBits
== 16) {
1709 assert(mesaVis
->stencilBits
== 0);
1710 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1712 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1715 assert(mesaVis
->depthBits
== 0);
1716 assert(mesaVis
->stencilBits
== 0);
1719 /* now add any/all software-based renderbuffers we may need */
1720 _swrast_add_soft_renderbuffers(fb
,
1721 false, /* never sw color */
1722 false, /* never sw depth */
1723 false, /* never sw stencil */
1724 mesaVis
->accumRedBits
> 0,
1725 false, /* never sw alpha */
1726 false /* never sw aux */ );
1727 driDrawPriv
->driverPrivate
= fb
;
1733 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1735 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1737 _mesa_reference_framebuffer(&fb
, NULL
);
1741 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1743 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1744 * gen10, PCI-id is enough to figure it out.
1746 assert(screen
->devinfo
.gen
>= 10);
1750 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1754 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1758 screen
->devinfo
.timestamp_frequency
= freq
;
1762 intel_detect_sseu(struct intel_screen
*screen
)
1764 assert(screen
->devinfo
.gen
>= 8);
1767 screen
->subslice_total
= -1;
1768 screen
->eu_total
= -1;
1770 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1771 &screen
->subslice_total
);
1772 if (ret
< 0 && ret
!= -EINVAL
)
1775 ret
= intel_get_param(screen
,
1776 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1777 if (ret
< 0 && ret
!= -EINVAL
)
1780 /* Without this information, we cannot get the right Braswell brandstrings,
1781 * and we have to use conservative numbers for GPGPU on many platforms, but
1782 * otherwise, things will just work.
1784 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1786 "Kernel 4.1 required to properly query GPU properties.\n");
1791 screen
->subslice_total
= -1;
1792 screen
->eu_total
= -1;
1793 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1797 intel_init_bufmgr(struct intel_screen
*screen
)
1799 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1801 if (getenv("INTEL_NO_HW") != NULL
)
1802 screen
->no_hw
= true;
1804 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
);
1805 if (screen
->bufmgr
== NULL
) {
1806 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1807 __func__
, __LINE__
);
1811 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1812 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1820 intel_detect_swizzling(struct intel_screen
*screen
)
1822 struct brw_bo
*buffer
;
1824 uint32_t aligned_pitch
;
1825 uint32_t tiling
= I915_TILING_X
;
1826 uint32_t swizzle_mode
= 0;
1828 buffer
= brw_bo_alloc_tiled_2d(screen
->bufmgr
, "swizzle test",
1829 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1833 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1834 brw_bo_unreference(buffer
);
1836 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1843 intel_detect_timestamp(struct intel_screen
*screen
)
1845 uint64_t dummy
= 0, last
= 0;
1846 int upper
, lower
, loops
;
1848 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1849 * TIMESTAMP register being shifted and the low 32bits always zero.
1851 * More recent kernels offer an interface to read the full 36bits
1854 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1857 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1858 * upper 32bits for a rapidly changing timestamp.
1860 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1864 for (loops
= 0; loops
< 10; loops
++) {
1865 /* The TIMESTAMP should change every 80ns, so several round trips
1866 * through the kernel should be enough to advance it.
1868 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1871 upper
+= (dummy
>> 32) != (last
>> 32);
1872 if (upper
> 1) /* beware 32bit counter overflow */
1873 return 2; /* upper dword holds the low 32bits of the timestamp */
1875 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1877 return 1; /* timestamp is unshifted */
1882 /* No advancement? No timestamp! */
1887 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1889 * Some combinations of hardware and kernel versions allow this feature,
1890 * while others don't. Instead of trying to enumerate every case, just
1891 * try and write a register and see if works.
1894 intel_detect_pipelined_register(struct intel_screen
*screen
,
1895 int reg
, uint32_t expected_value
, bool reset
)
1900 struct brw_bo
*results
, *bo
;
1902 uint32_t offset
= 0;
1904 bool success
= false;
1906 /* Create a zero'ed temporary buffer for reading our results */
1907 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1908 if (results
== NULL
)
1911 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1915 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
1921 /* Write the register. */
1922 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1924 *batch
++ = expected_value
;
1926 /* Save the register's value back to the buffer. */
1927 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1929 struct drm_i915_gem_relocation_entry reloc
= {
1930 .offset
= (char *) batch
- (char *) map
,
1931 .delta
= offset
* sizeof(uint32_t),
1932 .target_handle
= results
->gem_handle
,
1933 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1934 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1936 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1938 /* And afterwards clear the register */
1940 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1945 *batch
++ = MI_BATCH_BUFFER_END
;
1947 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1949 .handle
= results
->gem_handle
,
1952 .handle
= bo
->gem_handle
,
1953 .relocation_count
= 1,
1954 .relocs_ptr
= (uintptr_t) &reloc
,
1958 struct drm_i915_gem_execbuffer2 execbuf
= {
1959 .buffers_ptr
= (uintptr_t) exec_objects
,
1961 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
1962 .flags
= I915_EXEC_RENDER
,
1965 /* Don't bother with error checking - if the execbuf fails, the
1966 * value won't be written and we'll just report that there's no access.
1968 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1969 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1971 /* Check whether the value got written. */
1972 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
1974 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
1975 brw_bo_unmap(results
);
1979 brw_bo_unreference(bo
);
1981 brw_bo_unreference(results
);
1987 intel_detect_pipelined_so(struct intel_screen
*screen
)
1989 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1991 /* Supposedly, Broadwell just works. */
1992 if (devinfo
->gen
>= 8)
1995 if (devinfo
->gen
<= 6)
1998 /* See the big explanation about command parser versions below */
1999 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2002 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2003 * statistics registers), and we already reset it to zero before using it.
2005 return intel_detect_pipelined_register(screen
,
2006 GEN7_SO_WRITE_OFFSET(0),
2012 * Return array of MSAA modes supported by the hardware. The array is
2013 * zero-terminated and sorted in decreasing order.
2016 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2018 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2019 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2020 static const int gen7_modes
[] = {8, 4, 0, -1};
2021 static const int gen6_modes
[] = {4, 0, -1};
2022 static const int gen4_modes
[] = {0, -1};
2024 if (screen
->devinfo
.gen
>= 9) {
2026 } else if (screen
->devinfo
.gen
>= 8) {
2028 } else if (screen
->devinfo
.gen
>= 7) {
2030 } else if (screen
->devinfo
.gen
== 6) {
2038 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2040 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2041 dri_screen
->dri2
.loader
->getCapability
)
2042 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2044 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2045 dri_screen
->image
.loader
->getCapability
)
2046 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2051 static __DRIconfig
**
2052 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2054 static const mesa_format formats
[] = {
2055 MESA_FORMAT_B5G6R5_UNORM
,
2056 MESA_FORMAT_B8G8R8A8_UNORM
,
2057 MESA_FORMAT_B8G8R8X8_UNORM
,
2059 MESA_FORMAT_B8G8R8A8_SRGB
,
2061 /* For 10 bpc, 30 bit depth framebuffers. */
2062 MESA_FORMAT_B10G10R10A2_UNORM
,
2063 MESA_FORMAT_B10G10R10X2_UNORM
,
2065 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2066 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2067 * server may disagree on which format the GLXFBConfig represents,
2068 * resulting in swapped color channels.
2070 * The problem, as of 2017-05-30:
2071 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2072 * order and chooses the first __DRIconfig with the expected channel
2073 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2074 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2076 * EGL does not suffer from this problem. It correctly compares the
2077 * channel masks when matching EGLConfig to __DRIconfig.
2080 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2081 MESA_FORMAT_R8G8B8A8_UNORM
,
2083 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2084 MESA_FORMAT_R8G8B8X8_UNORM
,
2087 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
2088 static const GLenum back_buffer_modes
[] = {
2089 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2092 static const uint8_t singlesample_samples
[1] = {0};
2094 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2095 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2096 uint8_t depth_bits
[4], stencil_bits
[4];
2097 __DRIconfig
**configs
= NULL
;
2099 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2100 unsigned num_formats
;
2101 if (intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
))
2102 num_formats
= ARRAY_SIZE(formats
);
2104 num_formats
= ARRAY_SIZE(formats
) - 2; /* all - RGBA_ORDERING formats */
2106 /* Shall we expose 10 bpc formats? */
2107 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2108 "allow_rgb10_configs");
2110 /* Generate singlesample configs without accumulation buffer. */
2111 for (unsigned i
= 0; i
< num_formats
; i
++) {
2112 __DRIconfig
**new_configs
;
2113 int num_depth_stencil_bits
= 2;
2115 if (!allow_rgb10_configs
&&
2116 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2117 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2120 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2121 * buffer that has a different number of bits per pixel than the color
2122 * buffer, gen >= 6 supports this.
2125 stencil_bits
[0] = 0;
2127 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2129 stencil_bits
[1] = 0;
2130 if (devinfo
->gen
>= 6) {
2132 stencil_bits
[2] = 8;
2133 num_depth_stencil_bits
= 3;
2137 stencil_bits
[1] = 8;
2140 new_configs
= driCreateConfigs(formats
[i
],
2143 num_depth_stencil_bits
,
2144 back_buffer_modes
, 2,
2145 singlesample_samples
, 1,
2147 configs
= driConcatConfigs(configs
, new_configs
);
2150 /* Generate the minimum possible set of configs that include an
2151 * accumulation buffer.
2153 for (unsigned i
= 0; i
< num_formats
; i
++) {
2154 __DRIconfig
**new_configs
;
2156 if (!allow_rgb10_configs
&&
2157 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2158 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2161 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2163 stencil_bits
[0] = 0;
2166 stencil_bits
[0] = 8;
2169 new_configs
= driCreateConfigs(formats
[i
],
2170 depth_bits
, stencil_bits
, 1,
2171 back_buffer_modes
, 1,
2172 singlesample_samples
, 1,
2174 configs
= driConcatConfigs(configs
, new_configs
);
2177 /* Generate multisample configs.
2179 * This loop breaks early, and hence is a no-op, on gen < 6.
2181 * Multisample configs must follow the singlesample configs in order to
2182 * work around an X server bug present in 1.12. The X server chooses to
2183 * associate the first listed RGBA888-Z24S8 config, regardless of its
2184 * sample count, with the 32-bit depth visual used for compositing.
2186 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2187 * supported. Singlebuffer configs are not supported because no one wants
2190 for (unsigned i
= 0; i
< num_formats
; i
++) {
2191 if (devinfo
->gen
< 6)
2194 if (!allow_rgb10_configs
&&
2195 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2196 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2199 __DRIconfig
**new_configs
;
2200 const int num_depth_stencil_bits
= 2;
2201 int num_msaa_modes
= 0;
2202 const uint8_t *multisample_samples
= NULL
;
2205 stencil_bits
[0] = 0;
2207 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2209 stencil_bits
[1] = 0;
2212 stencil_bits
[1] = 8;
2215 if (devinfo
->gen
>= 9) {
2216 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2217 multisample_samples
= multisample_samples_gen9
;
2218 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2219 } else if (devinfo
->gen
== 8) {
2220 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2221 multisample_samples
= multisample_samples_gen8
;
2222 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2223 } else if (devinfo
->gen
== 7) {
2224 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2225 multisample_samples
= multisample_samples_gen7
;
2226 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2227 } else if (devinfo
->gen
== 6) {
2228 static const uint8_t multisample_samples_gen6
[] = {4};
2229 multisample_samples
= multisample_samples_gen6
;
2230 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2233 new_configs
= driCreateConfigs(formats
[i
],
2236 num_depth_stencil_bits
,
2237 back_buffer_modes
, 1,
2238 multisample_samples
,
2241 configs
= driConcatConfigs(configs
, new_configs
);
2244 if (configs
== NULL
) {
2245 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2254 set_max_gl_versions(struct intel_screen
*screen
)
2256 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2257 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2259 switch (screen
->devinfo
.gen
) {
2264 dri_screen
->max_gl_core_version
= 45;
2265 dri_screen
->max_gl_compat_version
= 30;
2266 dri_screen
->max_gl_es1_version
= 11;
2267 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2270 dri_screen
->max_gl_core_version
= 33;
2271 if (can_do_pipelined_register_writes(screen
)) {
2272 dri_screen
->max_gl_core_version
= 42;
2273 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2274 dri_screen
->max_gl_core_version
= 43;
2275 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2276 dri_screen
->max_gl_core_version
= 45;
2278 dri_screen
->max_gl_compat_version
= 30;
2279 dri_screen
->max_gl_es1_version
= 11;
2280 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2283 dri_screen
->max_gl_core_version
= 33;
2284 dri_screen
->max_gl_compat_version
= 30;
2285 dri_screen
->max_gl_es1_version
= 11;
2286 dri_screen
->max_gl_es2_version
= 30;
2290 dri_screen
->max_gl_core_version
= 0;
2291 dri_screen
->max_gl_compat_version
= 21;
2292 dri_screen
->max_gl_es1_version
= 11;
2293 dri_screen
->max_gl_es2_version
= 20;
2296 unreachable("unrecognized intel_screen::gen");
2301 * Return the revision (generally the revid field of the PCI header) of the
2305 intel_device_get_revision(int fd
)
2307 struct drm_i915_getparam gp
;
2311 memset(&gp
, 0, sizeof(gp
));
2312 gp
.param
= I915_PARAM_REVISION
;
2313 gp
.value
= &revision
;
2315 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
2323 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2325 struct brw_context
*brw
= (struct brw_context
*)data
;
2328 va_start(args
, fmt
);
2330 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2331 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2332 MESA_DEBUG_TYPE_OTHER
,
2333 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2338 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2340 struct brw_context
*brw
= (struct brw_context
*)data
;
2343 va_start(args
, fmt
);
2345 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2347 va_copy(args_copy
, args
);
2348 vfprintf(stderr
, fmt
, args_copy
);
2352 if (brw
->perf_debug
) {
2354 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2355 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2356 MESA_DEBUG_TYPE_PERFORMANCE
,
2357 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2363 parse_devid_override(const char *devid_override
)
2365 static const struct {
2385 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
2386 if (!strcmp(name_map
[i
].name
, devid_override
))
2387 return name_map
[i
].pci_id
;
2390 return strtol(devid_override
, NULL
, 0);
2394 * Get the PCI ID for the device. This can be overridden by setting the
2395 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2397 * Returns -1 on ioctl failure.
2400 get_pci_device_id(struct intel_screen
*screen
)
2402 if (geteuid() == getuid()) {
2403 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
2404 if (devid_override
) {
2405 screen
->no_hw
= true;
2406 return parse_devid_override(devid_override
);
2410 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2414 * This is the driver specific part of the createNewScreen entry point.
2415 * Called when using DRI2.
2417 * \return the struct gl_config supported by this driver
2420 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2422 struct intel_screen
*screen
;
2424 if (dri_screen
->image
.loader
) {
2425 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2426 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2428 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2429 "support required\n");
2433 /* Allocate the private area */
2434 screen
= rzalloc(NULL
, struct intel_screen
);
2436 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2439 /* parse information in __driConfigOptions */
2440 driOptionCache options
;
2441 memset(&options
, 0, sizeof(options
));
2443 driParseOptionInfo(&options
, brw_config_options
.xml
);
2444 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
, "i965");
2445 driDestroyOptionCache(&options
);
2447 screen
->driScrnPriv
= dri_screen
;
2448 dri_screen
->driverPrivate
= (void *) screen
;
2450 screen
->deviceID
= get_pci_device_id(screen
);
2452 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2455 if (!intel_init_bufmgr(screen
))
2458 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2460 brw_process_intel_debug_variable();
2462 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2464 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2465 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2468 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2469 /* Theorectically unlimited! At least for individual objects...
2471 * Currently the entire (global) address space for all GTT maps is
2472 * limited to 64bits. That is all objects on the system that are
2473 * setup for GTT mmapping must fit within 64bits. An attempt to use
2474 * one that exceeds the limit with fail in brw_bo_map_gtt().
2476 * Long before we hit that limit, we will be practically limited by
2477 * that any single object must fit in physical memory (RAM). The upper
2478 * limit on the CPU's address space is currently 48bits (Skylake), of
2479 * which only 39bits can be physical memory. (The GPU itself also has
2480 * a 48bit addressable virtual space.) We can fit over 32 million
2481 * objects of the current maximum allocable size before running out
2484 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2486 /* Estimate the size of the mappable aperture into the GTT. There's an
2487 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2488 * It turns out it's basically always 256MB, though some ancient hardware
2491 uint32_t gtt_size
= 256 * 1024 * 1024;
2493 /* We don't want to map two objects such that a memcpy between them would
2494 * just fault one mapping in and then the other over and over forever. So
2495 * we would need to divide the GTT size by 2. Additionally, some GTT is
2496 * taken up by things like the framebuffer and the ringbuffer and such, so
2497 * be more conservative.
2499 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2502 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2504 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2505 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2507 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2508 screen
->hw_has_swizzling
);
2510 if (devinfo
->gen
>= 10)
2511 intel_cs_timestamp_frequency(screen
);
2513 /* GENs prior to 8 do not support EU/Subslice info */
2514 if (devinfo
->gen
>= 8) {
2515 intel_detect_sseu(screen
);
2516 } else if (devinfo
->gen
== 7) {
2517 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2520 /* Gen7-7.5 kernel requirements / command parser saga:
2523 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2525 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2526 * all batches secure, allowing them to use any feature with no checking.
2527 * This is effectively equivalent to a command parser version of
2528 * \infinity - everything is possible.
2530 * The command parser does not exist, and querying the version will
2534 * The kernel enables the command parser by default, for systems with
2535 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2536 * hardware checker is still enabled, so Haswell and Baytrail cannot
2539 * Ivybridge goes from "everything is possible" to "only what the
2540 * command parser allows" (if the user boots with i915.cmd_parser=0,
2541 * then everything is possible again). We can only safely use features
2542 * allowed by the supported command parser version.
2544 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2545 * implemented by the kernel, even if it's turned off. So, checking
2546 * for version > 0 does not mean that you can write registers. We have
2547 * to try it and see. The version does, however, indicate the age of
2550 * Instead of matching the hardware checker's behavior of converting
2551 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2552 * -EINVAL, making it dangerous to try and use privileged features.
2554 * Effective command parser versions:
2555 * - Haswell: 0 (reporting 1, writes don't work)
2556 * - Baytrail: 0 (reporting 1, writes don't work)
2557 * - Ivybridge: 1 (enabled) or infinite (disabled)
2560 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2561 * effectively version 1 (enabled) or infinite (disabled).
2563 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2564 * Command parser v2 supports predicate writes.
2566 * - Haswell: 0 (reporting 1, writes don't work)
2567 * - Baytrail: 2 (enabled) or infinite (disabled)
2568 * - Ivybridge: 2 (enabled) or infinite (disabled)
2570 * So version >= 2 is enough to know that Ivybridge and Baytrail
2571 * will work. Haswell still can't do anything.
2573 * - v4.0: Version 3 happened. Largely not relevant.
2575 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2576 * L3 config registers are properly saved and restored as part
2577 * of the hardware context. We can approximately detect this point
2578 * in time by checking if I915_PARAM_REVISION is recognized - it
2579 * landed in a later commit, but in the same release cycle.
2581 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2582 * Command parser finally gains secure batch promotion. On Haswell,
2583 * the hardware checker gets disabled, which finally allows it to do
2584 * privileged commands.
2586 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2587 * - Haswell: 3 (enabled) or 0 (disabled)
2588 * - Baytrail: 3 (enabled) or infinite (disabled)
2589 * - Ivybridge: 3 (enabled) or infinite (disabled)
2591 * Unfortunately, detecting this point in time is tricky, because
2592 * no version bump happened when this important change occurred.
2593 * On Haswell, if we can write any register, then the kernel is at
2594 * least this new, and we can start trusting the version number.
2596 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2597 * Command parser reaches version 4, allowing access to Haswell
2598 * atomic scratch and chicken3 registers. If version >= 4, we know
2599 * the kernel is new enough to support privileged features on all
2600 * hardware. However, the user might have disabled it...and the
2601 * kernel will still report version 4. So we still have to guess
2604 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2605 * Command parser v5 whitelists indirect compute shader dispatch
2606 * registers, needed for OpenGL 4.3 and later.
2609 * Command parser v7 lets us use MI_MATH on Haswell.
2611 * Additionally, the kernel begins reporting version 0 when
2612 * the command parser is disabled, allowing us to skip the
2613 * guess-and-check step on Haswell. Unfortunately, this also
2614 * means that we can no longer use it as an indicator of the
2615 * age of the kernel.
2617 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2618 &screen
->cmd_parser_version
) < 0) {
2619 /* Command parser does not exist - getparam is unrecognized */
2620 screen
->cmd_parser_version
= 0;
2623 /* Kernel 4.13 retuired for exec object capture */
2624 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2625 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2628 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2629 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2632 if (!intel_detect_pipelined_so(screen
)) {
2633 /* We can't do anything, so the effective version is 0. */
2634 screen
->cmd_parser_version
= 0;
2636 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2639 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2640 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2642 /* Haswell requires command parser version 4 in order to have L3
2643 * atomic scratch1 and chicken3 bits
2645 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2646 screen
->kernel_features
|=
2647 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2650 /* Haswell requires command parser version 6 in order to write to the
2651 * MI_MATH GPR registers, and version 7 in order to use
2652 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2654 if (devinfo
->gen
>= 8 ||
2655 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2656 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2659 /* Gen7 needs at least command parser version 5 to support compute */
2660 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2661 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2663 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2664 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2666 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2668 screen
->winsys_msaa_samples_override
=
2669 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2670 printf("Forcing winsys sample count to %d\n",
2671 screen
->winsys_msaa_samples_override
);
2673 screen
->winsys_msaa_samples_override
= -1;
2676 set_max_gl_versions(screen
);
2678 /* Notification of GPU resets requires hardware contexts and a kernel new
2679 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2680 * supported, calling it with a context of 0 will either generate EPERM or
2681 * no error. If the ioctl is not supported, it always generate EINVAL.
2682 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2683 * extension to the loader.
2685 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2687 if (devinfo
->gen
>= 6) {
2688 struct drm_i915_reset_stats stats
;
2689 memset(&stats
, 0, sizeof(stats
));
2691 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2693 screen
->has_context_reset_notification
=
2694 (ret
!= -1 || errno
!= EINVAL
);
2697 dri_screen
->extensions
= !screen
->has_context_reset_notification
2698 ? screenExtensions
: intelRobustScreenExtensions
;
2700 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2701 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2702 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2703 screen
->compiler
->constant_buffer_0_is_relative
= true;
2704 screen
->compiler
->supports_pull_constants
= true;
2706 screen
->has_exec_fence
=
2707 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2709 intel_screen_init_surface_formats(screen
);
2711 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2712 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2714 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2715 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2716 fprintf(stderr
, " - User priority sorting enabled\n");
2717 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2718 fprintf(stderr
, " - Preemption enabled\n");
2722 brw_disk_cache_init(screen
);
2724 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2727 struct intel_buffer
{
2732 static __DRIbuffer
*
2733 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2734 unsigned attachment
, unsigned format
,
2735 int width
, int height
)
2737 struct intel_buffer
*intelBuffer
;
2738 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2740 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2741 attachment
== __DRI_BUFFER_BACK_LEFT
);
2743 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2744 if (intelBuffer
== NULL
)
2747 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2748 * supports Y tiled and compressed buffers, but there is no way to plumb that
2749 * through to here. */
2751 int cpp
= format
/ 8;
2752 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2753 "intelAllocateBuffer",
2757 I915_TILING_X
, &pitch
,
2760 if (intelBuffer
->bo
== NULL
) {
2765 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2767 intelBuffer
->base
.attachment
= attachment
;
2768 intelBuffer
->base
.cpp
= cpp
;
2769 intelBuffer
->base
.pitch
= pitch
;
2771 return &intelBuffer
->base
;
2775 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2777 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2779 brw_bo_unreference(intelBuffer
->bo
);
2783 static const struct __DriverAPIRec brw_driver_api
= {
2784 .InitScreen
= intelInitScreen2
,
2785 .DestroyScreen
= intelDestroyScreen
,
2786 .CreateContext
= brwCreateContext
,
2787 .DestroyContext
= intelDestroyContext
,
2788 .CreateBuffer
= intelCreateBuffer
,
2789 .DestroyBuffer
= intelDestroyBuffer
,
2790 .MakeCurrent
= intelMakeCurrent
,
2791 .UnbindContext
= intelUnbindContext
,
2792 .AllocateBuffer
= intelAllocateBuffer
,
2793 .ReleaseBuffer
= intelReleaseBuffer
2796 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2797 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2798 .vtable
= &brw_driver_api
,
2801 static const __DRIextension
*brw_driver_extensions
[] = {
2802 &driCoreExtension
.base
,
2803 &driImageDriverExtension
.base
,
2804 &driDRI2Extension
.base
,
2806 &brw_config_options
.base
,
2810 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2812 globalDriverAPI
= &brw_driver_api
;
2814 return brw_driver_extensions
;