2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "brw_state.h"
41 #include "compiler/nir/nir.h"
44 #include "util/disk_cache.h"
45 #include "util/xmlpool.h"
47 static const __DRIconfigOptionsExtension brw_config_options
= {
48 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
51 DRI_CONF_SECTION_PERFORMANCE
52 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
53 * DRI_CONF_BO_REUSE_ALL
55 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
56 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
57 DRI_CONF_ENUM(0, "Disable buffer object reuse")
58 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
61 DRI_CONF_MESA_NO_ERROR("false")
64 DRI_CONF_SECTION_QUALITY
65 DRI_CONF_PRECISE_TRIG("false")
67 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
68 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
69 "given integer. If negative, then do not clamp.")
73 DRI_CONF_SECTION_DEBUG
74 DRI_CONF_NO_RAST("false")
75 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
76 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
77 DRI_CONF_DISABLE_THROTTLING("false")
78 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
79 DRI_CONF_FORCE_GLSL_VERSION(0)
80 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
81 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
82 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
83 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
84 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
85 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
86 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
87 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
89 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
90 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
94 DRI_CONF_SECTION_MISCELLANEOUS
95 DRI_CONF_GLSL_ZERO_INIT("false")
96 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
101 #include "intel_batchbuffer.h"
102 #include "intel_buffers.h"
103 #include "brw_bufmgr.h"
104 #include "intel_fbo.h"
105 #include "intel_mipmap_tree.h"
106 #include "intel_screen.h"
107 #include "intel_tex.h"
108 #include "intel_image.h"
110 #include "brw_context.h"
112 #include "i915_drm.h"
115 * For debugging purposes, this returns a time in seconds.
122 clock_gettime(CLOCK_MONOTONIC
, &tp
);
124 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
127 static const __DRItexBufferExtension intelTexBufferExtension
= {
128 .base
= { __DRI_TEX_BUFFER
, 3 },
130 .setTexBuffer
= intelSetTexBuffer
,
131 .setTexBuffer2
= intelSetTexBuffer2
,
132 .releaseTexBuffer
= NULL
,
136 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
137 __DRIdrawable
*dPriv
,
139 enum __DRI2throttleReason reason
)
141 struct brw_context
*brw
= cPriv
->driverPrivate
;
146 struct gl_context
*ctx
= &brw
->ctx
;
148 FLUSH_VERTICES(ctx
, 0);
150 if (flags
& __DRI2_FLUSH_DRAWABLE
)
151 intel_resolve_for_dri2_flush(brw
, dPriv
);
153 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
154 brw
->need_swap_throttle
= true;
155 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
156 brw
->need_flush_throttle
= true;
158 intel_batchbuffer_flush(brw
);
162 * Provides compatibility with loaders that only support the older (version
163 * 1-3) flush interface.
165 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
168 intel_dri2_flush(__DRIdrawable
*drawable
)
170 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
171 __DRI2_FLUSH_DRAWABLE
,
172 __DRI2_THROTTLE_SWAPBUFFER
);
175 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
176 .base
= { __DRI2_FLUSH
, 4 },
178 .flush
= intel_dri2_flush
,
179 .invalidate
= dri2InvalidateDrawable
,
180 .flush_with_flags
= intel_dri2_flush_with_flags
,
183 static const struct intel_image_format intel_image_formats
[] = {
184 { __DRI_IMAGE_FOURCC_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
185 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
187 { __DRI_IMAGE_FOURCC_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
188 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
190 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
191 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
193 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
194 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
196 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
197 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
199 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
200 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
202 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
203 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
205 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
206 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
208 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
209 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
211 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
212 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
214 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
215 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
217 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
218 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
220 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
221 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
223 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
224 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
225 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
226 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
228 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
229 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
230 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
231 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
233 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
235 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
236 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
238 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
239 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
240 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
241 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
243 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
244 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
246 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
248 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
249 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
251 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
253 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
254 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
256 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
258 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
259 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
261 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
263 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
264 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
266 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
268 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
269 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
271 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
273 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
274 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
275 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
277 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
278 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
279 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
281 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
282 * and treat them as planar buffers in the compositors.
283 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
284 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
285 * clusters and places pairs and places U into the G component and
286 * V into A. This lets the texture sampler interpolate the Y
287 * components correctly when sampling from plane 0, and interpolate
288 * U and V correctly when sampling from plane 1. */
289 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
290 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
291 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
292 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
293 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
294 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
297 static const struct {
300 } supported_modifiers
[] = {
301 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
302 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
303 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
304 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
308 modifier_is_supported(const struct gen_device_info
*devinfo
,
309 const struct intel_image_format
*fmt
, int dri_format
,
312 const struct isl_drm_modifier_info
*modinfo
=
313 isl_drm_modifier_get_info(modifier
);
316 /* ISL had better know about the modifier */
320 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
321 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
322 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
325 /* CCS_E is not supported for planar images */
326 if (fmt
&& fmt
->nplanes
> 1)
330 assert(dri_format
== 0);
331 dri_format
= fmt
->planes
[0].dri_format
;
334 mesa_format format
= driImageFormatToGLFormat(dri_format
);
335 format
= _mesa_get_srgb_format_linear(format
);
336 if (!isl_format_supports_ccs_e(devinfo
,
337 brw_isl_format_for_mesa_format(format
)))
341 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
342 if (supported_modifiers
[i
].modifier
!= modifier
)
345 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
352 tiling_to_modifier(uint32_t tiling
)
354 static const uint64_t map
[] = {
355 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
356 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
357 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
360 assert(tiling
< ARRAY_SIZE(map
));
366 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
368 uint32_t tiling
, swizzle
;
369 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
371 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
372 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
373 func
, image
->offset
);
377 static const struct intel_image_format
*
378 intel_image_format_lookup(int fourcc
)
380 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
381 if (intel_image_formats
[i
].fourcc
== fourcc
)
382 return &intel_image_formats
[i
];
388 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
390 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
391 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
392 *fourcc
= intel_image_formats
[i
].fourcc
;
400 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
405 image
= calloc(1, sizeof *image
);
409 image
->screen
= screen
;
410 image
->dri_format
= dri_format
;
413 image
->format
= driImageFormatToGLFormat(dri_format
);
414 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
415 image
->format
== MESA_FORMAT_NONE
) {
420 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
421 image
->data
= loaderPrivate
;
427 * Sets up a DRIImage structure to point to a slice out of a miptree.
430 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
431 struct intel_mipmap_tree
*mt
, GLuint level
,
434 intel_miptree_make_shareable(brw
, mt
);
436 intel_miptree_check_level_layer(mt
, level
, zoffset
);
438 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
439 level
- mt
->first_level
);
440 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
441 level
- mt
->first_level
);
442 image
->pitch
= mt
->surf
.row_pitch
;
444 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
448 brw_bo_unreference(image
->bo
);
450 brw_bo_reference(mt
->bo
);
454 intel_create_image_from_name(__DRIscreen
*dri_screen
,
455 int width
, int height
, int format
,
456 int name
, int pitch
, void *loaderPrivate
)
458 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
462 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
466 if (image
->format
== MESA_FORMAT_NONE
)
469 cpp
= _mesa_get_format_bytes(image
->format
);
471 image
->width
= width
;
472 image
->height
= height
;
473 image
->pitch
= pitch
* cpp
;
474 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
480 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
486 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
487 int renderbuffer
, void *loaderPrivate
)
490 struct brw_context
*brw
= context
->driverPrivate
;
491 struct gl_context
*ctx
= &brw
->ctx
;
492 struct gl_renderbuffer
*rb
;
493 struct intel_renderbuffer
*irb
;
495 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
497 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
501 irb
= intel_renderbuffer(rb
);
502 intel_miptree_make_shareable(brw
, irb
->mt
);
503 image
= calloc(1, sizeof *image
);
507 image
->internal_format
= rb
->InternalFormat
;
508 image
->format
= rb
->Format
;
509 image
->modifier
= tiling_to_modifier(
510 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
512 image
->data
= loaderPrivate
;
513 brw_bo_unreference(image
->bo
);
514 image
->bo
= irb
->mt
->bo
;
515 brw_bo_reference(irb
->mt
->bo
);
516 image
->width
= rb
->Width
;
517 image
->height
= rb
->Height
;
518 image
->pitch
= irb
->mt
->surf
.row_pitch
;
519 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
520 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
522 rb
->NeedsFinishRenderTexture
= true;
527 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
528 unsigned texture
, int zoffset
,
534 struct brw_context
*brw
= context
->driverPrivate
;
535 struct gl_texture_object
*obj
;
536 struct intel_texture_object
*iobj
;
539 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
540 if (!obj
|| obj
->Target
!= target
) {
541 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
545 if (target
== GL_TEXTURE_CUBE_MAP
)
548 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
549 iobj
= intel_texture_object(obj
);
550 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
551 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
555 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
556 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
560 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
561 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
564 image
= calloc(1, sizeof *image
);
566 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
570 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
571 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
572 image
->modifier
= tiling_to_modifier(
573 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
574 image
->data
= loaderPrivate
;
575 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
576 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
577 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
578 if (image
->dri_format
== MESA_FORMAT_NONE
) {
579 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
584 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
589 intel_destroy_image(__DRIimage
*image
)
591 brw_bo_unreference(image
->bo
);
595 enum modifier_priority
{
596 MODIFIER_PRIORITY_INVALID
= 0,
597 MODIFIER_PRIORITY_LINEAR
,
600 MODIFIER_PRIORITY_Y_CCS
,
603 const uint64_t priority_to_modifier
[] = {
604 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
605 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
606 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
607 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
608 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
612 select_best_modifier(struct gen_device_info
*devinfo
,
614 const uint64_t *modifiers
,
615 const unsigned count
)
617 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
619 for (int i
= 0; i
< count
; i
++) {
620 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
623 switch (modifiers
[i
]) {
624 case I915_FORMAT_MOD_Y_TILED_CCS
:
625 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
627 case I915_FORMAT_MOD_Y_TILED
:
628 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
630 case I915_FORMAT_MOD_X_TILED
:
631 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
633 case DRM_FORMAT_MOD_LINEAR
:
634 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
636 case DRM_FORMAT_MOD_INVALID
:
642 return priority_to_modifier
[prio
];
646 intel_create_image_common(__DRIscreen
*dri_screen
,
647 int width
, int height
, int format
,
649 const uint64_t *modifiers
,
654 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
655 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
658 /* Callers of this may specify a modifier, or a dri usage, but not both. The
659 * newer modifier interface deprecates the older usage flags newer modifier
660 * interface deprecates the older usage flags.
662 assert(!(use
&& count
));
664 if (use
& __DRI_IMAGE_USE_CURSOR
) {
665 if (width
!= 64 || height
!= 64)
667 modifier
= DRM_FORMAT_MOD_LINEAR
;
670 if (use
& __DRI_IMAGE_USE_LINEAR
)
671 modifier
= DRM_FORMAT_MOD_LINEAR
;
673 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
675 /* User requested specific modifiers */
676 modifier
= select_best_modifier(&screen
->devinfo
, format
,
678 if (modifier
== DRM_FORMAT_MOD_INVALID
)
681 /* Historically, X-tiled was the default, and so lack of modifier means
684 modifier
= I915_FORMAT_MOD_X_TILED
;
688 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
692 const struct isl_drm_modifier_info
*mod_info
=
693 isl_drm_modifier_get_info(modifier
);
695 struct isl_surf surf
;
696 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
697 .dim
= ISL_SURF_DIM_2D
,
698 .format
= brw_isl_format_for_mesa_format(image
->format
),
705 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
706 ISL_SURF_USAGE_TEXTURE_BIT
|
707 ISL_SURF_USAGE_STORAGE_BIT
,
708 .tiling_flags
= (1 << mod_info
->tiling
));
715 struct isl_surf aux_surf
;
716 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
717 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, 0);
723 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
727 /* We request that the bufmgr zero the buffer for us for two reasons:
729 * 1) If a buffer gets re-used from the pool, we don't want to leak random
730 * garbage from our process to some other.
732 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
733 * a valid state. A CCS value of 0 indicates that the given block is
734 * in the pass-through state which is what we want.
736 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
737 surf
.size
+ aux_surf
.size
,
738 isl_tiling_to_i915_tiling(mod_info
->tiling
),
739 surf
.row_pitch
, BO_ALLOC_ZEROED
);
740 if (image
->bo
== NULL
) {
744 image
->width
= width
;
745 image
->height
= height
;
746 image
->pitch
= surf
.row_pitch
;
747 image
->modifier
= modifier
;
750 image
->aux_offset
= surf
.size
;
751 image
->aux_pitch
= aux_surf
.row_pitch
;
758 intel_create_image(__DRIscreen
*dri_screen
,
759 int width
, int height
, int format
,
763 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
768 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
769 int x0
, int y0
, int width
, int height
,
770 unsigned int flags
, int *stride
, void **map_info
)
772 struct brw_context
*brw
= NULL
;
773 struct brw_bo
*bo
= NULL
;
774 void *raw_data
= NULL
;
779 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
782 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
785 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
788 if (flags
& MAP_INTERNAL_MASK
)
791 brw
= context
->driverPrivate
;
797 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
798 raw_data
= brw_bo_map(brw
, bo
, flags
);
802 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
803 pix_bytes
= _mesa_get_format_bytes(image
->format
);
807 assert(pix_bytes
> 0);
809 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
811 brw_bo_reference(bo
);
813 *stride
= image
->pitch
;
820 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
822 struct brw_bo
*bo
= map_info
;
825 brw_bo_unreference(bo
);
829 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
830 int width
, int height
, int format
,
831 const uint64_t *modifiers
,
832 const unsigned count
,
835 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
836 modifiers
, count
, loaderPrivate
);
840 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
843 case __DRI_IMAGE_ATTRIB_STRIDE
:
844 *value
= image
->pitch
;
846 case __DRI_IMAGE_ATTRIB_HANDLE
:
847 *value
= brw_bo_export_gem_handle(image
->bo
);
849 case __DRI_IMAGE_ATTRIB_NAME
:
850 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
851 case __DRI_IMAGE_ATTRIB_FORMAT
:
852 *value
= image
->dri_format
;
854 case __DRI_IMAGE_ATTRIB_WIDTH
:
855 *value
= image
->width
;
857 case __DRI_IMAGE_ATTRIB_HEIGHT
:
858 *value
= image
->height
;
860 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
861 if (image
->planar_format
== NULL
)
863 *value
= image
->planar_format
->components
;
865 case __DRI_IMAGE_ATTRIB_FD
:
866 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
867 case __DRI_IMAGE_ATTRIB_FOURCC
:
868 return intel_lookup_fourcc(image
->dri_format
, value
);
869 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
870 if (isl_drm_modifier_has_aux(image
->modifier
)) {
871 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
873 } else if (image
->planar_format
) {
874 *value
= image
->planar_format
->nplanes
;
879 case __DRI_IMAGE_ATTRIB_OFFSET
:
880 *value
= image
->offset
;
882 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
883 *value
= (image
->modifier
& 0xffffffff);
885 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
886 *value
= ((image
->modifier
>> 32) & 0xffffffff);
895 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
896 uint32_t fourcc
, uint64_t modifier
,
897 int attrib
, uint64_t *value
)
899 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
900 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
902 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
906 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
907 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
916 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
920 image
= calloc(1, sizeof *image
);
924 brw_bo_reference(orig_image
->bo
);
925 image
->bo
= orig_image
->bo
;
926 image
->internal_format
= orig_image
->internal_format
;
927 image
->planar_format
= orig_image
->planar_format
;
928 image
->dri_format
= orig_image
->dri_format
;
929 image
->format
= orig_image
->format
;
930 image
->modifier
= orig_image
->modifier
;
931 image
->offset
= orig_image
->offset
;
932 image
->width
= orig_image
->width
;
933 image
->height
= orig_image
->height
;
934 image
->pitch
= orig_image
->pitch
;
935 image
->tile_x
= orig_image
->tile_x
;
936 image
->tile_y
= orig_image
->tile_y
;
937 image
->has_depthstencil
= orig_image
->has_depthstencil
;
938 image
->data
= loaderPrivate
;
939 image
->dma_buf_imported
= orig_image
->dma_buf_imported
;
940 image
->aux_offset
= orig_image
->aux_offset
;
941 image
->aux_pitch
= orig_image
->aux_pitch
;
943 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
944 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
950 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
952 if (use
& __DRI_IMAGE_USE_CURSOR
) {
953 if (image
->width
!= 64 || image
->height
!= 64)
961 intel_create_image_from_names(__DRIscreen
*dri_screen
,
962 int width
, int height
, int fourcc
,
963 int *names
, int num_names
,
964 int *strides
, int *offsets
,
967 const struct intel_image_format
*f
= NULL
;
971 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
974 f
= intel_image_format_lookup(fourcc
);
978 image
= intel_create_image_from_name(dri_screen
, width
, height
,
979 __DRI_IMAGE_FORMAT_NONE
,
980 names
[0], strides
[0],
986 image
->planar_format
= f
;
987 for (i
= 0; i
< f
->nplanes
; i
++) {
988 index
= f
->planes
[i
].buffer_index
;
989 image
->offsets
[index
] = offsets
[index
];
990 image
->strides
[index
] = strides
[index
];
997 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
998 int width
, int height
, int fourcc
,
999 uint64_t modifier
, int *fds
, int num_fds
,
1000 int *strides
, int *offsets
,
1001 void *loaderPrivate
)
1003 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1004 const struct intel_image_format
*f
;
1009 if (fds
== NULL
|| num_fds
< 1)
1012 f
= intel_image_format_lookup(fourcc
);
1016 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1017 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1020 if (f
->nplanes
== 1)
1021 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1024 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1030 image
->width
= width
;
1031 image
->height
= height
;
1032 image
->pitch
= strides
[0];
1034 image
->planar_format
= f
;
1036 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1037 const struct isl_drm_modifier_info
*mod_info
=
1038 isl_drm_modifier_get_info(modifier
);
1039 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1040 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1041 tiling
, strides
[0]);
1043 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1046 if (image
->bo
== NULL
) {
1051 /* We only support all planes from the same bo.
1052 * brw_bo_gem_create_from_prime() should return the same pointer for all
1053 * fds received here */
1054 for (i
= 1; i
< num_fds
; i
++) {
1055 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1056 brw_bo_unreference(aux
);
1057 if (aux
!= image
->bo
) {
1058 brw_bo_unreference(image
->bo
);
1064 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1065 image
->modifier
= modifier
;
1067 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1069 const struct isl_drm_modifier_info
*mod_info
=
1070 isl_drm_modifier_get_info(image
->modifier
);
1073 struct isl_surf surf
;
1074 for (i
= 0; i
< f
->nplanes
; i
++) {
1075 index
= f
->planes
[i
].buffer_index
;
1076 image
->offsets
[index
] = offsets
[index
];
1077 image
->strides
[index
] = strides
[index
];
1079 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1081 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1082 .dim
= ISL_SURF_DIM_2D
,
1083 .format
= brw_isl_format_for_mesa_format(format
),
1084 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1085 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1090 .row_pitch
= strides
[index
],
1091 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1092 ISL_SURF_USAGE_TEXTURE_BIT
|
1093 ISL_SURF_USAGE_STORAGE_BIT
,
1094 .tiling_flags
= (1 << mod_info
->tiling
));
1096 brw_bo_unreference(image
->bo
);
1101 const int end
= offsets
[index
] + surf
.size
;
1106 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1107 /* Even though we initialize surf in the loop above, we know that
1108 * anything with CCS_E will have exactly one plane so surf is properly
1109 * initialized when we get here.
1111 assert(f
->nplanes
== 1);
1113 image
->aux_offset
= offsets
[1];
1114 image
->aux_pitch
= strides
[1];
1116 /* Scanout hardware requires that the CCS be placed after the main
1117 * surface in memory. We consider any CCS that is placed any earlier in
1118 * memory to be invalid and reject it.
1120 * At some point in the future, this restriction may be relaxed if the
1121 * hardware becomes less strict but we may need a new modifier for that.
1124 if (image
->aux_offset
< size
) {
1125 brw_bo_unreference(image
->bo
);
1130 struct isl_surf aux_surf
;
1131 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
,
1134 brw_bo_unreference(image
->bo
);
1139 const int end
= image
->aux_offset
+ aux_surf
.size
;
1143 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1146 /* Check that the requested image actually fits within the BO. 'size'
1147 * is already relative to the offsets, so we don't need to add that. */
1148 if (image
->bo
->size
== 0) {
1149 image
->bo
->size
= size
;
1150 } else if (size
> image
->bo
->size
) {
1151 brw_bo_unreference(image
->bo
);
1156 if (f
->nplanes
== 1) {
1157 image
->offset
= image
->offsets
[0];
1158 intel_image_warn_if_unaligned(image
, __func__
);
1165 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1166 int width
, int height
, int fourcc
,
1167 int *fds
, int num_fds
, int *strides
, int *offsets
,
1168 void *loaderPrivate
)
1170 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1171 DRM_FORMAT_MOD_INVALID
,
1172 fds
, num_fds
, strides
, offsets
,
1177 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1178 int width
, int height
,
1179 int fourcc
, uint64_t modifier
,
1180 int *fds
, int num_fds
,
1181 int *strides
, int *offsets
,
1182 enum __DRIYUVColorSpace yuv_color_space
,
1183 enum __DRISampleRange sample_range
,
1184 enum __DRIChromaSiting horizontal_siting
,
1185 enum __DRIChromaSiting vertical_siting
,
1187 void *loaderPrivate
)
1190 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1193 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1197 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1199 fds
, num_fds
, strides
, offsets
,
1203 * Invalid parameters and any inconsistencies between are assumed to be
1204 * checked by the caller. Therefore besides unsupported formats one can fail
1205 * only in allocation.
1208 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1212 image
->dma_buf_imported
= true;
1213 image
->yuv_color_space
= yuv_color_space
;
1214 image
->sample_range
= sample_range
;
1215 image
->horizontal_siting
= horizontal_siting
;
1216 image
->vertical_siting
= vertical_siting
;
1218 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1223 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1224 int width
, int height
, int fourcc
,
1225 int *fds
, int num_fds
,
1226 int *strides
, int *offsets
,
1227 enum __DRIYUVColorSpace yuv_color_space
,
1228 enum __DRISampleRange sample_range
,
1229 enum __DRIChromaSiting horizontal_siting
,
1230 enum __DRIChromaSiting vertical_siting
,
1232 void *loaderPrivate
)
1234 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1235 fourcc
, DRM_FORMAT_MOD_INVALID
,
1236 fds
, num_fds
, strides
, offsets
,
1246 intel_query_dma_buf_formats(__DRIscreen
*screen
, int max
,
1247 int *formats
, int *count
)
1252 *count
= ARRAY_SIZE(intel_image_formats
) - 1; /* not SARGB */
1256 for (i
= 0; i
< (ARRAY_SIZE(intel_image_formats
)) && j
< max
; i
++) {
1257 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
)
1259 formats
[j
++] = intel_image_formats
[i
].fourcc
;
1267 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1268 uint64_t *modifiers
,
1269 unsigned int *external_only
,
1272 struct intel_screen
*screen
= _screen
->driverPrivate
;
1273 const struct intel_image_format
*f
;
1274 int num_mods
= 0, i
;
1276 f
= intel_image_format_lookup(fourcc
);
1280 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1281 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1282 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1289 modifiers
[num_mods
- 1] = modifier
;
1290 if (num_mods
>= max
)
1294 if (external_only
!= NULL
) {
1295 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1296 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1297 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1298 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1299 external_only
[i
] = GL_TRUE
;
1302 external_only
[i
] = GL_FALSE
;
1312 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1314 int width
, height
, offset
, stride
, dri_format
, index
;
1315 const struct intel_image_format
*f
;
1318 if (parent
== NULL
) {
1320 } else if (parent
->planar_format
== NULL
) {
1322 isl_drm_modifier_has_aux(parent
->modifier
) && plane
== 1;
1326 width
= parent
->width
;
1327 height
= parent
->height
;
1328 dri_format
= parent
->dri_format
;
1329 offset
= parent
->aux_offset
;
1330 stride
= parent
->aux_pitch
;
1332 /* Planar formats don't support aux buffers/images */
1333 assert(!isl_drm_modifier_has_aux(parent
->modifier
));
1334 f
= parent
->planar_format
;
1336 if (plane
>= f
->nplanes
)
1339 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
1340 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
1341 dri_format
= f
->planes
[plane
].dri_format
;
1342 index
= f
->planes
[plane
].buffer_index
;
1343 offset
= parent
->offsets
[index
];
1344 stride
= parent
->strides
[index
];
1346 if (offset
+ height
* stride
> parent
->bo
->size
) {
1347 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
1352 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1356 image
->bo
= parent
->bo
;
1357 brw_bo_reference(parent
->bo
);
1358 image
->modifier
= parent
->modifier
;
1360 image
->width
= width
;
1361 image
->height
= height
;
1362 image
->pitch
= stride
;
1363 image
->offset
= offset
;
1365 intel_image_warn_if_unaligned(image
, __func__
);
1370 static const __DRIimageExtension intelImageExtension
= {
1371 .base
= { __DRI_IMAGE
, 16 },
1373 .createImageFromName
= intel_create_image_from_name
,
1374 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1375 .destroyImage
= intel_destroy_image
,
1376 .createImage
= intel_create_image
,
1377 .queryImage
= intel_query_image
,
1378 .dupImage
= intel_dup_image
,
1379 .validateUsage
= intel_validate_usage
,
1380 .createImageFromNames
= intel_create_image_from_names
,
1381 .fromPlanar
= intel_from_planar
,
1382 .createImageFromTexture
= intel_create_image_from_texture
,
1383 .createImageFromFds
= intel_create_image_from_fds
,
1384 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1386 .getCapabilities
= NULL
,
1387 .mapImage
= intel_map_image
,
1388 .unmapImage
= intel_unmap_image
,
1389 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1390 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1391 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1392 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1393 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1397 get_aperture_size(int fd
)
1399 struct drm_i915_gem_get_aperture aperture
;
1401 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1404 return aperture
.aper_size
;
1408 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1409 int param
, unsigned int *value
)
1411 const struct intel_screen
*const screen
=
1412 (struct intel_screen
*) dri_screen
->driverPrivate
;
1415 case __DRI2_RENDERER_VENDOR_ID
:
1418 case __DRI2_RENDERER_DEVICE_ID
:
1419 value
[0] = screen
->deviceID
;
1421 case __DRI2_RENDERER_ACCELERATED
:
1424 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1425 /* Once a batch uses more than 75% of the maximum mappable size, we
1426 * assume that there's some fragmentation, and we start doing extra
1427 * flushing, etc. That's the big cliff apps will care about.
1429 const unsigned gpu_mappable_megabytes
=
1430 screen
->aperture_threshold
/ (1024 * 1024);
1432 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1433 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1435 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1438 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1439 * (uint64_t) system_page_size
;
1441 const unsigned system_memory_megabytes
=
1442 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1444 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1447 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1450 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1453 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1455 if (brw_hw_context_set_priority(screen
->bufmgr
,
1456 0, BRW_CONTEXT_HIGH_PRIORITY
) == 0)
1457 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1458 if (brw_hw_context_set_priority(screen
->bufmgr
,
1459 0, BRW_CONTEXT_LOW_PRIORITY
) == 0)
1460 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1461 /* reset to default last, just in case */
1462 if (brw_hw_context_set_priority(screen
->bufmgr
,
1463 0, BRW_CONTEXT_MEDIUM_PRIORITY
) == 0)
1464 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1466 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1470 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1477 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1478 int param
, const char **value
)
1480 const struct intel_screen
*screen
=
1481 (struct intel_screen
*) dri_screen
->driverPrivate
;
1484 case __DRI2_RENDERER_VENDOR_ID
:
1485 value
[0] = brw_vendor_string
;
1487 case __DRI2_RENDERER_DEVICE_ID
:
1488 value
[0] = brw_get_renderer_string(screen
);
1497 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1498 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1500 .queryInteger
= brw_query_renderer_integer
,
1501 .queryString
= brw_query_renderer_string
1504 static const __DRIrobustnessExtension dri2Robustness
= {
1505 .base
= { __DRI2_ROBUSTNESS
, 1 }
1508 static const __DRIextension
*screenExtensions
[] = {
1509 &intelTexBufferExtension
.base
,
1510 &intelFenceExtension
.base
,
1511 &intelFlushExtension
.base
,
1512 &intelImageExtension
.base
,
1513 &intelRendererQueryExtension
.base
,
1514 &dri2ConfigQueryExtension
.base
,
1515 &dri2NoErrorExtension
.base
,
1519 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1520 &intelTexBufferExtension
.base
,
1521 &intelFenceExtension
.base
,
1522 &intelFlushExtension
.base
,
1523 &intelImageExtension
.base
,
1524 &intelRendererQueryExtension
.base
,
1525 &dri2ConfigQueryExtension
.base
,
1526 &dri2Robustness
.base
,
1527 &dri2NoErrorExtension
.base
,
1532 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1535 struct drm_i915_getparam gp
;
1537 memset(&gp
, 0, sizeof(gp
));
1541 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1544 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1551 intel_get_boolean(struct intel_screen
*screen
, int param
)
1554 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1558 intel_get_integer(struct intel_screen
*screen
, int param
)
1562 if (intel_get_param(screen
, param
, &value
) == 0)
1569 intelDestroyScreen(__DRIscreen
* sPriv
)
1571 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1573 brw_bufmgr_destroy(screen
->bufmgr
);
1574 driDestroyOptionInfo(&screen
->optionCache
);
1576 disk_cache_destroy(screen
->disk_cache
);
1578 ralloc_free(screen
);
1579 sPriv
->driverPrivate
= NULL
;
1584 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1586 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1587 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1588 * this does not allocate GPU memory.
1591 intelCreateBuffer(__DRIscreen
*dri_screen
,
1592 __DRIdrawable
* driDrawPriv
,
1593 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1595 struct intel_renderbuffer
*rb
;
1596 struct intel_screen
*screen
= (struct intel_screen
*)
1597 dri_screen
->driverPrivate
;
1598 mesa_format rgbFormat
;
1599 unsigned num_samples
=
1600 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1605 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1609 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1611 if (screen
->winsys_msaa_samples_override
!= -1) {
1612 num_samples
= screen
->winsys_msaa_samples_override
;
1613 fb
->Visual
.samples
= num_samples
;
1616 if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1617 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1618 : MESA_FORMAT_R10G10B10A2_UNORM
;
1619 } else if (mesaVis
->redBits
== 10) {
1620 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1621 : MESA_FORMAT_R10G10B10X2_UNORM
;
1622 } else if (mesaVis
->redBits
== 5) {
1623 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1624 : MESA_FORMAT_B5G6R5_UNORM
;
1625 } else if (mesaVis
->sRGBCapable
) {
1626 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1627 : MESA_FORMAT_B8G8R8A8_SRGB
;
1628 } else if (mesaVis
->alphaBits
== 0) {
1629 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1630 : MESA_FORMAT_B8G8R8X8_UNORM
;
1632 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1633 : MESA_FORMAT_B8G8R8A8_SRGB
;
1634 fb
->Visual
.sRGBCapable
= true;
1637 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1638 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1640 /* setup the hardware-based renderbuffers */
1641 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1642 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1643 rb
->need_srgb
= srgb_cap_set
;
1645 if (mesaVis
->doubleBufferMode
) {
1646 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1647 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1648 rb
->need_srgb
= srgb_cap_set
;
1652 * Assert here that the gl_config has an expected depth/stencil bit
1653 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1654 * which constructs the advertised configs.)
1656 if (mesaVis
->depthBits
== 24) {
1657 assert(mesaVis
->stencilBits
== 8);
1659 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1660 rb
= intel_create_private_renderbuffer(screen
,
1661 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1663 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1664 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1666 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1669 * Use combined depth/stencil. Note that the renderbuffer is
1670 * attached to two attachment points.
1672 rb
= intel_create_private_renderbuffer(screen
,
1673 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1675 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1676 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1679 else if (mesaVis
->depthBits
== 16) {
1680 assert(mesaVis
->stencilBits
== 0);
1681 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1683 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1686 assert(mesaVis
->depthBits
== 0);
1687 assert(mesaVis
->stencilBits
== 0);
1690 /* now add any/all software-based renderbuffers we may need */
1691 _swrast_add_soft_renderbuffers(fb
,
1692 false, /* never sw color */
1693 false, /* never sw depth */
1694 false, /* never sw stencil */
1695 mesaVis
->accumRedBits
> 0,
1696 false, /* never sw alpha */
1697 false /* never sw aux */ );
1698 driDrawPriv
->driverPrivate
= fb
;
1704 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1706 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1708 _mesa_reference_framebuffer(&fb
, NULL
);
1712 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1714 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1715 * gen10, PCI-id is enough to figure it out.
1717 assert(screen
->devinfo
.gen
>= 10);
1721 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1725 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1729 screen
->devinfo
.timestamp_frequency
= freq
;
1733 intel_detect_sseu(struct intel_screen
*screen
)
1735 assert(screen
->devinfo
.gen
>= 8);
1738 screen
->subslice_total
= -1;
1739 screen
->eu_total
= -1;
1741 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1742 &screen
->subslice_total
);
1743 if (ret
< 0 && ret
!= -EINVAL
)
1746 ret
= intel_get_param(screen
,
1747 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1748 if (ret
< 0 && ret
!= -EINVAL
)
1751 /* Without this information, we cannot get the right Braswell brandstrings,
1752 * and we have to use conservative numbers for GPGPU on many platforms, but
1753 * otherwise, things will just work.
1755 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1757 "Kernel 4.1 required to properly query GPU properties.\n");
1762 screen
->subslice_total
= -1;
1763 screen
->eu_total
= -1;
1764 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1768 intel_init_bufmgr(struct intel_screen
*screen
)
1770 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1772 if (getenv("INTEL_NO_HW") != NULL
)
1773 screen
->no_hw
= true;
1775 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
);
1776 if (screen
->bufmgr
== NULL
) {
1777 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1778 __func__
, __LINE__
);
1782 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1783 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1791 intel_detect_swizzling(struct intel_screen
*screen
)
1793 struct brw_bo
*buffer
;
1795 uint32_t aligned_pitch
;
1796 uint32_t tiling
= I915_TILING_X
;
1797 uint32_t swizzle_mode
= 0;
1799 buffer
= brw_bo_alloc_tiled_2d(screen
->bufmgr
, "swizzle test",
1800 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1804 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1805 brw_bo_unreference(buffer
);
1807 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1814 intel_detect_timestamp(struct intel_screen
*screen
)
1816 uint64_t dummy
= 0, last
= 0;
1817 int upper
, lower
, loops
;
1819 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1820 * TIMESTAMP register being shifted and the low 32bits always zero.
1822 * More recent kernels offer an interface to read the full 36bits
1825 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1828 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1829 * upper 32bits for a rapidly changing timestamp.
1831 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1835 for (loops
= 0; loops
< 10; loops
++) {
1836 /* The TIMESTAMP should change every 80ns, so several round trips
1837 * through the kernel should be enough to advance it.
1839 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1842 upper
+= (dummy
>> 32) != (last
>> 32);
1843 if (upper
> 1) /* beware 32bit counter overflow */
1844 return 2; /* upper dword holds the low 32bits of the timestamp */
1846 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1848 return 1; /* timestamp is unshifted */
1853 /* No advancement? No timestamp! */
1858 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1860 * Some combinations of hardware and kernel versions allow this feature,
1861 * while others don't. Instead of trying to enumerate every case, just
1862 * try and write a register and see if works.
1865 intel_detect_pipelined_register(struct intel_screen
*screen
,
1866 int reg
, uint32_t expected_value
, bool reset
)
1871 struct brw_bo
*results
, *bo
;
1873 uint32_t offset
= 0;
1875 bool success
= false;
1877 /* Create a zero'ed temporary buffer for reading our results */
1878 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1879 if (results
== NULL
)
1882 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1886 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
1892 /* Write the register. */
1893 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1895 *batch
++ = expected_value
;
1897 /* Save the register's value back to the buffer. */
1898 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1900 struct drm_i915_gem_relocation_entry reloc
= {
1901 .offset
= (char *) batch
- (char *) map
,
1902 .delta
= offset
* sizeof(uint32_t),
1903 .target_handle
= results
->gem_handle
,
1904 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1905 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1907 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1909 /* And afterwards clear the register */
1911 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1916 *batch
++ = MI_BATCH_BUFFER_END
;
1918 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1920 .handle
= results
->gem_handle
,
1923 .handle
= bo
->gem_handle
,
1924 .relocation_count
= 1,
1925 .relocs_ptr
= (uintptr_t) &reloc
,
1929 struct drm_i915_gem_execbuffer2 execbuf
= {
1930 .buffers_ptr
= (uintptr_t) exec_objects
,
1932 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
1933 .flags
= I915_EXEC_RENDER
,
1936 /* Don't bother with error checking - if the execbuf fails, the
1937 * value won't be written and we'll just report that there's no access.
1939 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1940 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1942 /* Check whether the value got written. */
1943 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
1945 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
1946 brw_bo_unmap(results
);
1950 brw_bo_unreference(bo
);
1952 brw_bo_unreference(results
);
1958 intel_detect_pipelined_so(struct intel_screen
*screen
)
1960 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1962 /* Supposedly, Broadwell just works. */
1963 if (devinfo
->gen
>= 8)
1966 if (devinfo
->gen
<= 6)
1969 /* See the big explanation about command parser versions below */
1970 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1973 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1974 * statistics registers), and we already reset it to zero before using it.
1976 return intel_detect_pipelined_register(screen
,
1977 GEN7_SO_WRITE_OFFSET(0),
1983 * Return array of MSAA modes supported by the hardware. The array is
1984 * zero-terminated and sorted in decreasing order.
1987 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1989 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1990 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1991 static const int gen7_modes
[] = {8, 4, 0, -1};
1992 static const int gen6_modes
[] = {4, 0, -1};
1993 static const int gen4_modes
[] = {0, -1};
1995 if (screen
->devinfo
.gen
>= 9) {
1997 } else if (screen
->devinfo
.gen
>= 8) {
1999 } else if (screen
->devinfo
.gen
>= 7) {
2001 } else if (screen
->devinfo
.gen
== 6) {
2009 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2011 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2012 dri_screen
->dri2
.loader
->getCapability
)
2013 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2015 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2016 dri_screen
->image
.loader
->getCapability
)
2017 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2022 static __DRIconfig
**
2023 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2025 static const mesa_format formats
[] = {
2026 MESA_FORMAT_B5G6R5_UNORM
,
2027 MESA_FORMAT_B8G8R8A8_UNORM
,
2028 MESA_FORMAT_B8G8R8X8_UNORM
,
2030 MESA_FORMAT_B8G8R8A8_SRGB
,
2032 /* For 10 bpc, 30 bit depth framebuffers. */
2033 MESA_FORMAT_B10G10R10A2_UNORM
,
2034 MESA_FORMAT_B10G10R10X2_UNORM
,
2036 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2037 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2038 * server may disagree on which format the GLXFBConfig represents,
2039 * resulting in swapped color channels.
2041 * The problem, as of 2017-05-30:
2042 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2043 * order and chooses the first __DRIconfig with the expected channel
2044 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2045 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2047 * EGL does not suffer from this problem. It correctly compares the
2048 * channel masks when matching EGLConfig to __DRIconfig.
2051 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2052 MESA_FORMAT_R8G8B8A8_UNORM
,
2054 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2055 MESA_FORMAT_R8G8B8X8_UNORM
,
2058 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
2059 static const GLenum back_buffer_modes
[] = {
2060 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2063 static const uint8_t singlesample_samples
[1] = {0};
2065 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2066 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2067 uint8_t depth_bits
[4], stencil_bits
[4];
2068 __DRIconfig
**configs
= NULL
;
2070 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2071 unsigned num_formats
;
2072 if (intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
))
2073 num_formats
= ARRAY_SIZE(formats
);
2075 num_formats
= ARRAY_SIZE(formats
) - 2; /* all - RGBA_ORDERING formats */
2077 /* Shall we expose 10 bpc formats? */
2078 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2079 "allow_rgb10_configs");
2081 /* Generate singlesample configs without accumulation buffer. */
2082 for (unsigned i
= 0; i
< num_formats
; i
++) {
2083 __DRIconfig
**new_configs
;
2084 int num_depth_stencil_bits
= 2;
2086 if (!allow_rgb10_configs
&&
2087 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2088 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2091 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2092 * buffer that has a different number of bits per pixel than the color
2093 * buffer, gen >= 6 supports this.
2096 stencil_bits
[0] = 0;
2098 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2100 stencil_bits
[1] = 0;
2101 if (devinfo
->gen
>= 6) {
2103 stencil_bits
[2] = 8;
2104 num_depth_stencil_bits
= 3;
2108 stencil_bits
[1] = 8;
2111 new_configs
= driCreateConfigs(formats
[i
],
2114 num_depth_stencil_bits
,
2115 back_buffer_modes
, 2,
2116 singlesample_samples
, 1,
2118 configs
= driConcatConfigs(configs
, new_configs
);
2121 /* Generate the minimum possible set of configs that include an
2122 * accumulation buffer.
2124 for (unsigned i
= 0; i
< num_formats
; i
++) {
2125 __DRIconfig
**new_configs
;
2127 if (!allow_rgb10_configs
&&
2128 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2129 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2132 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2134 stencil_bits
[0] = 0;
2137 stencil_bits
[0] = 8;
2140 new_configs
= driCreateConfigs(formats
[i
],
2141 depth_bits
, stencil_bits
, 1,
2142 back_buffer_modes
, 1,
2143 singlesample_samples
, 1,
2145 configs
= driConcatConfigs(configs
, new_configs
);
2148 /* Generate multisample configs.
2150 * This loop breaks early, and hence is a no-op, on gen < 6.
2152 * Multisample configs must follow the singlesample configs in order to
2153 * work around an X server bug present in 1.12. The X server chooses to
2154 * associate the first listed RGBA888-Z24S8 config, regardless of its
2155 * sample count, with the 32-bit depth visual used for compositing.
2157 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2158 * supported. Singlebuffer configs are not supported because no one wants
2161 for (unsigned i
= 0; i
< num_formats
; i
++) {
2162 if (devinfo
->gen
< 6)
2165 if (!allow_rgb10_configs
&&
2166 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2167 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2170 __DRIconfig
**new_configs
;
2171 const int num_depth_stencil_bits
= 2;
2172 int num_msaa_modes
= 0;
2173 const uint8_t *multisample_samples
= NULL
;
2176 stencil_bits
[0] = 0;
2178 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2180 stencil_bits
[1] = 0;
2183 stencil_bits
[1] = 8;
2186 if (devinfo
->gen
>= 9) {
2187 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2188 multisample_samples
= multisample_samples_gen9
;
2189 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2190 } else if (devinfo
->gen
== 8) {
2191 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2192 multisample_samples
= multisample_samples_gen8
;
2193 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2194 } else if (devinfo
->gen
== 7) {
2195 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2196 multisample_samples
= multisample_samples_gen7
;
2197 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2198 } else if (devinfo
->gen
== 6) {
2199 static const uint8_t multisample_samples_gen6
[] = {4};
2200 multisample_samples
= multisample_samples_gen6
;
2201 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2204 new_configs
= driCreateConfigs(formats
[i
],
2207 num_depth_stencil_bits
,
2208 back_buffer_modes
, 1,
2209 multisample_samples
,
2212 configs
= driConcatConfigs(configs
, new_configs
);
2215 if (configs
== NULL
) {
2216 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2225 set_max_gl_versions(struct intel_screen
*screen
)
2227 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2228 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2230 switch (screen
->devinfo
.gen
) {
2234 dri_screen
->max_gl_core_version
= 45;
2235 dri_screen
->max_gl_compat_version
= 30;
2236 dri_screen
->max_gl_es1_version
= 11;
2237 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2240 dri_screen
->max_gl_core_version
= 33;
2241 if (can_do_pipelined_register_writes(screen
)) {
2242 dri_screen
->max_gl_core_version
= 42;
2243 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2244 dri_screen
->max_gl_core_version
= 43;
2245 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2246 dri_screen
->max_gl_core_version
= 45;
2248 dri_screen
->max_gl_compat_version
= 30;
2249 dri_screen
->max_gl_es1_version
= 11;
2250 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2253 dri_screen
->max_gl_core_version
= 33;
2254 dri_screen
->max_gl_compat_version
= 30;
2255 dri_screen
->max_gl_es1_version
= 11;
2256 dri_screen
->max_gl_es2_version
= 30;
2260 dri_screen
->max_gl_core_version
= 0;
2261 dri_screen
->max_gl_compat_version
= 21;
2262 dri_screen
->max_gl_es1_version
= 11;
2263 dri_screen
->max_gl_es2_version
= 20;
2266 unreachable("unrecognized intel_screen::gen");
2271 * Return the revision (generally the revid field of the PCI header) of the
2275 intel_device_get_revision(int fd
)
2277 struct drm_i915_getparam gp
;
2281 memset(&gp
, 0, sizeof(gp
));
2282 gp
.param
= I915_PARAM_REVISION
;
2283 gp
.value
= &revision
;
2285 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
2293 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2295 struct brw_context
*brw
= (struct brw_context
*)data
;
2298 va_start(args
, fmt
);
2300 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2301 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2302 MESA_DEBUG_TYPE_OTHER
,
2303 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2308 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2310 struct brw_context
*brw
= (struct brw_context
*)data
;
2313 va_start(args
, fmt
);
2315 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2317 va_copy(args_copy
, args
);
2318 vfprintf(stderr
, fmt
, args_copy
);
2322 if (brw
->perf_debug
) {
2324 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2325 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2326 MESA_DEBUG_TYPE_PERFORMANCE
,
2327 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2333 parse_devid_override(const char *devid_override
)
2335 static const struct {
2355 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
2356 if (!strcmp(name_map
[i
].name
, devid_override
))
2357 return name_map
[i
].pci_id
;
2360 return strtol(devid_override
, NULL
, 0);
2364 * Get the PCI ID for the device. This can be overridden by setting the
2365 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2367 * Returns -1 on ioctl failure.
2370 get_pci_device_id(struct intel_screen
*screen
)
2372 if (geteuid() == getuid()) {
2373 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
2374 if (devid_override
) {
2375 screen
->no_hw
= true;
2376 return parse_devid_override(devid_override
);
2380 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2384 * This is the driver specific part of the createNewScreen entry point.
2385 * Called when using DRI2.
2387 * \return the struct gl_config supported by this driver
2390 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2392 struct intel_screen
*screen
;
2394 if (dri_screen
->image
.loader
) {
2395 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2396 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2398 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2399 "support required\n");
2403 /* Allocate the private area */
2404 screen
= rzalloc(NULL
, struct intel_screen
);
2406 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2409 /* parse information in __driConfigOptions */
2410 driOptionCache options
;
2411 memset(&options
, 0, sizeof(options
));
2413 driParseOptionInfo(&options
, brw_config_options
.xml
);
2414 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
, "i965");
2415 driDestroyOptionCache(&options
);
2417 screen
->driScrnPriv
= dri_screen
;
2418 dri_screen
->driverPrivate
= (void *) screen
;
2420 screen
->deviceID
= get_pci_device_id(screen
);
2422 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2425 if (!intel_init_bufmgr(screen
))
2428 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2430 brw_process_intel_debug_variable();
2432 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2434 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2435 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2438 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2439 /* Theorectically unlimited! At least for individual objects...
2441 * Currently the entire (global) address space for all GTT maps is
2442 * limited to 64bits. That is all objects on the system that are
2443 * setup for GTT mmapping must fit within 64bits. An attempt to use
2444 * one that exceeds the limit with fail in brw_bo_map_gtt().
2446 * Long before we hit that limit, we will be practically limited by
2447 * that any single object must fit in physical memory (RAM). The upper
2448 * limit on the CPU's address space is currently 48bits (Skylake), of
2449 * which only 39bits can be physical memory. (The GPU itself also has
2450 * a 48bit addressable virtual space.) We can fit over 32 million
2451 * objects of the current maximum allocable size before running out
2454 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2456 /* Estimate the size of the mappable aperture into the GTT. There's an
2457 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2458 * It turns out it's basically always 256MB, though some ancient hardware
2461 uint32_t gtt_size
= 256 * 1024 * 1024;
2463 /* We don't want to map two objects such that a memcpy between them would
2464 * just fault one mapping in and then the other over and over forever. So
2465 * we would need to divide the GTT size by 2. Additionally, some GTT is
2466 * taken up by things like the framebuffer and the ringbuffer and such, so
2467 * be more conservative.
2469 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2472 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2474 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2475 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2477 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2478 screen
->hw_has_swizzling
);
2480 if (devinfo
->gen
>= 10)
2481 intel_cs_timestamp_frequency(screen
);
2483 /* GENs prior to 8 do not support EU/Subslice info */
2484 if (devinfo
->gen
>= 8) {
2485 intel_detect_sseu(screen
);
2486 } else if (devinfo
->gen
== 7) {
2487 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2490 /* Gen7-7.5 kernel requirements / command parser saga:
2493 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2495 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2496 * all batches secure, allowing them to use any feature with no checking.
2497 * This is effectively equivalent to a command parser version of
2498 * \infinity - everything is possible.
2500 * The command parser does not exist, and querying the version will
2504 * The kernel enables the command parser by default, for systems with
2505 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2506 * hardware checker is still enabled, so Haswell and Baytrail cannot
2509 * Ivybridge goes from "everything is possible" to "only what the
2510 * command parser allows" (if the user boots with i915.cmd_parser=0,
2511 * then everything is possible again). We can only safely use features
2512 * allowed by the supported command parser version.
2514 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2515 * implemented by the kernel, even if it's turned off. So, checking
2516 * for version > 0 does not mean that you can write registers. We have
2517 * to try it and see. The version does, however, indicate the age of
2520 * Instead of matching the hardware checker's behavior of converting
2521 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2522 * -EINVAL, making it dangerous to try and use privileged features.
2524 * Effective command parser versions:
2525 * - Haswell: 0 (reporting 1, writes don't work)
2526 * - Baytrail: 0 (reporting 1, writes don't work)
2527 * - Ivybridge: 1 (enabled) or infinite (disabled)
2530 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2531 * effectively version 1 (enabled) or infinite (disabled).
2533 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2534 * Command parser v2 supports predicate writes.
2536 * - Haswell: 0 (reporting 1, writes don't work)
2537 * - Baytrail: 2 (enabled) or infinite (disabled)
2538 * - Ivybridge: 2 (enabled) or infinite (disabled)
2540 * So version >= 2 is enough to know that Ivybridge and Baytrail
2541 * will work. Haswell still can't do anything.
2543 * - v4.0: Version 3 happened. Largely not relevant.
2545 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2546 * L3 config registers are properly saved and restored as part
2547 * of the hardware context. We can approximately detect this point
2548 * in time by checking if I915_PARAM_REVISION is recognized - it
2549 * landed in a later commit, but in the same release cycle.
2551 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2552 * Command parser finally gains secure batch promotion. On Haswell,
2553 * the hardware checker gets disabled, which finally allows it to do
2554 * privileged commands.
2556 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2557 * - Haswell: 3 (enabled) or 0 (disabled)
2558 * - Baytrail: 3 (enabled) or infinite (disabled)
2559 * - Ivybridge: 3 (enabled) or infinite (disabled)
2561 * Unfortunately, detecting this point in time is tricky, because
2562 * no version bump happened when this important change occurred.
2563 * On Haswell, if we can write any register, then the kernel is at
2564 * least this new, and we can start trusting the version number.
2566 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2567 * Command parser reaches version 4, allowing access to Haswell
2568 * atomic scratch and chicken3 registers. If version >= 4, we know
2569 * the kernel is new enough to support privileged features on all
2570 * hardware. However, the user might have disabled it...and the
2571 * kernel will still report version 4. So we still have to guess
2574 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2575 * Command parser v5 whitelists indirect compute shader dispatch
2576 * registers, needed for OpenGL 4.3 and later.
2579 * Command parser v7 lets us use MI_MATH on Haswell.
2581 * Additionally, the kernel begins reporting version 0 when
2582 * the command parser is disabled, allowing us to skip the
2583 * guess-and-check step on Haswell. Unfortunately, this also
2584 * means that we can no longer use it as an indicator of the
2585 * age of the kernel.
2587 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2588 &screen
->cmd_parser_version
) < 0) {
2589 /* Command parser does not exist - getparam is unrecognized */
2590 screen
->cmd_parser_version
= 0;
2593 /* Kernel 4.13 retuired for exec object capture */
2594 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2595 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2598 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2599 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2602 if (!intel_detect_pipelined_so(screen
)) {
2603 /* We can't do anything, so the effective version is 0. */
2604 screen
->cmd_parser_version
= 0;
2606 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2609 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2610 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2612 /* Haswell requires command parser version 4 in order to have L3
2613 * atomic scratch1 and chicken3 bits
2615 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2616 screen
->kernel_features
|=
2617 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2620 /* Haswell requires command parser version 6 in order to write to the
2621 * MI_MATH GPR registers, and version 7 in order to use
2622 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2624 if (devinfo
->gen
>= 8 ||
2625 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2626 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2629 /* Gen7 needs at least command parser version 5 to support compute */
2630 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2631 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2633 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2635 screen
->winsys_msaa_samples_override
=
2636 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2637 printf("Forcing winsys sample count to %d\n",
2638 screen
->winsys_msaa_samples_override
);
2640 screen
->winsys_msaa_samples_override
= -1;
2643 set_max_gl_versions(screen
);
2645 /* Notification of GPU resets requires hardware contexts and a kernel new
2646 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2647 * supported, calling it with a context of 0 will either generate EPERM or
2648 * no error. If the ioctl is not supported, it always generate EINVAL.
2649 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2650 * extension to the loader.
2652 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2654 if (devinfo
->gen
>= 6) {
2655 struct drm_i915_reset_stats stats
;
2656 memset(&stats
, 0, sizeof(stats
));
2658 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2660 screen
->has_context_reset_notification
=
2661 (ret
!= -1 || errno
!= EINVAL
);
2664 dri_screen
->extensions
= !screen
->has_context_reset_notification
2665 ? screenExtensions
: intelRobustScreenExtensions
;
2667 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2668 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2669 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2670 screen
->compiler
->constant_buffer_0_is_relative
= true;
2671 screen
->compiler
->supports_pull_constants
= true;
2673 screen
->has_exec_fence
=
2674 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2676 intel_screen_init_surface_formats(screen
);
2678 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2679 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2681 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2682 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2683 fprintf(stderr
, " - User priority sorting enabled\n");
2684 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2685 fprintf(stderr
, " - Preemption enabled\n");
2689 brw_disk_cache_init(screen
);
2691 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2694 struct intel_buffer
{
2699 static __DRIbuffer
*
2700 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2701 unsigned attachment
, unsigned format
,
2702 int width
, int height
)
2704 struct intel_buffer
*intelBuffer
;
2705 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2707 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2708 attachment
== __DRI_BUFFER_BACK_LEFT
);
2710 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2711 if (intelBuffer
== NULL
)
2714 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2715 * supports Y tiled and compressed buffers, but there is no way to plumb that
2716 * through to here. */
2718 int cpp
= format
/ 8;
2719 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2720 "intelAllocateBuffer",
2724 I915_TILING_X
, &pitch
,
2727 if (intelBuffer
->bo
== NULL
) {
2732 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2734 intelBuffer
->base
.attachment
= attachment
;
2735 intelBuffer
->base
.cpp
= cpp
;
2736 intelBuffer
->base
.pitch
= pitch
;
2738 return &intelBuffer
->base
;
2742 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2744 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2746 brw_bo_unreference(intelBuffer
->bo
);
2750 static const struct __DriverAPIRec brw_driver_api
= {
2751 .InitScreen
= intelInitScreen2
,
2752 .DestroyScreen
= intelDestroyScreen
,
2753 .CreateContext
= brwCreateContext
,
2754 .DestroyContext
= intelDestroyContext
,
2755 .CreateBuffer
= intelCreateBuffer
,
2756 .DestroyBuffer
= intelDestroyBuffer
,
2757 .MakeCurrent
= intelMakeCurrent
,
2758 .UnbindContext
= intelUnbindContext
,
2759 .AllocateBuffer
= intelAllocateBuffer
,
2760 .ReleaseBuffer
= intelReleaseBuffer
2763 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2764 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2765 .vtable
= &brw_driver_api
,
2768 static const __DRIextension
*brw_driver_extensions
[] = {
2769 &driCoreExtension
.base
,
2770 &driImageDriverExtension
.base
,
2771 &driDRI2Extension
.base
,
2773 &brw_config_options
.base
,
2777 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2779 globalDriverAPI
= &brw_driver_api
;
2781 return brw_driver_extensions
;