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mesa: add AllowGLSLCrossStageInterpolationMismatch workaround
[mesa.git] / src / mesa / drivers / dri / i965 / intel_screen.c
1 /*
2 * Copyright 2003 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <drm_fourcc.h>
27 #include <errno.h>
28 #include <time.h>
29 #include <unistd.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "brw_state.h"
41 #include "compiler/nir/nir.h"
42
43 #include "utils.h"
44 #include "util/xmlpool.h"
45
46 static const __DRIconfigOptionsExtension brw_config_options = {
47 .base = { __DRI_CONFIG_OPTIONS, 1 },
48 .xml =
49 DRI_CONF_BEGIN
50 DRI_CONF_SECTION_PERFORMANCE
51 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
52 * DRI_CONF_BO_REUSE_ALL
53 */
54 DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 1, "0:1")
55 DRI_CONF_DESC_BEGIN(en, "Buffer object reuse")
56 DRI_CONF_ENUM(0, "Disable buffer object reuse")
57 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
58 DRI_CONF_DESC_END
59 DRI_CONF_OPT_END
60 DRI_CONF_MESA_NO_ERROR("false")
61 DRI_CONF_SECTION_END
62
63 DRI_CONF_SECTION_QUALITY
64 DRI_CONF_PRECISE_TRIG("false")
65
66 DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1)
67 DRI_CONF_DESC(en, "Clamp the value of GL_MAX_SAMPLES to the "
68 "given integer. If negative, then do not clamp.")
69 DRI_CONF_OPT_END
70 DRI_CONF_SECTION_END
71
72 DRI_CONF_SECTION_DEBUG
73 DRI_CONF_NO_RAST("false")
74 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
75 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
76 DRI_CONF_DISABLE_THROTTLING("false")
77 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
78 DRI_CONF_FORCE_GLSL_VERSION(0)
79 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
80 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
81 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
82 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
83 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
84 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
85 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
86 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
87
88 DRI_CONF_OPT_BEGIN_B(shader_precompile, "true")
89 DRI_CONF_DESC(en, "Perform code generation at shader link time.")
90 DRI_CONF_OPT_END
91 DRI_CONF_SECTION_END
92
93 DRI_CONF_SECTION_MISCELLANEOUS
94 DRI_CONF_GLSL_ZERO_INIT("false")
95 DRI_CONF_SECTION_END
96 DRI_CONF_END
97 };
98
99 #include "intel_batchbuffer.h"
100 #include "intel_buffers.h"
101 #include "brw_bufmgr.h"
102 #include "intel_fbo.h"
103 #include "intel_mipmap_tree.h"
104 #include "intel_screen.h"
105 #include "intel_tex.h"
106 #include "intel_image.h"
107
108 #include "brw_context.h"
109
110 #include "i915_drm.h"
111
112 /**
113 * For debugging purposes, this returns a time in seconds.
114 */
115 double
116 get_time(void)
117 {
118 struct timespec tp;
119
120 clock_gettime(CLOCK_MONOTONIC, &tp);
121
122 return tp.tv_sec + tp.tv_nsec / 1000000000.0;
123 }
124
125 static const __DRItexBufferExtension intelTexBufferExtension = {
126 .base = { __DRI_TEX_BUFFER, 3 },
127
128 .setTexBuffer = intelSetTexBuffer,
129 .setTexBuffer2 = intelSetTexBuffer2,
130 .releaseTexBuffer = NULL,
131 };
132
133 static void
134 intel_dri2_flush_with_flags(__DRIcontext *cPriv,
135 __DRIdrawable *dPriv,
136 unsigned flags,
137 enum __DRI2throttleReason reason)
138 {
139 struct brw_context *brw = cPriv->driverPrivate;
140
141 if (!brw)
142 return;
143
144 struct gl_context *ctx = &brw->ctx;
145
146 FLUSH_VERTICES(ctx, 0);
147
148 if (flags & __DRI2_FLUSH_DRAWABLE)
149 intel_resolve_for_dri2_flush(brw, dPriv);
150
151 if (reason == __DRI2_THROTTLE_SWAPBUFFER)
152 brw->need_swap_throttle = true;
153 if (reason == __DRI2_THROTTLE_FLUSHFRONT)
154 brw->need_flush_throttle = true;
155
156 intel_batchbuffer_flush(brw);
157 }
158
159 /**
160 * Provides compatibility with loaders that only support the older (version
161 * 1-3) flush interface.
162 *
163 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
164 */
165 static void
166 intel_dri2_flush(__DRIdrawable *drawable)
167 {
168 intel_dri2_flush_with_flags(drawable->driContextPriv, drawable,
169 __DRI2_FLUSH_DRAWABLE,
170 __DRI2_THROTTLE_SWAPBUFFER);
171 }
172
173 static const struct __DRI2flushExtensionRec intelFlushExtension = {
174 .base = { __DRI2_FLUSH, 4 },
175
176 .flush = intel_dri2_flush,
177 .invalidate = dri2InvalidateDrawable,
178 .flush_with_flags = intel_dri2_flush_with_flags,
179 };
180
181 static const struct intel_image_format intel_image_formats[] = {
182 { __DRI_IMAGE_FOURCC_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
183 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
184
185 { __DRI_IMAGE_FOURCC_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
186 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } },
187
188 { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
189 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } },
190
191 { __DRI_IMAGE_FOURCC_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
192 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } },
193
194 { __DRI_IMAGE_FOURCC_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
195 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } },
196
197 { __DRI_IMAGE_FOURCC_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1,
198 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555, 2 } } },
199
200 { __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1,
201 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } },
202
203 { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
204 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
205
206 { __DRI_IMAGE_FOURCC_R16, __DRI_IMAGE_COMPONENTS_R, 1,
207 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } },
208
209 { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
210 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } },
211
212 { __DRI_IMAGE_FOURCC_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } },
214
215 { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
217 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
218 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
219
220 { __DRI_IMAGE_FOURCC_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
221 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
222 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
223 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
224
225 { __DRI_IMAGE_FOURCC_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
226 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
227 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
228 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
229
230 { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
232 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
233 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
234
235 { __DRI_IMAGE_FOURCC_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
236 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
237 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
238 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
239
240 { __DRI_IMAGE_FOURCC_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
241 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
242 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
243 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
244
245 { __DRI_IMAGE_FOURCC_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
246 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
247 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
248 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
249
250 { __DRI_IMAGE_FOURCC_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
251 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
252 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
253 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
254
255 { __DRI_IMAGE_FOURCC_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
256 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
257 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
258 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
259
260 { __DRI_IMAGE_FOURCC_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
261 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
262 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
263 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
264
265 { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
266 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
267 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
268
269 { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
270 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
271 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } },
272
273 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
274 * and treat them as planar buffers in the compositors.
275 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
276 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
277 * clusters and places pairs and places U into the G component and
278 * V into A. This lets the texture sampler interpolate the Y
279 * components correctly when sampling from plane 0, and interpolate
280 * U and V correctly when sampling from plane 1. */
281 { __DRI_IMAGE_FOURCC_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2,
282 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
283 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
284 { __DRI_IMAGE_FOURCC_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2,
285 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
286 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }
287 };
288
289 static const struct {
290 uint64_t modifier;
291 unsigned since_gen;
292 } supported_modifiers[] = {
293 { .modifier = DRM_FORMAT_MOD_LINEAR , .since_gen = 1 },
294 { .modifier = I915_FORMAT_MOD_X_TILED , .since_gen = 1 },
295 { .modifier = I915_FORMAT_MOD_Y_TILED , .since_gen = 6 },
296 { .modifier = I915_FORMAT_MOD_Y_TILED_CCS , .since_gen = 9 },
297 };
298
299 static bool
300 modifier_is_supported(const struct gen_device_info *devinfo,
301 const struct intel_image_format *fmt, int dri_format,
302 uint64_t modifier)
303 {
304 const struct isl_drm_modifier_info *modinfo =
305 isl_drm_modifier_get_info(modifier);
306 int i;
307
308 /* ISL had better know about the modifier */
309 if (!modinfo)
310 return false;
311
312 if (modinfo->aux_usage == ISL_AUX_USAGE_CCS_E) {
313 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
314 if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC))
315 return false;
316
317 /* CCS_E is not supported for planar images */
318 if (fmt && fmt->nplanes > 1)
319 return false;
320
321 if (fmt) {
322 assert(dri_format == 0);
323 dri_format = fmt->planes[0].dri_format;
324 }
325
326 mesa_format format = driImageFormatToGLFormat(dri_format);
327 format = _mesa_get_srgb_format_linear(format);
328 if (!isl_format_supports_ccs_e(devinfo,
329 brw_isl_format_for_mesa_format(format)))
330 return false;
331 }
332
333 for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) {
334 if (supported_modifiers[i].modifier != modifier)
335 continue;
336
337 return supported_modifiers[i].since_gen <= devinfo->gen;
338 }
339
340 return false;
341 }
342
343 static uint64_t
344 tiling_to_modifier(uint32_t tiling)
345 {
346 static const uint64_t map[] = {
347 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR,
348 [I915_TILING_X] = I915_FORMAT_MOD_X_TILED,
349 [I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED,
350 };
351
352 assert(tiling < ARRAY_SIZE(map));
353
354 return map[tiling];
355 }
356
357 static void
358 intel_image_warn_if_unaligned(__DRIimage *image, const char *func)
359 {
360 uint32_t tiling, swizzle;
361 brw_bo_get_tiling(image->bo, &tiling, &swizzle);
362
363 if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) {
364 _mesa_warning(NULL, "%s: offset 0x%08x not on tile boundary",
365 func, image->offset);
366 }
367 }
368
369 static const struct intel_image_format *
370 intel_image_format_lookup(int fourcc)
371 {
372 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
373 if (intel_image_formats[i].fourcc == fourcc)
374 return &intel_image_formats[i];
375 }
376
377 return NULL;
378 }
379
380 static boolean intel_lookup_fourcc(int dri_format, int *fourcc)
381 {
382 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
383 if (intel_image_formats[i].planes[0].dri_format == dri_format) {
384 *fourcc = intel_image_formats[i].fourcc;
385 return true;
386 }
387 }
388 return false;
389 }
390
391 static __DRIimage *
392 intel_allocate_image(struct intel_screen *screen, int dri_format,
393 void *loaderPrivate)
394 {
395 __DRIimage *image;
396
397 image = calloc(1, sizeof *image);
398 if (image == NULL)
399 return NULL;
400
401 image->screen = screen;
402 image->dri_format = dri_format;
403 image->offset = 0;
404
405 image->format = driImageFormatToGLFormat(dri_format);
406 if (dri_format != __DRI_IMAGE_FORMAT_NONE &&
407 image->format == MESA_FORMAT_NONE) {
408 free(image);
409 return NULL;
410 }
411
412 image->internal_format = _mesa_get_format_base_format(image->format);
413 image->data = loaderPrivate;
414
415 return image;
416 }
417
418 /**
419 * Sets up a DRIImage structure to point to a slice out of a miptree.
420 */
421 static void
422 intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image,
423 struct intel_mipmap_tree *mt, GLuint level,
424 GLuint zoffset)
425 {
426 intel_miptree_make_shareable(brw, mt);
427
428 intel_miptree_check_level_layer(mt, level, zoffset);
429
430 image->width = minify(mt->surf.phys_level0_sa.width,
431 level - mt->first_level);
432 image->height = minify(mt->surf.phys_level0_sa.height,
433 level - mt->first_level);
434 image->pitch = mt->surf.row_pitch;
435
436 image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
437 &image->tile_x,
438 &image->tile_y);
439
440 brw_bo_unreference(image->bo);
441 image->bo = mt->bo;
442 brw_bo_reference(mt->bo);
443 }
444
445 static __DRIimage *
446 intel_create_image_from_name(__DRIscreen *dri_screen,
447 int width, int height, int format,
448 int name, int pitch, void *loaderPrivate)
449 {
450 struct intel_screen *screen = dri_screen->driverPrivate;
451 __DRIimage *image;
452 int cpp;
453
454 image = intel_allocate_image(screen, format, loaderPrivate);
455 if (image == NULL)
456 return NULL;
457
458 if (image->format == MESA_FORMAT_NONE)
459 cpp = 1;
460 else
461 cpp = _mesa_get_format_bytes(image->format);
462
463 image->width = width;
464 image->height = height;
465 image->pitch = pitch * cpp;
466 image->bo = brw_bo_gem_create_from_name(screen->bufmgr, "image",
467 name);
468 if (!image->bo) {
469 free(image);
470 return NULL;
471 }
472 image->modifier = tiling_to_modifier(image->bo->tiling_mode);
473
474 return image;
475 }
476
477 static __DRIimage *
478 intel_create_image_from_renderbuffer(__DRIcontext *context,
479 int renderbuffer, void *loaderPrivate)
480 {
481 __DRIimage *image;
482 struct brw_context *brw = context->driverPrivate;
483 struct gl_context *ctx = &brw->ctx;
484 struct gl_renderbuffer *rb;
485 struct intel_renderbuffer *irb;
486
487 rb = _mesa_lookup_renderbuffer(ctx, renderbuffer);
488 if (!rb) {
489 _mesa_error(ctx, GL_INVALID_OPERATION, "glRenderbufferExternalMESA");
490 return NULL;
491 }
492
493 irb = intel_renderbuffer(rb);
494 intel_miptree_make_shareable(brw, irb->mt);
495 image = calloc(1, sizeof *image);
496 if (image == NULL)
497 return NULL;
498
499 image->internal_format = rb->InternalFormat;
500 image->format = rb->Format;
501 image->modifier = tiling_to_modifier(
502 isl_tiling_to_i915_tiling(irb->mt->surf.tiling));
503 image->offset = 0;
504 image->data = loaderPrivate;
505 brw_bo_unreference(image->bo);
506 image->bo = irb->mt->bo;
507 brw_bo_reference(irb->mt->bo);
508 image->width = rb->Width;
509 image->height = rb->Height;
510 image->pitch = irb->mt->surf.row_pitch;
511 image->dri_format = driGLFormatToImageFormat(image->format);
512 image->has_depthstencil = irb->mt->stencil_mt? true : false;
513
514 rb->NeedsFinishRenderTexture = true;
515 return image;
516 }
517
518 static __DRIimage *
519 intel_create_image_from_texture(__DRIcontext *context, int target,
520 unsigned texture, int zoffset,
521 int level,
522 unsigned *error,
523 void *loaderPrivate)
524 {
525 __DRIimage *image;
526 struct brw_context *brw = context->driverPrivate;
527 struct gl_texture_object *obj;
528 struct intel_texture_object *iobj;
529 GLuint face = 0;
530
531 obj = _mesa_lookup_texture(&brw->ctx, texture);
532 if (!obj || obj->Target != target) {
533 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
534 return NULL;
535 }
536
537 if (target == GL_TEXTURE_CUBE_MAP)
538 face = zoffset;
539
540 _mesa_test_texobj_completeness(&brw->ctx, obj);
541 iobj = intel_texture_object(obj);
542 if (!obj->_BaseComplete || (level > 0 && !obj->_MipmapComplete)) {
543 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
544 return NULL;
545 }
546
547 if (level < obj->BaseLevel || level > obj->_MaxLevel) {
548 *error = __DRI_IMAGE_ERROR_BAD_MATCH;
549 return NULL;
550 }
551
552 if (target == GL_TEXTURE_3D && obj->Image[face][level]->Depth < zoffset) {
553 *error = __DRI_IMAGE_ERROR_BAD_MATCH;
554 return NULL;
555 }
556 image = calloc(1, sizeof *image);
557 if (image == NULL) {
558 *error = __DRI_IMAGE_ERROR_BAD_ALLOC;
559 return NULL;
560 }
561
562 image->internal_format = obj->Image[face][level]->InternalFormat;
563 image->format = obj->Image[face][level]->TexFormat;
564 image->modifier = tiling_to_modifier(
565 isl_tiling_to_i915_tiling(iobj->mt->surf.tiling));
566 image->data = loaderPrivate;
567 intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset);
568 image->dri_format = driGLFormatToImageFormat(image->format);
569 image->has_depthstencil = iobj->mt->stencil_mt? true : false;
570 if (image->dri_format == MESA_FORMAT_NONE) {
571 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
572 free(image);
573 return NULL;
574 }
575
576 *error = __DRI_IMAGE_ERROR_SUCCESS;
577 return image;
578 }
579
580 static void
581 intel_destroy_image(__DRIimage *image)
582 {
583 brw_bo_unreference(image->bo);
584 free(image);
585 }
586
587 enum modifier_priority {
588 MODIFIER_PRIORITY_INVALID = 0,
589 MODIFIER_PRIORITY_LINEAR,
590 MODIFIER_PRIORITY_X,
591 MODIFIER_PRIORITY_Y,
592 MODIFIER_PRIORITY_Y_CCS,
593 };
594
595 const uint64_t priority_to_modifier[] = {
596 [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
597 [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
598 [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
599 [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
600 [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
601 };
602
603 static uint64_t
604 select_best_modifier(struct gen_device_info *devinfo,
605 int dri_format,
606 const uint64_t *modifiers,
607 const unsigned count)
608 {
609 enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
610
611 for (int i = 0; i < count; i++) {
612 if (!modifier_is_supported(devinfo, NULL, dri_format, modifiers[i]))
613 continue;
614
615 switch (modifiers[i]) {
616 case I915_FORMAT_MOD_Y_TILED_CCS:
617 prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
618 break;
619 case I915_FORMAT_MOD_Y_TILED:
620 prio = MAX2(prio, MODIFIER_PRIORITY_Y);
621 break;
622 case I915_FORMAT_MOD_X_TILED:
623 prio = MAX2(prio, MODIFIER_PRIORITY_X);
624 break;
625 case DRM_FORMAT_MOD_LINEAR:
626 prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
627 break;
628 case DRM_FORMAT_MOD_INVALID:
629 default:
630 break;
631 }
632 }
633
634 return priority_to_modifier[prio];
635 }
636
637 static __DRIimage *
638 intel_create_image_common(__DRIscreen *dri_screen,
639 int width, int height, int format,
640 unsigned int use,
641 const uint64_t *modifiers,
642 unsigned count,
643 void *loaderPrivate)
644 {
645 __DRIimage *image;
646 struct intel_screen *screen = dri_screen->driverPrivate;
647 uint64_t modifier = DRM_FORMAT_MOD_INVALID;
648 bool ok;
649
650 /* Callers of this may specify a modifier, or a dri usage, but not both. The
651 * newer modifier interface deprecates the older usage flags newer modifier
652 * interface deprecates the older usage flags.
653 */
654 assert(!(use && count));
655
656 if (use & __DRI_IMAGE_USE_CURSOR) {
657 if (width != 64 || height != 64)
658 return NULL;
659 modifier = DRM_FORMAT_MOD_LINEAR;
660 }
661
662 if (use & __DRI_IMAGE_USE_LINEAR)
663 modifier = DRM_FORMAT_MOD_LINEAR;
664
665 if (modifier == DRM_FORMAT_MOD_INVALID) {
666 if (modifiers) {
667 /* User requested specific modifiers */
668 modifier = select_best_modifier(&screen->devinfo, format,
669 modifiers, count);
670 if (modifier == DRM_FORMAT_MOD_INVALID)
671 return NULL;
672 } else {
673 /* Historically, X-tiled was the default, and so lack of modifier means
674 * X-tiled.
675 */
676 modifier = I915_FORMAT_MOD_X_TILED;
677 }
678 }
679
680 image = intel_allocate_image(screen, format, loaderPrivate);
681 if (image == NULL)
682 return NULL;
683
684 const struct isl_drm_modifier_info *mod_info =
685 isl_drm_modifier_get_info(modifier);
686
687 struct isl_surf surf;
688 ok = isl_surf_init(&screen->isl_dev, &surf,
689 .dim = ISL_SURF_DIM_2D,
690 .format = brw_isl_format_for_mesa_format(image->format),
691 .width = width,
692 .height = height,
693 .depth = 1,
694 .levels = 1,
695 .array_len = 1,
696 .samples = 1,
697 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
698 ISL_SURF_USAGE_TEXTURE_BIT |
699 ISL_SURF_USAGE_STORAGE_BIT,
700 .tiling_flags = (1 << mod_info->tiling));
701 assert(ok);
702 if (!ok) {
703 free(image);
704 return NULL;
705 }
706
707 struct isl_surf aux_surf;
708 if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
709 ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, 0);
710 if (!ok) {
711 free(image);
712 return NULL;
713 }
714 } else {
715 assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
716 aux_surf.size = 0;
717 }
718
719 /* We request that the bufmgr zero the buffer for us for two reasons:
720 *
721 * 1) If a buffer gets re-used from the pool, we don't want to leak random
722 * garbage from our process to some other.
723 *
724 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
725 * a valid state. A CCS value of 0 indicates that the given block is
726 * in the pass-through state which is what we want.
727 */
728 image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
729 surf.size + aux_surf.size,
730 isl_tiling_to_i915_tiling(mod_info->tiling),
731 surf.row_pitch, BO_ALLOC_ZEROED);
732 if (image->bo == NULL) {
733 free(image);
734 return NULL;
735 }
736 image->width = width;
737 image->height = height;
738 image->pitch = surf.row_pitch;
739 image->modifier = modifier;
740
741 if (aux_surf.size) {
742 image->aux_offset = surf.size;
743 image->aux_pitch = aux_surf.row_pitch;
744 }
745
746 return image;
747 }
748
749 static __DRIimage *
750 intel_create_image(__DRIscreen *dri_screen,
751 int width, int height, int format,
752 unsigned int use,
753 void *loaderPrivate)
754 {
755 return intel_create_image_common(dri_screen, width, height, format, use, NULL, 0,
756 loaderPrivate);
757 }
758
759 static void *
760 intel_map_image(__DRIcontext *context, __DRIimage *image,
761 int x0, int y0, int width, int height,
762 unsigned int flags, int *stride, void **map_info)
763 {
764 struct brw_context *brw = NULL;
765 struct brw_bo *bo = NULL;
766 void *raw_data = NULL;
767 GLuint pix_w = 1;
768 GLuint pix_h = 1;
769 GLint pix_bytes = 1;
770
771 if (!context || !image || !stride || !map_info || *map_info)
772 return NULL;
773
774 if (x0 < 0 || x0 >= image->width || width > image->width - x0)
775 return NULL;
776
777 if (y0 < 0 || y0 >= image->height || height > image->height - y0)
778 return NULL;
779
780 if (flags & MAP_INTERNAL_MASK)
781 return NULL;
782
783 brw = context->driverPrivate;
784 bo = image->bo;
785
786 assert(brw);
787 assert(bo);
788
789 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
790 raw_data = brw_bo_map(brw, bo, flags);
791 if (!raw_data)
792 return NULL;
793
794 _mesa_get_format_block_size(image->format, &pix_w, &pix_h);
795 pix_bytes = _mesa_get_format_bytes(image->format);
796
797 assert(pix_w);
798 assert(pix_h);
799 assert(pix_bytes > 0);
800
801 raw_data += (x0 / pix_w) * pix_bytes + (y0 / pix_h) * image->pitch;
802
803 brw_bo_reference(bo);
804
805 *stride = image->pitch;
806 *map_info = bo;
807
808 return raw_data;
809 }
810
811 static void
812 intel_unmap_image(__DRIcontext *context, __DRIimage *image, void *map_info)
813 {
814 struct brw_bo *bo = map_info;
815
816 brw_bo_unmap(bo);
817 brw_bo_unreference(bo);
818 }
819
820 static __DRIimage *
821 intel_create_image_with_modifiers(__DRIscreen *dri_screen,
822 int width, int height, int format,
823 const uint64_t *modifiers,
824 const unsigned count,
825 void *loaderPrivate)
826 {
827 return intel_create_image_common(dri_screen, width, height, format, 0,
828 modifiers, count, loaderPrivate);
829 }
830
831 static GLboolean
832 intel_query_image(__DRIimage *image, int attrib, int *value)
833 {
834 switch (attrib) {
835 case __DRI_IMAGE_ATTRIB_STRIDE:
836 *value = image->pitch;
837 return true;
838 case __DRI_IMAGE_ATTRIB_HANDLE:
839 *value = brw_bo_export_gem_handle(image->bo);
840 return true;
841 case __DRI_IMAGE_ATTRIB_NAME:
842 return !brw_bo_flink(image->bo, (uint32_t *) value);
843 case __DRI_IMAGE_ATTRIB_FORMAT:
844 *value = image->dri_format;
845 return true;
846 case __DRI_IMAGE_ATTRIB_WIDTH:
847 *value = image->width;
848 return true;
849 case __DRI_IMAGE_ATTRIB_HEIGHT:
850 *value = image->height;
851 return true;
852 case __DRI_IMAGE_ATTRIB_COMPONENTS:
853 if (image->planar_format == NULL)
854 return false;
855 *value = image->planar_format->components;
856 return true;
857 case __DRI_IMAGE_ATTRIB_FD:
858 return !brw_bo_gem_export_to_prime(image->bo, value);
859 case __DRI_IMAGE_ATTRIB_FOURCC:
860 return intel_lookup_fourcc(image->dri_format, value);
861 case __DRI_IMAGE_ATTRIB_NUM_PLANES:
862 if (isl_drm_modifier_has_aux(image->modifier)) {
863 assert(!image->planar_format || image->planar_format->nplanes == 1);
864 *value = 2;
865 } else if (image->planar_format) {
866 *value = image->planar_format->nplanes;
867 } else {
868 *value = 1;
869 }
870 return true;
871 case __DRI_IMAGE_ATTRIB_OFFSET:
872 *value = image->offset;
873 return true;
874 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER:
875 *value = (image->modifier & 0xffffffff);
876 return true;
877 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER:
878 *value = ((image->modifier >> 32) & 0xffffffff);
879 return true;
880
881 default:
882 return false;
883 }
884 }
885
886 static GLboolean
887 intel_query_format_modifier_attribs(__DRIscreen *dri_screen,
888 uint32_t fourcc, uint64_t modifier,
889 int attrib, uint64_t *value)
890 {
891 struct intel_screen *screen = dri_screen->driverPrivate;
892 const struct intel_image_format *f = intel_image_format_lookup(fourcc);
893
894 if (!modifier_is_supported(&screen->devinfo, f, 0, modifier))
895 return false;
896
897 switch (attrib) {
898 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT:
899 *value = isl_drm_modifier_has_aux(modifier) ? 2 : f->nplanes;
900 return true;
901
902 default:
903 return false;
904 }
905 }
906
907 static __DRIimage *
908 intel_dup_image(__DRIimage *orig_image, void *loaderPrivate)
909 {
910 __DRIimage *image;
911
912 image = calloc(1, sizeof *image);
913 if (image == NULL)
914 return NULL;
915
916 brw_bo_reference(orig_image->bo);
917 image->bo = orig_image->bo;
918 image->internal_format = orig_image->internal_format;
919 image->planar_format = orig_image->planar_format;
920 image->dri_format = orig_image->dri_format;
921 image->format = orig_image->format;
922 image->modifier = orig_image->modifier;
923 image->offset = orig_image->offset;
924 image->width = orig_image->width;
925 image->height = orig_image->height;
926 image->pitch = orig_image->pitch;
927 image->tile_x = orig_image->tile_x;
928 image->tile_y = orig_image->tile_y;
929 image->has_depthstencil = orig_image->has_depthstencil;
930 image->data = loaderPrivate;
931 image->dma_buf_imported = orig_image->dma_buf_imported;
932 image->aux_offset = orig_image->aux_offset;
933 image->aux_pitch = orig_image->aux_pitch;
934
935 memcpy(image->strides, orig_image->strides, sizeof(image->strides));
936 memcpy(image->offsets, orig_image->offsets, sizeof(image->offsets));
937
938 return image;
939 }
940
941 static GLboolean
942 intel_validate_usage(__DRIimage *image, unsigned int use)
943 {
944 if (use & __DRI_IMAGE_USE_CURSOR) {
945 if (image->width != 64 || image->height != 64)
946 return GL_FALSE;
947 }
948
949 return GL_TRUE;
950 }
951
952 static __DRIimage *
953 intel_create_image_from_names(__DRIscreen *dri_screen,
954 int width, int height, int fourcc,
955 int *names, int num_names,
956 int *strides, int *offsets,
957 void *loaderPrivate)
958 {
959 const struct intel_image_format *f = NULL;
960 __DRIimage *image;
961 int i, index;
962
963 if (dri_screen == NULL || names == NULL || num_names != 1)
964 return NULL;
965
966 f = intel_image_format_lookup(fourcc);
967 if (f == NULL)
968 return NULL;
969
970 image = intel_create_image_from_name(dri_screen, width, height,
971 __DRI_IMAGE_FORMAT_NONE,
972 names[0], strides[0],
973 loaderPrivate);
974
975 if (image == NULL)
976 return NULL;
977
978 image->planar_format = f;
979 for (i = 0; i < f->nplanes; i++) {
980 index = f->planes[i].buffer_index;
981 image->offsets[index] = offsets[index];
982 image->strides[index] = strides[index];
983 }
984
985 return image;
986 }
987
988 static __DRIimage *
989 intel_create_image_from_fds_common(__DRIscreen *dri_screen,
990 int width, int height, int fourcc,
991 uint64_t modifier, int *fds, int num_fds,
992 int *strides, int *offsets,
993 void *loaderPrivate)
994 {
995 struct intel_screen *screen = dri_screen->driverPrivate;
996 const struct intel_image_format *f;
997 __DRIimage *image;
998 int i, index;
999 bool ok;
1000
1001 if (fds == NULL || num_fds < 1)
1002 return NULL;
1003
1004 f = intel_image_format_lookup(fourcc);
1005 if (f == NULL)
1006 return NULL;
1007
1008 if (modifier != DRM_FORMAT_MOD_INVALID &&
1009 !modifier_is_supported(&screen->devinfo, f, 0, modifier))
1010 return NULL;
1011
1012 if (f->nplanes == 1)
1013 image = intel_allocate_image(screen, f->planes[0].dri_format,
1014 loaderPrivate);
1015 else
1016 image = intel_allocate_image(screen, __DRI_IMAGE_FORMAT_NONE,
1017 loaderPrivate);
1018
1019 if (image == NULL)
1020 return NULL;
1021
1022 image->width = width;
1023 image->height = height;
1024 image->pitch = strides[0];
1025
1026 image->planar_format = f;
1027
1028 image->bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0]);
1029 if (image->bo == NULL) {
1030 free(image);
1031 return NULL;
1032 }
1033
1034 /* We only support all planes from the same bo.
1035 * brw_bo_gem_create_from_prime() should return the same pointer for all
1036 * fds received here */
1037 for (i = 1; i < num_fds; i++) {
1038 struct brw_bo *aux = brw_bo_gem_create_from_prime(screen->bufmgr, fds[i]);
1039 brw_bo_unreference(aux);
1040 if (aux != image->bo) {
1041 brw_bo_unreference(image->bo);
1042 free(image);
1043 return NULL;
1044 }
1045 }
1046
1047 if (modifier != DRM_FORMAT_MOD_INVALID)
1048 image->modifier = modifier;
1049 else
1050 image->modifier = tiling_to_modifier(image->bo->tiling_mode);
1051
1052 const struct isl_drm_modifier_info *mod_info =
1053 isl_drm_modifier_get_info(image->modifier);
1054
1055 int size = 0;
1056 struct isl_surf surf;
1057 for (i = 0; i < f->nplanes; i++) {
1058 index = f->planes[i].buffer_index;
1059 image->offsets[index] = offsets[index];
1060 image->strides[index] = strides[index];
1061
1062 mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format);
1063
1064 ok = isl_surf_init(&screen->isl_dev, &surf,
1065 .dim = ISL_SURF_DIM_2D,
1066 .format = brw_isl_format_for_mesa_format(format),
1067 .width = image->width >> f->planes[i].width_shift,
1068 .height = image->height >> f->planes[i].height_shift,
1069 .depth = 1,
1070 .levels = 1,
1071 .array_len = 1,
1072 .samples = 1,
1073 .row_pitch = strides[index],
1074 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
1075 ISL_SURF_USAGE_TEXTURE_BIT |
1076 ISL_SURF_USAGE_STORAGE_BIT,
1077 .tiling_flags = (1 << mod_info->tiling));
1078 if (!ok) {
1079 brw_bo_unreference(image->bo);
1080 free(image);
1081 return NULL;
1082 }
1083
1084 const int end = offsets[index] + surf.size;
1085 if (size < end)
1086 size = end;
1087 }
1088
1089 if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
1090 /* Even though we initialize surf in the loop above, we know that
1091 * anything with CCS_E will have exactly one plane so surf is properly
1092 * initialized when we get here.
1093 */
1094 assert(f->nplanes == 1);
1095
1096 image->aux_offset = offsets[1];
1097 image->aux_pitch = strides[1];
1098
1099 /* Scanout hardware requires that the CCS be placed after the main
1100 * surface in memory. We consider any CCS that is placed any earlier in
1101 * memory to be invalid and reject it.
1102 *
1103 * At some point in the future, this restriction may be relaxed if the
1104 * hardware becomes less strict but we may need a new modifier for that.
1105 */
1106 assert(size > 0);
1107 if (image->aux_offset < size) {
1108 brw_bo_unreference(image->bo);
1109 free(image);
1110 return NULL;
1111 }
1112
1113 struct isl_surf aux_surf;
1114 ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf,
1115 image->aux_pitch);
1116 if (!ok) {
1117 brw_bo_unreference(image->bo);
1118 free(image);
1119 return NULL;
1120 }
1121
1122 const int end = image->aux_offset + aux_surf.size;
1123 if (size < end)
1124 size = end;
1125 } else {
1126 assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
1127 }
1128
1129 /* Check that the requested image actually fits within the BO. 'size'
1130 * is already relative to the offsets, so we don't need to add that. */
1131 if (image->bo->size == 0) {
1132 image->bo->size = size;
1133 } else if (size > image->bo->size) {
1134 brw_bo_unreference(image->bo);
1135 free(image);
1136 return NULL;
1137 }
1138
1139 if (f->nplanes == 1) {
1140 image->offset = image->offsets[0];
1141 intel_image_warn_if_unaligned(image, __func__);
1142 }
1143
1144 return image;
1145 }
1146
1147 static __DRIimage *
1148 intel_create_image_from_fds(__DRIscreen *dri_screen,
1149 int width, int height, int fourcc,
1150 int *fds, int num_fds, int *strides, int *offsets,
1151 void *loaderPrivate)
1152 {
1153 return intel_create_image_from_fds_common(dri_screen, width, height, fourcc,
1154 DRM_FORMAT_MOD_INVALID,
1155 fds, num_fds, strides, offsets,
1156 loaderPrivate);
1157 }
1158
1159 static __DRIimage *
1160 intel_create_image_from_dma_bufs2(__DRIscreen *dri_screen,
1161 int width, int height,
1162 int fourcc, uint64_t modifier,
1163 int *fds, int num_fds,
1164 int *strides, int *offsets,
1165 enum __DRIYUVColorSpace yuv_color_space,
1166 enum __DRISampleRange sample_range,
1167 enum __DRIChromaSiting horizontal_siting,
1168 enum __DRIChromaSiting vertical_siting,
1169 unsigned *error,
1170 void *loaderPrivate)
1171 {
1172 __DRIimage *image;
1173 const struct intel_image_format *f = intel_image_format_lookup(fourcc);
1174
1175 if (!f) {
1176 *error = __DRI_IMAGE_ERROR_BAD_MATCH;
1177 return NULL;
1178 }
1179
1180 image = intel_create_image_from_fds_common(dri_screen, width, height,
1181 fourcc, modifier,
1182 fds, num_fds, strides, offsets,
1183 loaderPrivate);
1184
1185 /*
1186 * Invalid parameters and any inconsistencies between are assumed to be
1187 * checked by the caller. Therefore besides unsupported formats one can fail
1188 * only in allocation.
1189 */
1190 if (!image) {
1191 *error = __DRI_IMAGE_ERROR_BAD_ALLOC;
1192 return NULL;
1193 }
1194
1195 image->dma_buf_imported = true;
1196 image->yuv_color_space = yuv_color_space;
1197 image->sample_range = sample_range;
1198 image->horizontal_siting = horizontal_siting;
1199 image->vertical_siting = vertical_siting;
1200
1201 *error = __DRI_IMAGE_ERROR_SUCCESS;
1202 return image;
1203 }
1204
1205 static __DRIimage *
1206 intel_create_image_from_dma_bufs(__DRIscreen *dri_screen,
1207 int width, int height, int fourcc,
1208 int *fds, int num_fds,
1209 int *strides, int *offsets,
1210 enum __DRIYUVColorSpace yuv_color_space,
1211 enum __DRISampleRange sample_range,
1212 enum __DRIChromaSiting horizontal_siting,
1213 enum __DRIChromaSiting vertical_siting,
1214 unsigned *error,
1215 void *loaderPrivate)
1216 {
1217 return intel_create_image_from_dma_bufs2(dri_screen, width, height,
1218 fourcc, DRM_FORMAT_MOD_INVALID,
1219 fds, num_fds, strides, offsets,
1220 yuv_color_space,
1221 sample_range,
1222 horizontal_siting,
1223 vertical_siting,
1224 error,
1225 loaderPrivate);
1226 }
1227
1228 static GLboolean
1229 intel_query_dma_buf_formats(__DRIscreen *screen, int max,
1230 int *formats, int *count)
1231 {
1232 int i, j = 0;
1233
1234 if (max == 0) {
1235 *count = ARRAY_SIZE(intel_image_formats) - 1; /* not SARGB */
1236 return true;
1237 }
1238
1239 for (i = 0; i < (ARRAY_SIZE(intel_image_formats)) && j < max; i++) {
1240 if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888)
1241 continue;
1242 formats[j++] = intel_image_formats[i].fourcc;
1243 }
1244
1245 *count = j;
1246 return true;
1247 }
1248
1249 static GLboolean
1250 intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max,
1251 uint64_t *modifiers,
1252 unsigned int *external_only,
1253 int *count)
1254 {
1255 struct intel_screen *screen = _screen->driverPrivate;
1256 const struct intel_image_format *f;
1257 int num_mods = 0, i;
1258
1259 f = intel_image_format_lookup(fourcc);
1260 if (f == NULL)
1261 return false;
1262
1263 for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) {
1264 uint64_t modifier = supported_modifiers[i].modifier;
1265 if (!modifier_is_supported(&screen->devinfo, f, 0, modifier))
1266 continue;
1267
1268 num_mods++;
1269 if (max == 0)
1270 continue;
1271
1272 modifiers[num_mods - 1] = modifier;
1273 if (num_mods >= max)
1274 break;
1275 }
1276
1277 if (external_only != NULL) {
1278 for (i = 0; i < num_mods && i < max; i++) {
1279 if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V ||
1280 f->components == __DRI_IMAGE_COMPONENTS_Y_UV ||
1281 f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV) {
1282 external_only[i] = GL_TRUE;
1283 }
1284 else {
1285 external_only[i] = GL_FALSE;
1286 }
1287 }
1288 }
1289
1290 *count = num_mods;
1291 return true;
1292 }
1293
1294 static __DRIimage *
1295 intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
1296 {
1297 int width, height, offset, stride, dri_format, index;
1298 const struct intel_image_format *f;
1299 __DRIimage *image;
1300
1301 if (parent == NULL) {
1302 return NULL;
1303 } else if (parent->planar_format == NULL) {
1304 const bool is_aux =
1305 isl_drm_modifier_has_aux(parent->modifier) && plane == 1;
1306 if (!is_aux)
1307 return NULL;
1308
1309 width = parent->width;
1310 height = parent->height;
1311 dri_format = parent->dri_format;
1312 offset = parent->aux_offset;
1313 stride = parent->aux_pitch;
1314 } else {
1315 /* Planar formats don't support aux buffers/images */
1316 assert(!isl_drm_modifier_has_aux(parent->modifier));
1317 f = parent->planar_format;
1318
1319 if (plane >= f->nplanes)
1320 return NULL;
1321
1322 width = parent->width >> f->planes[plane].width_shift;
1323 height = parent->height >> f->planes[plane].height_shift;
1324 dri_format = f->planes[plane].dri_format;
1325 index = f->planes[plane].buffer_index;
1326 offset = parent->offsets[index];
1327 stride = parent->strides[index];
1328
1329 if (offset + height * stride > parent->bo->size) {
1330 _mesa_warning(NULL, "intel_create_sub_image: subimage out of bounds");
1331 return NULL;
1332 }
1333 }
1334
1335 image = intel_allocate_image(parent->screen, dri_format, loaderPrivate);
1336 if (image == NULL)
1337 return NULL;
1338
1339 image->bo = parent->bo;
1340 brw_bo_reference(parent->bo);
1341 image->modifier = parent->modifier;
1342
1343 image->width = width;
1344 image->height = height;
1345 image->pitch = stride;
1346 image->offset = offset;
1347
1348 intel_image_warn_if_unaligned(image, __func__);
1349
1350 return image;
1351 }
1352
1353 static const __DRIimageExtension intelImageExtension = {
1354 .base = { __DRI_IMAGE, 16 },
1355
1356 .createImageFromName = intel_create_image_from_name,
1357 .createImageFromRenderbuffer = intel_create_image_from_renderbuffer,
1358 .destroyImage = intel_destroy_image,
1359 .createImage = intel_create_image,
1360 .queryImage = intel_query_image,
1361 .dupImage = intel_dup_image,
1362 .validateUsage = intel_validate_usage,
1363 .createImageFromNames = intel_create_image_from_names,
1364 .fromPlanar = intel_from_planar,
1365 .createImageFromTexture = intel_create_image_from_texture,
1366 .createImageFromFds = intel_create_image_from_fds,
1367 .createImageFromDmaBufs = intel_create_image_from_dma_bufs,
1368 .blitImage = NULL,
1369 .getCapabilities = NULL,
1370 .mapImage = intel_map_image,
1371 .unmapImage = intel_unmap_image,
1372 .createImageWithModifiers = intel_create_image_with_modifiers,
1373 .createImageFromDmaBufs2 = intel_create_image_from_dma_bufs2,
1374 .queryDmaBufFormats = intel_query_dma_buf_formats,
1375 .queryDmaBufModifiers = intel_query_dma_buf_modifiers,
1376 .queryDmaBufFormatModifierAttribs = intel_query_format_modifier_attribs,
1377 };
1378
1379 static uint64_t
1380 get_aperture_size(int fd)
1381 {
1382 struct drm_i915_gem_get_aperture aperture;
1383
1384 if (drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture) != 0)
1385 return 0;
1386
1387 return aperture.aper_size;
1388 }
1389
1390 static int
1391 brw_query_renderer_integer(__DRIscreen *dri_screen,
1392 int param, unsigned int *value)
1393 {
1394 const struct intel_screen *const screen =
1395 (struct intel_screen *) dri_screen->driverPrivate;
1396
1397 switch (param) {
1398 case __DRI2_RENDERER_VENDOR_ID:
1399 value[0] = 0x8086;
1400 return 0;
1401 case __DRI2_RENDERER_DEVICE_ID:
1402 value[0] = screen->deviceID;
1403 return 0;
1404 case __DRI2_RENDERER_ACCELERATED:
1405 value[0] = 1;
1406 return 0;
1407 case __DRI2_RENDERER_VIDEO_MEMORY: {
1408 /* Once a batch uses more than 75% of the maximum mappable size, we
1409 * assume that there's some fragmentation, and we start doing extra
1410 * flushing, etc. That's the big cliff apps will care about.
1411 */
1412 const unsigned gpu_mappable_megabytes =
1413 screen->aperture_threshold / (1024 * 1024);
1414
1415 const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
1416 const long system_page_size = sysconf(_SC_PAGE_SIZE);
1417
1418 if (system_memory_pages <= 0 || system_page_size <= 0)
1419 return -1;
1420
1421 const uint64_t system_memory_bytes = (uint64_t) system_memory_pages
1422 * (uint64_t) system_page_size;
1423
1424 const unsigned system_memory_megabytes =
1425 (unsigned) (system_memory_bytes / (1024 * 1024));
1426
1427 value[0] = MIN2(system_memory_megabytes, gpu_mappable_megabytes);
1428 return 0;
1429 }
1430 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE:
1431 value[0] = 1;
1432 return 0;
1433 case __DRI2_RENDERER_HAS_TEXTURE_3D:
1434 value[0] = 1;
1435 return 0;
1436 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY:
1437 value[0] = 0;
1438 if (brw_hw_context_set_priority(screen->bufmgr,
1439 0, BRW_CONTEXT_HIGH_PRIORITY) == 0)
1440 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH;
1441 if (brw_hw_context_set_priority(screen->bufmgr,
1442 0, BRW_CONTEXT_LOW_PRIORITY) == 0)
1443 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW;
1444 /* reset to default last, just in case */
1445 if (brw_hw_context_set_priority(screen->bufmgr,
1446 0, BRW_CONTEXT_MEDIUM_PRIORITY) == 0)
1447 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM;
1448 return 0;
1449 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB:
1450 value[0] = 1;
1451 return 0;
1452 default:
1453 return driQueryRendererIntegerCommon(dri_screen, param, value);
1454 }
1455
1456 return -1;
1457 }
1458
1459 static int
1460 brw_query_renderer_string(__DRIscreen *dri_screen,
1461 int param, const char **value)
1462 {
1463 const struct intel_screen *screen =
1464 (struct intel_screen *) dri_screen->driverPrivate;
1465
1466 switch (param) {
1467 case __DRI2_RENDERER_VENDOR_ID:
1468 value[0] = brw_vendor_string;
1469 return 0;
1470 case __DRI2_RENDERER_DEVICE_ID:
1471 value[0] = brw_get_renderer_string(screen);
1472 return 0;
1473 default:
1474 break;
1475 }
1476
1477 return -1;
1478 }
1479
1480 static const __DRI2rendererQueryExtension intelRendererQueryExtension = {
1481 .base = { __DRI2_RENDERER_QUERY, 1 },
1482
1483 .queryInteger = brw_query_renderer_integer,
1484 .queryString = brw_query_renderer_string
1485 };
1486
1487 static const __DRIrobustnessExtension dri2Robustness = {
1488 .base = { __DRI2_ROBUSTNESS, 1 }
1489 };
1490
1491 static const __DRIextension *screenExtensions[] = {
1492 &intelTexBufferExtension.base,
1493 &intelFenceExtension.base,
1494 &intelFlushExtension.base,
1495 &intelImageExtension.base,
1496 &intelRendererQueryExtension.base,
1497 &dri2ConfigQueryExtension.base,
1498 &dri2NoErrorExtension.base,
1499 &dri2FlushControlExtension.base,
1500 NULL
1501 };
1502
1503 static const __DRIextension *intelRobustScreenExtensions[] = {
1504 &intelTexBufferExtension.base,
1505 &intelFenceExtension.base,
1506 &intelFlushExtension.base,
1507 &intelImageExtension.base,
1508 &intelRendererQueryExtension.base,
1509 &dri2ConfigQueryExtension.base,
1510 &dri2FlushControlExtension.base,
1511 &dri2Robustness.base,
1512 &dri2NoErrorExtension.base,
1513 NULL
1514 };
1515
1516 static int
1517 intel_get_param(struct intel_screen *screen, int param, int *value)
1518 {
1519 int ret = 0;
1520 struct drm_i915_getparam gp;
1521
1522 memset(&gp, 0, sizeof(gp));
1523 gp.param = param;
1524 gp.value = value;
1525
1526 if (drmIoctl(screen->driScrnPriv->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) {
1527 ret = -errno;
1528 if (ret != -EINVAL)
1529 _mesa_warning(NULL, "drm_i915_getparam: %d", ret);
1530 }
1531
1532 return ret;
1533 }
1534
1535 static bool
1536 intel_get_boolean(struct intel_screen *screen, int param)
1537 {
1538 int value = 0;
1539 return (intel_get_param(screen, param, &value) == 0) && value;
1540 }
1541
1542 static int
1543 intel_get_integer(struct intel_screen *screen, int param)
1544 {
1545 int value = -1;
1546
1547 if (intel_get_param(screen, param, &value) == 0)
1548 return value;
1549
1550 return -1;
1551 }
1552
1553 static void
1554 intelDestroyScreen(__DRIscreen * sPriv)
1555 {
1556 struct intel_screen *screen = sPriv->driverPrivate;
1557
1558 brw_bufmgr_destroy(screen->bufmgr);
1559 driDestroyOptionInfo(&screen->optionCache);
1560
1561 ralloc_free(screen);
1562 sPriv->driverPrivate = NULL;
1563 }
1564
1565
1566 /**
1567 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1568 *
1569 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1570 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1571 * this does not allocate GPU memory.
1572 */
1573 static GLboolean
1574 intelCreateBuffer(__DRIscreen *dri_screen,
1575 __DRIdrawable * driDrawPriv,
1576 const struct gl_config * mesaVis, GLboolean isPixmap)
1577 {
1578 struct intel_renderbuffer *rb;
1579 struct intel_screen *screen = (struct intel_screen *)
1580 dri_screen->driverPrivate;
1581 mesa_format rgbFormat;
1582 unsigned num_samples =
1583 intel_quantize_num_samples(screen, mesaVis->samples);
1584
1585 if (isPixmap)
1586 return false;
1587
1588 struct gl_framebuffer *fb = CALLOC_STRUCT(gl_framebuffer);
1589 if (!fb)
1590 return false;
1591
1592 _mesa_initialize_window_framebuffer(fb, mesaVis);
1593
1594 if (screen->winsys_msaa_samples_override != -1) {
1595 num_samples = screen->winsys_msaa_samples_override;
1596 fb->Visual.samples = num_samples;
1597 }
1598
1599 if (mesaVis->redBits == 5) {
1600 rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1601 : MESA_FORMAT_B5G6R5_UNORM;
1602 } else if (mesaVis->sRGBCapable) {
1603 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1604 : MESA_FORMAT_B8G8R8A8_SRGB;
1605 } else if (mesaVis->alphaBits == 0) {
1606 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1607 : MESA_FORMAT_B8G8R8X8_UNORM;
1608 } else {
1609 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1610 : MESA_FORMAT_B8G8R8A8_SRGB;
1611 fb->Visual.sRGBCapable = true;
1612 }
1613
1614 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1615 bool srgb_cap_set = mesaVis->redBits >= 8 && mesaVis->sRGBCapable;
1616
1617 /* setup the hardware-based renderbuffers */
1618 rb = intel_create_winsys_renderbuffer(screen, rgbFormat, num_samples);
1619 _mesa_attach_and_own_rb(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
1620 rb->need_srgb = srgb_cap_set;
1621
1622 if (mesaVis->doubleBufferMode) {
1623 rb = intel_create_winsys_renderbuffer(screen, rgbFormat, num_samples);
1624 _mesa_attach_and_own_rb(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
1625 rb->need_srgb = srgb_cap_set;
1626 }
1627
1628 /*
1629 * Assert here that the gl_config has an expected depth/stencil bit
1630 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1631 * which constructs the advertised configs.)
1632 */
1633 if (mesaVis->depthBits == 24) {
1634 assert(mesaVis->stencilBits == 8);
1635
1636 if (screen->devinfo.has_hiz_and_separate_stencil) {
1637 rb = intel_create_private_renderbuffer(screen,
1638 MESA_FORMAT_Z24_UNORM_X8_UINT,
1639 num_samples);
1640 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
1641 rb = intel_create_private_renderbuffer(screen, MESA_FORMAT_S_UINT8,
1642 num_samples);
1643 _mesa_attach_and_own_rb(fb, BUFFER_STENCIL, &rb->Base.Base);
1644 } else {
1645 /*
1646 * Use combined depth/stencil. Note that the renderbuffer is
1647 * attached to two attachment points.
1648 */
1649 rb = intel_create_private_renderbuffer(screen,
1650 MESA_FORMAT_Z24_UNORM_S8_UINT,
1651 num_samples);
1652 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
1653 _mesa_attach_and_reference_rb(fb, BUFFER_STENCIL, &rb->Base.Base);
1654 }
1655 }
1656 else if (mesaVis->depthBits == 16) {
1657 assert(mesaVis->stencilBits == 0);
1658 rb = intel_create_private_renderbuffer(screen, MESA_FORMAT_Z_UNORM16,
1659 num_samples);
1660 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
1661 }
1662 else {
1663 assert(mesaVis->depthBits == 0);
1664 assert(mesaVis->stencilBits == 0);
1665 }
1666
1667 /* now add any/all software-based renderbuffers we may need */
1668 _swrast_add_soft_renderbuffers(fb,
1669 false, /* never sw color */
1670 false, /* never sw depth */
1671 false, /* never sw stencil */
1672 mesaVis->accumRedBits > 0,
1673 false, /* never sw alpha */
1674 false /* never sw aux */ );
1675 driDrawPriv->driverPrivate = fb;
1676
1677 return true;
1678 }
1679
1680 static void
1681 intelDestroyBuffer(__DRIdrawable * driDrawPriv)
1682 {
1683 struct gl_framebuffer *fb = driDrawPriv->driverPrivate;
1684
1685 _mesa_reference_framebuffer(&fb, NULL);
1686 }
1687
1688 static void
1689 intel_detect_sseu(struct intel_screen *screen)
1690 {
1691 assert(screen->devinfo.gen >= 8);
1692 int ret;
1693
1694 screen->subslice_total = -1;
1695 screen->eu_total = -1;
1696
1697 ret = intel_get_param(screen, I915_PARAM_SUBSLICE_TOTAL,
1698 &screen->subslice_total);
1699 if (ret < 0 && ret != -EINVAL)
1700 goto err_out;
1701
1702 ret = intel_get_param(screen,
1703 I915_PARAM_EU_TOTAL, &screen->eu_total);
1704 if (ret < 0 && ret != -EINVAL)
1705 goto err_out;
1706
1707 /* Without this information, we cannot get the right Braswell brandstrings,
1708 * and we have to use conservative numbers for GPGPU on many platforms, but
1709 * otherwise, things will just work.
1710 */
1711 if (screen->subslice_total < 1 || screen->eu_total < 1)
1712 _mesa_warning(NULL,
1713 "Kernel 4.1 required to properly query GPU properties.\n");
1714
1715 return;
1716
1717 err_out:
1718 screen->subslice_total = -1;
1719 screen->eu_total = -1;
1720 _mesa_warning(NULL, "Failed to query GPU properties (%s).\n", strerror(-ret));
1721 }
1722
1723 static bool
1724 intel_init_bufmgr(struct intel_screen *screen)
1725 {
1726 __DRIscreen *dri_screen = screen->driScrnPriv;
1727
1728 if (getenv("INTEL_NO_HW") != NULL)
1729 screen->no_hw = true;
1730
1731 screen->bufmgr = brw_bufmgr_init(&screen->devinfo, dri_screen->fd);
1732 if (screen->bufmgr == NULL) {
1733 fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
1734 __func__, __LINE__);
1735 return false;
1736 }
1737
1738 if (!intel_get_boolean(screen, I915_PARAM_HAS_WAIT_TIMEOUT)) {
1739 fprintf(stderr, "[%s: %u] Kernel 3.6 required.\n", __func__, __LINE__);
1740 return false;
1741 }
1742
1743 return true;
1744 }
1745
1746 static bool
1747 intel_detect_swizzling(struct intel_screen *screen)
1748 {
1749 struct brw_bo *buffer;
1750 unsigned flags = 0;
1751 uint32_t aligned_pitch;
1752 uint32_t tiling = I915_TILING_X;
1753 uint32_t swizzle_mode = 0;
1754
1755 buffer = brw_bo_alloc_tiled_2d(screen->bufmgr, "swizzle test",
1756 64, 64, 4, tiling, &aligned_pitch, flags);
1757 if (buffer == NULL)
1758 return false;
1759
1760 brw_bo_get_tiling(buffer, &tiling, &swizzle_mode);
1761 brw_bo_unreference(buffer);
1762
1763 if (swizzle_mode == I915_BIT_6_SWIZZLE_NONE)
1764 return false;
1765 else
1766 return true;
1767 }
1768
1769 static int
1770 intel_detect_timestamp(struct intel_screen *screen)
1771 {
1772 uint64_t dummy = 0, last = 0;
1773 int upper, lower, loops;
1774
1775 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1776 * TIMESTAMP register being shifted and the low 32bits always zero.
1777 *
1778 * More recent kernels offer an interface to read the full 36bits
1779 * everywhere.
1780 */
1781 if (brw_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0)
1782 return 3;
1783
1784 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1785 * upper 32bits for a rapidly changing timestamp.
1786 */
1787 if (brw_reg_read(screen->bufmgr, TIMESTAMP, &last))
1788 return 0;
1789
1790 upper = lower = 0;
1791 for (loops = 0; loops < 10; loops++) {
1792 /* The TIMESTAMP should change every 80ns, so several round trips
1793 * through the kernel should be enough to advance it.
1794 */
1795 if (brw_reg_read(screen->bufmgr, TIMESTAMP, &dummy))
1796 return 0;
1797
1798 upper += (dummy >> 32) != (last >> 32);
1799 if (upper > 1) /* beware 32bit counter overflow */
1800 return 2; /* upper dword holds the low 32bits of the timestamp */
1801
1802 lower += (dummy & 0xffffffff) != (last & 0xffffffff);
1803 if (lower > 1)
1804 return 1; /* timestamp is unshifted */
1805
1806 last = dummy;
1807 }
1808
1809 /* No advancement? No timestamp! */
1810 return 0;
1811 }
1812
1813 /**
1814 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1815 *
1816 * Some combinations of hardware and kernel versions allow this feature,
1817 * while others don't. Instead of trying to enumerate every case, just
1818 * try and write a register and see if works.
1819 */
1820 static bool
1821 intel_detect_pipelined_register(struct intel_screen *screen,
1822 int reg, uint32_t expected_value, bool reset)
1823 {
1824 if (screen->no_hw)
1825 return false;
1826
1827 struct brw_bo *results, *bo;
1828 uint32_t *batch;
1829 uint32_t offset = 0;
1830 void *map;
1831 bool success = false;
1832
1833 /* Create a zero'ed temporary buffer for reading our results */
1834 results = brw_bo_alloc(screen->bufmgr, "registers", 4096, 0);
1835 if (results == NULL)
1836 goto err;
1837
1838 bo = brw_bo_alloc(screen->bufmgr, "batchbuffer", 4096, 0);
1839 if (bo == NULL)
1840 goto err_results;
1841
1842 map = brw_bo_map(NULL, bo, MAP_WRITE);
1843 if (!map)
1844 goto err_batch;
1845
1846 batch = map;
1847
1848 /* Write the register. */
1849 *batch++ = MI_LOAD_REGISTER_IMM | (3 - 2);
1850 *batch++ = reg;
1851 *batch++ = expected_value;
1852
1853 /* Save the register's value back to the buffer. */
1854 *batch++ = MI_STORE_REGISTER_MEM | (3 - 2);
1855 *batch++ = reg;
1856 struct drm_i915_gem_relocation_entry reloc = {
1857 .offset = (char *) batch - (char *) map,
1858 .delta = offset * sizeof(uint32_t),
1859 .target_handle = results->gem_handle,
1860 .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
1861 .write_domain = I915_GEM_DOMAIN_INSTRUCTION,
1862 };
1863 *batch++ = reloc.presumed_offset + reloc.delta;
1864
1865 /* And afterwards clear the register */
1866 if (reset) {
1867 *batch++ = MI_LOAD_REGISTER_IMM | (3 - 2);
1868 *batch++ = reg;
1869 *batch++ = 0;
1870 }
1871
1872 *batch++ = MI_BATCH_BUFFER_END;
1873
1874 struct drm_i915_gem_exec_object2 exec_objects[2] = {
1875 {
1876 .handle = results->gem_handle,
1877 },
1878 {
1879 .handle = bo->gem_handle,
1880 .relocation_count = 1,
1881 .relocs_ptr = (uintptr_t) &reloc,
1882 }
1883 };
1884
1885 struct drm_i915_gem_execbuffer2 execbuf = {
1886 .buffers_ptr = (uintptr_t) exec_objects,
1887 .buffer_count = 2,
1888 .batch_len = ALIGN((char *) batch - (char *) map, 8),
1889 .flags = I915_EXEC_RENDER,
1890 };
1891
1892 /* Don't bother with error checking - if the execbuf fails, the
1893 * value won't be written and we'll just report that there's no access.
1894 */
1895 __DRIscreen *dri_screen = screen->driScrnPriv;
1896 drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
1897
1898 /* Check whether the value got written. */
1899 void *results_map = brw_bo_map(NULL, results, MAP_READ);
1900 if (results_map) {
1901 success = *((uint32_t *)results_map + offset) == expected_value;
1902 brw_bo_unmap(results);
1903 }
1904
1905 err_batch:
1906 brw_bo_unreference(bo);
1907 err_results:
1908 brw_bo_unreference(results);
1909 err:
1910 return success;
1911 }
1912
1913 static bool
1914 intel_detect_pipelined_so(struct intel_screen *screen)
1915 {
1916 const struct gen_device_info *devinfo = &screen->devinfo;
1917
1918 /* Supposedly, Broadwell just works. */
1919 if (devinfo->gen >= 8)
1920 return true;
1921
1922 if (devinfo->gen <= 6)
1923 return false;
1924
1925 /* See the big explanation about command parser versions below */
1926 if (screen->cmd_parser_version >= (devinfo->is_haswell ? 7 : 2))
1927 return true;
1928
1929 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1930 * statistics registers), and we already reset it to zero before using it.
1931 */
1932 return intel_detect_pipelined_register(screen,
1933 GEN7_SO_WRITE_OFFSET(0),
1934 0x1337d0d0,
1935 false);
1936 }
1937
1938 /**
1939 * Return array of MSAA modes supported by the hardware. The array is
1940 * zero-terminated and sorted in decreasing order.
1941 */
1942 const int*
1943 intel_supported_msaa_modes(const struct intel_screen *screen)
1944 {
1945 static const int gen9_modes[] = {16, 8, 4, 2, 0, -1};
1946 static const int gen8_modes[] = {8, 4, 2, 0, -1};
1947 static const int gen7_modes[] = {8, 4, 0, -1};
1948 static const int gen6_modes[] = {4, 0, -1};
1949 static const int gen4_modes[] = {0, -1};
1950
1951 if (screen->devinfo.gen >= 9) {
1952 return gen9_modes;
1953 } else if (screen->devinfo.gen >= 8) {
1954 return gen8_modes;
1955 } else if (screen->devinfo.gen >= 7) {
1956 return gen7_modes;
1957 } else if (screen->devinfo.gen == 6) {
1958 return gen6_modes;
1959 } else {
1960 return gen4_modes;
1961 }
1962 }
1963
1964 static unsigned
1965 intel_loader_get_cap(const __DRIscreen *dri_screen, enum dri_loader_cap cap)
1966 {
1967 if (dri_screen->dri2.loader && dri_screen->dri2.loader->base.version >= 4 &&
1968 dri_screen->dri2.loader->getCapability)
1969 return dri_screen->dri2.loader->getCapability(dri_screen->loaderPrivate, cap);
1970
1971 if (dri_screen->image.loader && dri_screen->image.loader->base.version >= 2 &&
1972 dri_screen->image.loader->getCapability)
1973 return dri_screen->image.loader->getCapability(dri_screen->loaderPrivate, cap);
1974
1975 return 0;
1976 }
1977
1978 static __DRIconfig**
1979 intel_screen_make_configs(__DRIscreen *dri_screen)
1980 {
1981 static const mesa_format formats[] = {
1982 MESA_FORMAT_B5G6R5_UNORM,
1983 MESA_FORMAT_B8G8R8A8_UNORM,
1984 MESA_FORMAT_B8G8R8X8_UNORM,
1985
1986 MESA_FORMAT_B8G8R8A8_SRGB,
1987
1988 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
1989 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
1990 * server may disagree on which format the GLXFBConfig represents,
1991 * resulting in swapped color channels.
1992 *
1993 * The problem, as of 2017-05-30:
1994 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
1995 * order and chooses the first __DRIconfig with the expected channel
1996 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
1997 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
1998 *
1999 * EGL does not suffer from this problem. It correctly compares the
2000 * channel masks when matching EGLConfig to __DRIconfig.
2001 */
2002
2003 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2004 MESA_FORMAT_R8G8B8A8_UNORM,
2005
2006 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2007 MESA_FORMAT_R8G8B8X8_UNORM,
2008 };
2009
2010 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
2011 static const GLenum back_buffer_modes[] = {
2012 __DRI_ATTRIB_SWAP_UNDEFINED, __DRI_ATTRIB_SWAP_NONE
2013 };
2014
2015 static const uint8_t singlesample_samples[1] = {0};
2016
2017 struct intel_screen *screen = dri_screen->driverPrivate;
2018 const struct gen_device_info *devinfo = &screen->devinfo;
2019 uint8_t depth_bits[4], stencil_bits[4];
2020 __DRIconfig **configs = NULL;
2021
2022 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2023 unsigned num_formats;
2024 if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING))
2025 num_formats = ARRAY_SIZE(formats);
2026 else
2027 num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */
2028
2029 /* Generate singlesample configs without accumulation buffer. */
2030 for (unsigned i = 0; i < num_formats; i++) {
2031 __DRIconfig **new_configs;
2032 int num_depth_stencil_bits = 2;
2033
2034 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2035 * buffer that has a different number of bits per pixel than the color
2036 * buffer, gen >= 6 supports this.
2037 */
2038 depth_bits[0] = 0;
2039 stencil_bits[0] = 0;
2040
2041 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
2042 depth_bits[1] = 16;
2043 stencil_bits[1] = 0;
2044 if (devinfo->gen >= 6) {
2045 depth_bits[2] = 24;
2046 stencil_bits[2] = 8;
2047 num_depth_stencil_bits = 3;
2048 }
2049 } else {
2050 depth_bits[1] = 24;
2051 stencil_bits[1] = 8;
2052 }
2053
2054 new_configs = driCreateConfigs(formats[i],
2055 depth_bits,
2056 stencil_bits,
2057 num_depth_stencil_bits,
2058 back_buffer_modes, 2,
2059 singlesample_samples, 1,
2060 false, false);
2061 configs = driConcatConfigs(configs, new_configs);
2062 }
2063
2064 /* Generate the minimum possible set of configs that include an
2065 * accumulation buffer.
2066 */
2067 for (unsigned i = 0; i < num_formats; i++) {
2068 __DRIconfig **new_configs;
2069
2070 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
2071 depth_bits[0] = 16;
2072 stencil_bits[0] = 0;
2073 } else {
2074 depth_bits[0] = 24;
2075 stencil_bits[0] = 8;
2076 }
2077
2078 new_configs = driCreateConfigs(formats[i],
2079 depth_bits, stencil_bits, 1,
2080 back_buffer_modes, 1,
2081 singlesample_samples, 1,
2082 true, false);
2083 configs = driConcatConfigs(configs, new_configs);
2084 }
2085
2086 /* Generate multisample configs.
2087 *
2088 * This loop breaks early, and hence is a no-op, on gen < 6.
2089 *
2090 * Multisample configs must follow the singlesample configs in order to
2091 * work around an X server bug present in 1.12. The X server chooses to
2092 * associate the first listed RGBA888-Z24S8 config, regardless of its
2093 * sample count, with the 32-bit depth visual used for compositing.
2094 *
2095 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2096 * supported. Singlebuffer configs are not supported because no one wants
2097 * them.
2098 */
2099 for (unsigned i = 0; i < num_formats; i++) {
2100 if (devinfo->gen < 6)
2101 break;
2102
2103 __DRIconfig **new_configs;
2104 const int num_depth_stencil_bits = 2;
2105 int num_msaa_modes = 0;
2106 const uint8_t *multisample_samples = NULL;
2107
2108 depth_bits[0] = 0;
2109 stencil_bits[0] = 0;
2110
2111 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
2112 depth_bits[1] = 16;
2113 stencil_bits[1] = 0;
2114 } else {
2115 depth_bits[1] = 24;
2116 stencil_bits[1] = 8;
2117 }
2118
2119 if (devinfo->gen >= 9) {
2120 static const uint8_t multisample_samples_gen9[] = {2, 4, 8, 16};
2121 multisample_samples = multisample_samples_gen9;
2122 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen9);
2123 } else if (devinfo->gen == 8) {
2124 static const uint8_t multisample_samples_gen8[] = {2, 4, 8};
2125 multisample_samples = multisample_samples_gen8;
2126 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen8);
2127 } else if (devinfo->gen == 7) {
2128 static const uint8_t multisample_samples_gen7[] = {4, 8};
2129 multisample_samples = multisample_samples_gen7;
2130 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen7);
2131 } else if (devinfo->gen == 6) {
2132 static const uint8_t multisample_samples_gen6[] = {4};
2133 multisample_samples = multisample_samples_gen6;
2134 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen6);
2135 }
2136
2137 new_configs = driCreateConfigs(formats[i],
2138 depth_bits,
2139 stencil_bits,
2140 num_depth_stencil_bits,
2141 back_buffer_modes, 1,
2142 multisample_samples,
2143 num_msaa_modes,
2144 false, false);
2145 configs = driConcatConfigs(configs, new_configs);
2146 }
2147
2148 if (configs == NULL) {
2149 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
2150 __LINE__);
2151 return NULL;
2152 }
2153
2154 return configs;
2155 }
2156
2157 static void
2158 set_max_gl_versions(struct intel_screen *screen)
2159 {
2160 __DRIscreen *dri_screen = screen->driScrnPriv;
2161 const bool has_astc = screen->devinfo.gen >= 9;
2162
2163 switch (screen->devinfo.gen) {
2164 case 10:
2165 case 9:
2166 case 8:
2167 dri_screen->max_gl_core_version = 45;
2168 dri_screen->max_gl_compat_version = 30;
2169 dri_screen->max_gl_es1_version = 11;
2170 dri_screen->max_gl_es2_version = has_astc ? 32 : 31;
2171 break;
2172 case 7:
2173 dri_screen->max_gl_core_version = 33;
2174 if (can_do_pipelined_register_writes(screen)) {
2175 dri_screen->max_gl_core_version = 42;
2176 if (screen->devinfo.is_haswell && can_do_compute_dispatch(screen))
2177 dri_screen->max_gl_core_version = 43;
2178 if (screen->devinfo.is_haswell && can_do_mi_math_and_lrr(screen))
2179 dri_screen->max_gl_core_version = 45;
2180 }
2181 dri_screen->max_gl_compat_version = 30;
2182 dri_screen->max_gl_es1_version = 11;
2183 dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30;
2184 break;
2185 case 6:
2186 dri_screen->max_gl_core_version = 33;
2187 dri_screen->max_gl_compat_version = 30;
2188 dri_screen->max_gl_es1_version = 11;
2189 dri_screen->max_gl_es2_version = 30;
2190 break;
2191 case 5:
2192 case 4:
2193 dri_screen->max_gl_core_version = 0;
2194 dri_screen->max_gl_compat_version = 21;
2195 dri_screen->max_gl_es1_version = 11;
2196 dri_screen->max_gl_es2_version = 20;
2197 break;
2198 default:
2199 unreachable("unrecognized intel_screen::gen");
2200 }
2201 }
2202
2203 /**
2204 * Return the revision (generally the revid field of the PCI header) of the
2205 * graphics device.
2206 */
2207 int
2208 intel_device_get_revision(int fd)
2209 {
2210 struct drm_i915_getparam gp;
2211 int revision;
2212 int ret;
2213
2214 memset(&gp, 0, sizeof(gp));
2215 gp.param = I915_PARAM_REVISION;
2216 gp.value = &revision;
2217
2218 ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
2219 if (ret)
2220 revision = -1;
2221
2222 return revision;
2223 }
2224
2225 static void
2226 shader_debug_log_mesa(void *data, const char *fmt, ...)
2227 {
2228 struct brw_context *brw = (struct brw_context *)data;
2229 va_list args;
2230
2231 va_start(args, fmt);
2232 GLuint msg_id = 0;
2233 _mesa_gl_vdebug(&brw->ctx, &msg_id,
2234 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2235 MESA_DEBUG_TYPE_OTHER,
2236 MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
2237 va_end(args);
2238 }
2239
2240 static void
2241 shader_perf_log_mesa(void *data, const char *fmt, ...)
2242 {
2243 struct brw_context *brw = (struct brw_context *)data;
2244
2245 va_list args;
2246 va_start(args, fmt);
2247
2248 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
2249 va_list args_copy;
2250 va_copy(args_copy, args);
2251 vfprintf(stderr, fmt, args_copy);
2252 va_end(args_copy);
2253 }
2254
2255 if (brw->perf_debug) {
2256 GLuint msg_id = 0;
2257 _mesa_gl_vdebug(&brw->ctx, &msg_id,
2258 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2259 MESA_DEBUG_TYPE_PERFORMANCE,
2260 MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
2261 }
2262 va_end(args);
2263 }
2264
2265 static int
2266 parse_devid_override(const char *devid_override)
2267 {
2268 static const struct {
2269 const char *name;
2270 int pci_id;
2271 } name_map[] = {
2272 { "brw", 0x2a02 },
2273 { "g4x", 0x2a42 },
2274 { "ilk", 0x0042 },
2275 { "snb", 0x0126 },
2276 { "ivb", 0x016a },
2277 { "hsw", 0x0d2e },
2278 { "byt", 0x0f33 },
2279 { "bdw", 0x162e },
2280 { "chv", 0x22B3 },
2281 { "skl", 0x1912 },
2282 { "bxt", 0x5A85 },
2283 { "kbl", 0x5912 },
2284 { "glk", 0x3185 },
2285 { "cnl", 0x5a52 },
2286 };
2287
2288 for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
2289 if (!strcmp(name_map[i].name, devid_override))
2290 return name_map[i].pci_id;
2291 }
2292
2293 return strtol(devid_override, NULL, 0);
2294 }
2295
2296 /**
2297 * Get the PCI ID for the device. This can be overridden by setting the
2298 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2299 *
2300 * Returns -1 on ioctl failure.
2301 */
2302 static int
2303 get_pci_device_id(struct intel_screen *screen)
2304 {
2305 if (geteuid() == getuid()) {
2306 char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
2307 if (devid_override) {
2308 screen->no_hw = true;
2309 return parse_devid_override(devid_override);
2310 }
2311 }
2312
2313 return intel_get_integer(screen, I915_PARAM_CHIPSET_ID);
2314 }
2315
2316 /**
2317 * This is the driver specific part of the createNewScreen entry point.
2318 * Called when using DRI2.
2319 *
2320 * \return the struct gl_config supported by this driver
2321 */
2322 static const
2323 __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
2324 {
2325 struct intel_screen *screen;
2326
2327 if (dri_screen->image.loader) {
2328 } else if (dri_screen->dri2.loader->base.version <= 2 ||
2329 dri_screen->dri2.loader->getBuffersWithFormat == NULL) {
2330 fprintf(stderr,
2331 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2332 "support required\n");
2333 return NULL;
2334 }
2335
2336 /* Allocate the private area */
2337 screen = rzalloc(NULL, struct intel_screen);
2338 if (!screen) {
2339 fprintf(stderr, "\nERROR! Allocating private area failed\n");
2340 return NULL;
2341 }
2342 /* parse information in __driConfigOptions */
2343 driParseOptionInfo(&screen->optionCache, brw_config_options.xml);
2344
2345 screen->driScrnPriv = dri_screen;
2346 dri_screen->driverPrivate = (void *) screen;
2347
2348 screen->deviceID = get_pci_device_id(screen);
2349
2350 if (!gen_get_device_info(screen->deviceID, &screen->devinfo))
2351 return NULL;
2352
2353 if (!intel_init_bufmgr(screen))
2354 return NULL;
2355
2356 const struct gen_device_info *devinfo = &screen->devinfo;
2357
2358 brw_process_intel_debug_variable();
2359
2360 if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
2361 fprintf(stderr,
2362 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2363 INTEL_DEBUG &= ~DEBUG_SHADER_TIME;
2364 }
2365
2366 if (intel_get_integer(screen, I915_PARAM_MMAP_GTT_VERSION) >= 1) {
2367 /* Theorectically unlimited! At least for individual objects...
2368 *
2369 * Currently the entire (global) address space for all GTT maps is
2370 * limited to 64bits. That is all objects on the system that are
2371 * setup for GTT mmapping must fit within 64bits. An attempt to use
2372 * one that exceeds the limit with fail in brw_bo_map_gtt().
2373 *
2374 * Long before we hit that limit, we will be practically limited by
2375 * that any single object must fit in physical memory (RAM). The upper
2376 * limit on the CPU's address space is currently 48bits (Skylake), of
2377 * which only 39bits can be physical memory. (The GPU itself also has
2378 * a 48bit addressable virtual space.) We can fit over 32 million
2379 * objects of the current maximum allocable size before running out
2380 * of mmap space.
2381 */
2382 screen->max_gtt_map_object_size = UINT64_MAX;
2383 } else {
2384 /* Estimate the size of the mappable aperture into the GTT. There's an
2385 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2386 * It turns out it's basically always 256MB, though some ancient hardware
2387 * was smaller.
2388 */
2389 uint32_t gtt_size = 256 * 1024 * 1024;
2390
2391 /* We don't want to map two objects such that a memcpy between them would
2392 * just fault one mapping in and then the other over and over forever. So
2393 * we would need to divide the GTT size by 2. Additionally, some GTT is
2394 * taken up by things like the framebuffer and the ringbuffer and such, so
2395 * be more conservative.
2396 */
2397 screen->max_gtt_map_object_size = gtt_size / 4;
2398 }
2399
2400 screen->aperture_threshold = get_aperture_size(dri_screen->fd) * 3 / 4;
2401
2402 screen->hw_has_swizzling = intel_detect_swizzling(screen);
2403 screen->hw_has_timestamp = intel_detect_timestamp(screen);
2404
2405 isl_device_init(&screen->isl_dev, &screen->devinfo,
2406 screen->hw_has_swizzling);
2407
2408 /* GENs prior to 8 do not support EU/Subslice info */
2409 if (devinfo->gen >= 8) {
2410 intel_detect_sseu(screen);
2411 } else if (devinfo->gen == 7) {
2412 screen->subslice_total = 1 << (devinfo->gt - 1);
2413 }
2414
2415 /* Gen7-7.5 kernel requirements / command parser saga:
2416 *
2417 * - pre-v3.16:
2418 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2419 *
2420 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2421 * all batches secure, allowing them to use any feature with no checking.
2422 * This is effectively equivalent to a command parser version of
2423 * \infinity - everything is possible.
2424 *
2425 * The command parser does not exist, and querying the version will
2426 * return -EINVAL.
2427 *
2428 * - v3.16:
2429 * The kernel enables the command parser by default, for systems with
2430 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2431 * hardware checker is still enabled, so Haswell and Baytrail cannot
2432 * do anything.
2433 *
2434 * Ivybridge goes from "everything is possible" to "only what the
2435 * command parser allows" (if the user boots with i915.cmd_parser=0,
2436 * then everything is possible again). We can only safely use features
2437 * allowed by the supported command parser version.
2438 *
2439 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2440 * implemented by the kernel, even if it's turned off. So, checking
2441 * for version > 0 does not mean that you can write registers. We have
2442 * to try it and see. The version does, however, indicate the age of
2443 * the kernel.
2444 *
2445 * Instead of matching the hardware checker's behavior of converting
2446 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2447 * -EINVAL, making it dangerous to try and use privileged features.
2448 *
2449 * Effective command parser versions:
2450 * - Haswell: 0 (reporting 1, writes don't work)
2451 * - Baytrail: 0 (reporting 1, writes don't work)
2452 * - Ivybridge: 1 (enabled) or infinite (disabled)
2453 *
2454 * - v3.17:
2455 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2456 * effectively version 1 (enabled) or infinite (disabled).
2457 *
2458 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2459 * Command parser v2 supports predicate writes.
2460 *
2461 * - Haswell: 0 (reporting 1, writes don't work)
2462 * - Baytrail: 2 (enabled) or infinite (disabled)
2463 * - Ivybridge: 2 (enabled) or infinite (disabled)
2464 *
2465 * So version >= 2 is enough to know that Ivybridge and Baytrail
2466 * will work. Haswell still can't do anything.
2467 *
2468 * - v4.0: Version 3 happened. Largely not relevant.
2469 *
2470 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2471 * L3 config registers are properly saved and restored as part
2472 * of the hardware context. We can approximately detect this point
2473 * in time by checking if I915_PARAM_REVISION is recognized - it
2474 * landed in a later commit, but in the same release cycle.
2475 *
2476 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2477 * Command parser finally gains secure batch promotion. On Haswell,
2478 * the hardware checker gets disabled, which finally allows it to do
2479 * privileged commands.
2480 *
2481 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2482 * - Haswell: 3 (enabled) or 0 (disabled)
2483 * - Baytrail: 3 (enabled) or infinite (disabled)
2484 * - Ivybridge: 3 (enabled) or infinite (disabled)
2485 *
2486 * Unfortunately, detecting this point in time is tricky, because
2487 * no version bump happened when this important change occurred.
2488 * On Haswell, if we can write any register, then the kernel is at
2489 * least this new, and we can start trusting the version number.
2490 *
2491 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2492 * Command parser reaches version 4, allowing access to Haswell
2493 * atomic scratch and chicken3 registers. If version >= 4, we know
2494 * the kernel is new enough to support privileged features on all
2495 * hardware. However, the user might have disabled it...and the
2496 * kernel will still report version 4. So we still have to guess
2497 * and check.
2498 *
2499 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2500 * Command parser v5 whitelists indirect compute shader dispatch
2501 * registers, needed for OpenGL 4.3 and later.
2502 *
2503 * - v4.8:
2504 * Command parser v7 lets us use MI_MATH on Haswell.
2505 *
2506 * Additionally, the kernel begins reporting version 0 when
2507 * the command parser is disabled, allowing us to skip the
2508 * guess-and-check step on Haswell. Unfortunately, this also
2509 * means that we can no longer use it as an indicator of the
2510 * age of the kernel.
2511 */
2512 if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION,
2513 &screen->cmd_parser_version) < 0) {
2514 /* Command parser does not exist - getparam is unrecognized */
2515 screen->cmd_parser_version = 0;
2516 }
2517
2518 /* Kernel 4.13 retuired for exec object capture */
2519 if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_CAPTURE)) {
2520 screen->kernel_features |= KERNEL_ALLOWS_EXEC_CAPTURE;
2521 }
2522
2523 if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_BATCH_FIRST)) {
2524 screen->kernel_features |= KERNEL_ALLOWS_EXEC_BATCH_FIRST;
2525 }
2526
2527 if (!intel_detect_pipelined_so(screen)) {
2528 /* We can't do anything, so the effective version is 0. */
2529 screen->cmd_parser_version = 0;
2530 } else {
2531 screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES;
2532 }
2533
2534 if (devinfo->gen >= 8 || screen->cmd_parser_version >= 2)
2535 screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES;
2536
2537 /* Haswell requires command parser version 4 in order to have L3
2538 * atomic scratch1 and chicken3 bits
2539 */
2540 if (devinfo->is_haswell && screen->cmd_parser_version >= 4) {
2541 screen->kernel_features |=
2542 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3;
2543 }
2544
2545 /* Haswell requires command parser version 6 in order to write to the
2546 * MI_MATH GPR registers, and version 7 in order to use
2547 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2548 */
2549 if (devinfo->gen >= 8 ||
2550 (devinfo->is_haswell && screen->cmd_parser_version >= 7)) {
2551 screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR;
2552 }
2553
2554 /* Gen7 needs at least command parser version 5 to support compute */
2555 if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5)
2556 screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
2557
2558 const char *force_msaa = getenv("INTEL_FORCE_MSAA");
2559 if (force_msaa) {
2560 screen->winsys_msaa_samples_override =
2561 intel_quantize_num_samples(screen, atoi(force_msaa));
2562 printf("Forcing winsys sample count to %d\n",
2563 screen->winsys_msaa_samples_override);
2564 } else {
2565 screen->winsys_msaa_samples_override = -1;
2566 }
2567
2568 set_max_gl_versions(screen);
2569
2570 /* Notification of GPU resets requires hardware contexts and a kernel new
2571 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2572 * supported, calling it with a context of 0 will either generate EPERM or
2573 * no error. If the ioctl is not supported, it always generate EINVAL.
2574 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2575 * extension to the loader.
2576 *
2577 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2578 */
2579 if (devinfo->gen >= 6) {
2580 struct drm_i915_reset_stats stats;
2581 memset(&stats, 0, sizeof(stats));
2582
2583 const int ret = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats);
2584
2585 screen->has_context_reset_notification =
2586 (ret != -1 || errno != EINVAL);
2587 }
2588
2589 dri_screen->extensions = !screen->has_context_reset_notification
2590 ? screenExtensions : intelRobustScreenExtensions;
2591
2592 screen->compiler = brw_compiler_create(screen, devinfo);
2593 screen->compiler->shader_debug_log = shader_debug_log_mesa;
2594 screen->compiler->shader_perf_log = shader_perf_log_mesa;
2595 screen->compiler->constant_buffer_0_is_relative = true;
2596 screen->compiler->supports_pull_constants = true;
2597
2598 screen->has_exec_fence =
2599 intel_get_boolean(screen, I915_PARAM_HAS_EXEC_FENCE);
2600
2601 intel_screen_init_surface_formats(screen);
2602
2603 if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
2604 unsigned int caps = intel_get_integer(screen, I915_PARAM_HAS_SCHEDULER);
2605 if (caps) {
2606 fprintf(stderr, "Kernel scheduler detected: %08x\n", caps);
2607 if (caps & I915_SCHEDULER_CAP_PRIORITY)
2608 fprintf(stderr, " - User priority sorting enabled\n");
2609 if (caps & I915_SCHEDULER_CAP_PREEMPTION)
2610 fprintf(stderr, " - Preemption enabled\n");
2611 }
2612 }
2613
2614 return (const __DRIconfig**) intel_screen_make_configs(dri_screen);
2615 }
2616
2617 struct intel_buffer {
2618 __DRIbuffer base;
2619 struct brw_bo *bo;
2620 };
2621
2622 static __DRIbuffer *
2623 intelAllocateBuffer(__DRIscreen *dri_screen,
2624 unsigned attachment, unsigned format,
2625 int width, int height)
2626 {
2627 struct intel_buffer *intelBuffer;
2628 struct intel_screen *screen = dri_screen->driverPrivate;
2629
2630 assert(attachment == __DRI_BUFFER_FRONT_LEFT ||
2631 attachment == __DRI_BUFFER_BACK_LEFT);
2632
2633 intelBuffer = calloc(1, sizeof *intelBuffer);
2634 if (intelBuffer == NULL)
2635 return NULL;
2636
2637 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2638 * supports Y tiled and compressed buffers, but there is no way to plumb that
2639 * through to here. */
2640 uint32_t pitch;
2641 int cpp = format / 8;
2642 intelBuffer->bo = brw_bo_alloc_tiled_2d(screen->bufmgr,
2643 "intelAllocateBuffer",
2644 width,
2645 height,
2646 cpp,
2647 I915_TILING_X, &pitch,
2648 BO_ALLOC_BUSY);
2649
2650 if (intelBuffer->bo == NULL) {
2651 free(intelBuffer);
2652 return NULL;
2653 }
2654
2655 brw_bo_flink(intelBuffer->bo, &intelBuffer->base.name);
2656
2657 intelBuffer->base.attachment = attachment;
2658 intelBuffer->base.cpp = cpp;
2659 intelBuffer->base.pitch = pitch;
2660
2661 return &intelBuffer->base;
2662 }
2663
2664 static void
2665 intelReleaseBuffer(__DRIscreen *dri_screen, __DRIbuffer *buffer)
2666 {
2667 struct intel_buffer *intelBuffer = (struct intel_buffer *) buffer;
2668
2669 brw_bo_unreference(intelBuffer->bo);
2670 free(intelBuffer);
2671 }
2672
2673 static const struct __DriverAPIRec brw_driver_api = {
2674 .InitScreen = intelInitScreen2,
2675 .DestroyScreen = intelDestroyScreen,
2676 .CreateContext = brwCreateContext,
2677 .DestroyContext = intelDestroyContext,
2678 .CreateBuffer = intelCreateBuffer,
2679 .DestroyBuffer = intelDestroyBuffer,
2680 .MakeCurrent = intelMakeCurrent,
2681 .UnbindContext = intelUnbindContext,
2682 .AllocateBuffer = intelAllocateBuffer,
2683 .ReleaseBuffer = intelReleaseBuffer
2684 };
2685
2686 static const struct __DRIDriverVtableExtensionRec brw_vtable = {
2687 .base = { __DRI_DRIVER_VTABLE, 1 },
2688 .vtable = &brw_driver_api,
2689 };
2690
2691 static const __DRIextension *brw_driver_extensions[] = {
2692 &driCoreExtension.base,
2693 &driImageDriverExtension.base,
2694 &driDRI2Extension.base,
2695 &brw_vtable.base,
2696 &brw_config_options.base,
2697 NULL
2698 };
2699
2700 PUBLIC const __DRIextension **__driDriverGetExtensions_i965(void)
2701 {
2702 globalDriverAPI = &brw_driver_api;
2703
2704 return brw_driver_extensions;
2705 }