src/mesa/drivers/dri/intel/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_context.h"
  29 #include "intel_batchbuffer.h"
  30 #include "intel_decode.h"
  31 #include "intel_reg.h"
  32 #include "intel_bufmgr.h"
  33 #include "intel_buffers.h"
  34
  35 void
  36 intel_batchbuffer_reset(struct intel_batchbuffer *batch)
  37 {
  38    struct intel_context *intel = batch->intel;
  39
  40    if (batch->buf != NULL) {
  41       drm_intel_bo_unreference(batch->buf);
  42       batch->buf = NULL;
  43    }
  44
  45    batch->buf = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
  46                                    intel->maxBatchSize, 4096);
  47    drm_intel_gem_bo_map_gtt(batch->buf);
  48    batch->map = batch->buf->virtual;
  49
  50    batch->size = intel->maxBatchSize;
  51    batch->ptr = batch->map;
  52    batch->reserved_space = BATCH_RESERVED;
  53    batch->dirty_state = ~0;
  54    batch->state_batch_offset = batch->size;
  55 }
  56
  57 struct intel_batchbuffer *
  58 intel_batchbuffer_alloc(struct intel_context *intel)
  59 {
  60    struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
  61
  62    batch->intel = intel;
  63    intel_batchbuffer_reset(batch);
  64
  65    return batch;
  66 }
  67
  68 void
  69 intel_batchbuffer_free(struct intel_batchbuffer *batch)
  70 {
  71    if (batch->map) {
  72       drm_intel_gem_bo_unmap_gtt(batch->buf);
  73       batch->map = NULL;
  74    }
  75    dri_bo_unreference(batch->buf);
  76    batch->buf = NULL;
  77    free(batch);
  78 }
  79
  80
  81
  82 /* TODO: Push this whole function into bufmgr.
  83  */
  84 static void
  85 do_flush_locked(struct intel_batchbuffer *batch, GLuint used)
  86 {
  87    struct intel_context *intel = batch->intel;
  88    int ret = 0;
  89    int x_off = 0, y_off = 0;
  90
  91    drm_intel_gem_bo_unmap_gtt(batch->buf);
  92
  93    batch->ptr = NULL;
  94
  95    if (!intel->no_hw) {
  96       drm_intel_bo_exec(batch->buf, used, NULL, 0,
  97                         (x_off & 0xffff) | (y_off << 16));
  98    }
  99
 100    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
 101       drm_intel_bo_map(batch->buf, GL_FALSE);
 102       intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
 103                    intel->intelScreen->deviceID, GL_TRUE);
 104       drm_intel_bo_unmap(batch->buf);
 105
 106       if (intel->vtbl.debug_batch != NULL)
 107          intel->vtbl.debug_batch(intel);
 108    }
 109
 110    if (ret != 0) {
 111       exit(1);
 112    }
 113    intel->vtbl.new_batch(intel);
 114 }
 115
 116 void
 117 _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
 118                          int line)
 119 {
 120    struct intel_context *intel = batch->intel;
 121    GLuint used = batch->ptr - batch->map;
 122
 123    if (intel->first_post_swapbuffers_batch == NULL) {
 124       intel->first_post_swapbuffers_batch = intel->batch->buf;
 125       drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
 126    }
 127
 128    if (used == 0)
 129       return;
 130
 131    if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
 132       fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
 133               used);
 134
 135    batch->reserved_space = 0;
 136
 137    if (intel->always_flush_cache) {
 138       intel_batchbuffer_emit_mi_flush(batch);
 139       used = batch->ptr - batch->map;
 140    }
 141
 142    /* Round batchbuffer usage to 2 DWORDs. */
 143
 144    if ((used & 4) == 0) {
 145       *(GLuint *) (batch->ptr) = 0; /* noop */
 146       batch->ptr += 4;
 147       used = batch->ptr - batch->map;
 148    }
 149
 150    /* Mark the end of the buffer. */
 151    *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END;
 152    batch->ptr += 4;
 153    used = batch->ptr - batch->map;
 154    assert (used <= batch->buf->size);
 155
 156    /* Workaround for recursive batchbuffer flushing: If the window is
 157     * moved, we can get into a case where we try to flush during a
 158     * flush.  What happens is that when we try to grab the lock for
 159     * the first flush, we detect that the window moved which then
 160     * causes another flush (from the intel_draw_buffer() call in
 161     * intelUpdatePageFlipping()).  To work around this we reset the
 162     * batchbuffer tail pointer before trying to get the lock.  This
 163     * prevent the nested buffer flush, but a better fix would be to
 164     * avoid that in the first place. */
 165    batch->ptr = batch->map;
 166
 167    if (intel->vtbl.finish_batch)
 168       intel->vtbl.finish_batch(intel);
 169
 170    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 171    assert(!intel->no_batch_wrap);
 172
 173    do_flush_locked(batch, used);
 174
 175    if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
 176       fprintf(stderr, "waiting for idle\n");
 177       drm_intel_bo_map(batch->buf, GL_TRUE);
 178       drm_intel_bo_unmap(batch->buf);
 179    }
 180
 181    /* Reset the buffer:
 182     */
 183    intel_batchbuffer_reset(batch);
 184 }
 185
 186
 187 /*  This is the only way buffers get added to the validate list.
 188  */
 189 GLboolean
 190 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
 191                              drm_intel_bo *buffer,
 192                              uint32_t read_domains, uint32_t write_domain,
 193                              uint32_t delta)
 194 {
 195    int ret;
 196
 197    assert(delta < buffer->size);
 198
 199    if (batch->ptr - batch->map > batch->buf->size)
 200     printf ("bad relocation ptr %p map %p offset %d size %lu\n",
 201             batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
 202    ret = drm_intel_bo_emit_reloc(batch->buf, batch->ptr - batch->map,
 203                                  buffer, delta,
 204                                  read_domains, write_domain);
 205
 206    /*
 207     * Using the old buffer offset, write in what the right data would be, in case
 208     * the buffer doesn't move and we can short-circuit the relocation processing
 209     * in the kernel
 210     */
 211    intel_batchbuffer_emit_dword (batch, buffer->offset + delta);
 212
 213    return GL_TRUE;
 214 }
 215
 216 GLboolean
 217 intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch,
 218                                     drm_intel_bo *buffer,
 219                                     uint32_t read_domains, uint32_t write_domain,
 220                                     uint32_t delta)
 221 {
 222    int ret;
 223
 224    assert(delta < buffer->size);
 225
 226    if (batch->ptr - batch->map > batch->buf->size)
 227     printf ("bad relocation ptr %p map %p offset %d size %lu\n",
 228             batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
 229    ret = drm_intel_bo_emit_reloc_fence(batch->buf, batch->ptr - batch->map,
 230                                        buffer, delta,
 231                                        read_domains, write_domain);
 232
 233    /*
 234     * Using the old buffer offset, write in what the right data would
 235     * be, in case the buffer doesn't move and we can short-circuit the
 236     * relocation processing in the kernel
 237     */
 238    intel_batchbuffer_emit_dword (batch, buffer->offset + delta);
 239
 240    return GL_TRUE;
 241 }
 242
 243 void
 244 intel_batchbuffer_data(struct intel_batchbuffer *batch,
 245                        const void *data, GLuint bytes)
 246 {
 247    assert((bytes & 3) == 0);
 248    intel_batchbuffer_require_space(batch, bytes);
 249    __memcpy(batch->ptr, data, bytes);
 250    batch->ptr += bytes;
 251 }
 252
 253 /* Emit a pipelined flush to either flush render and texture cache for
 254  * reading from a FBO-drawn texture, or flush so that frontbuffer
 255  * render appears on the screen in DRI1.
 256  *
 257  * This is also used for the always_flush_cache driconf debug option.
 258  */
 259 void
 260 intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
 261 {
 262    struct intel_context *intel = batch->intel;
 263
 264    if (intel->gen >= 6) {
 265       BEGIN_BATCH(8);
 266
 267       /* XXX workaround: issue any post sync != 0 before write cache flush = 1 */
 268       OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 269       OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
 270       OUT_BATCH(0); /* write address */
 271       OUT_BATCH(0); /* write data */
 272
 273       OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 274       OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
 275                 PIPE_CONTROL_WRITE_FLUSH |
 276                 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 277                 PIPE_CONTROL_NO_WRITE);
 278       OUT_BATCH(0); /* write address */
 279       OUT_BATCH(0); /* write data */
 280       ADVANCE_BATCH();
 281    } else if (intel->gen >= 4) {
 282       BEGIN_BATCH(4);
 283       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
 284                 PIPE_CONTROL_WRITE_FLUSH |
 285                 PIPE_CONTROL_NO_WRITE);
 286       OUT_BATCH(0); /* write address */
 287       OUT_BATCH(0); /* write data */
 288       OUT_BATCH(0); /* write data */
 289       ADVANCE_BATCH();
 290    } else {
 291       BEGIN_BATCH(1);
 292       OUT_BATCH(MI_FLUSH);
 293       ADVANCE_BATCH();
 294    }
 295 }