src/mesa/drivers/dri/intel/intel_batchbuffer.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "intel_context.h"
  29 #include "intel_batchbuffer.h"
  30 #include "intel_buffer_objects.h"
  31 #include "intel_decode.h"
  32 #include "intel_reg.h"
  33 #include "intel_bufmgr.h"
  34 #include "intel_buffers.h"
  35
  36 struct cached_batch_item {
  37    struct cached_batch_item *next;
  38    uint16_t header;
  39    uint16_t size;
  40 };
  41
  42 static void clear_cache( struct intel_context *intel )
  43 {
  44    struct cached_batch_item *item = intel->batch.cached_items;
  45
  46    while (item) {
  47       struct cached_batch_item *next = item->next;
  48       free(item);
  49       item = next;
  50    }
  51
  52    intel->batch.cached_items = NULL;
  53 }
  54
  55 void
  56 intel_batchbuffer_init(struct intel_context *intel)
  57 {
  58    intel_batchbuffer_reset(intel);
  59
  60    if (intel->gen == 6) {
  61       /* We can't just use brw_state_batch to get a chunk of space for
  62        * the gen6 workaround because it involves actually writing to
  63        * the buffer, and the kernel doesn't let us write to the batch.
  64        */
  65       intel->batch.workaround_bo = drm_intel_bo_alloc(intel->bufmgr,
  66                                                       "gen6 workaround",
  67                                                       4096, 4096);
  68    }
  69 }
  70
  71 void
  72 intel_batchbuffer_reset(struct intel_context *intel)
  73 {
  74    if (intel->batch.last_bo != NULL) {
  75       drm_intel_bo_unreference(intel->batch.last_bo);
  76       intel->batch.last_bo = NULL;
  77    }
  78    intel->batch.last_bo = intel->batch.bo;
  79
  80    clear_cache(intel);
  81
  82    intel->batch.bo = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
  83                                         intel->maxBatchSize, 4096);
  84
  85    intel->batch.reserved_space = BATCH_RESERVED;
  86    intel->batch.state_batch_offset = intel->batch.bo->size;
  87    intel->batch.used = 0;
  88 }
  89
  90 void
  91 intel_batchbuffer_free(struct intel_context *intel)
  92 {
  93    drm_intel_bo_unreference(intel->batch.last_bo);
  94    drm_intel_bo_unreference(intel->batch.bo);
  95    drm_intel_bo_unreference(intel->batch.workaround_bo);
  96    clear_cache(intel);
  97 }
  98
  99
 100 /* TODO: Push this whole function into bufmgr.
 101  */
 102 static void
 103 do_flush_locked(struct intel_context *intel)
 104 {
 105    struct intel_batchbuffer *batch = &intel->batch;
 106    int ret = 0;
 107
 108    if (!intel->intelScreen->no_hw) {
 109       int ring;
 110
 111       if (intel->gen < 6 || !batch->is_blit) {
 112          ring = I915_EXEC_RENDER;
 113       } else {
 114          ring = I915_EXEC_BLT;
 115       }
 116
 117       ret = drm_intel_bo_subdata(batch->bo, 0, 4*batch->used, batch->map);
 118       if (ret == 0 && batch->state_batch_offset != batch->bo->size) {
 119          ret = drm_intel_bo_subdata(batch->bo,
 120                                     batch->state_batch_offset,
 121                                     batch->bo->size - batch->state_batch_offset,
 122                                     (char *)batch->map + batch->state_batch_offset);
 123       }
 124
 125       if (ret == 0)
 126          ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0, ring);
 127    }
 128
 129    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
 130       intel_decode(batch->map, batch->used,
 131                    batch->bo->offset,
 132                    intel->intelScreen->deviceID, GL_TRUE);
 133
 134       if (intel->vtbl.debug_batch != NULL)
 135          intel->vtbl.debug_batch(intel);
 136    }
 137
 138    if (ret != 0) {
 139       exit(1);
 140    }
 141    intel->vtbl.new_batch(intel);
 142 }
 143
 144 void
 145 _intel_batchbuffer_flush(struct intel_context *intel,
 146                          const char *file, int line)
 147 {
 148    if (intel->batch.used == 0)
 149       return;
 150
 151    if (intel->first_post_swapbuffers_batch == NULL) {
 152       intel->first_post_swapbuffers_batch = intel->batch.bo;
 153       drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
 154    }
 155
 156    if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
 157       fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
 158               4*intel->batch.used);
 159
 160    intel->batch.reserved_space = 0;
 161
 162    if (intel->always_flush_cache) {
 163       intel_batchbuffer_emit_mi_flush(intel);
 164    }
 165
 166    /* Mark the end of the buffer. */
 167    intel_batchbuffer_emit_dword(intel, MI_BATCH_BUFFER_END);
 168    if (intel->batch.used & 1) {
 169       /* Round batchbuffer usage to 2 DWORDs. */
 170       intel_batchbuffer_emit_dword(intel, MI_NOOP);
 171    }
 172
 173    if (intel->vtbl.finish_batch)
 174       intel->vtbl.finish_batch(intel);
 175
 176    intel_upload_finish(intel);
 177
 178    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 179    assert(!intel->no_batch_wrap);
 180
 181    do_flush_locked(intel);
 182
 183    if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
 184       fprintf(stderr, "waiting for idle\n");
 185       drm_intel_bo_wait_rendering(intel->batch.bo);
 186    }
 187
 188    /* Reset the buffer:
 189     */
 190    intel_batchbuffer_reset(intel);
 191 }
 192
 193
 194 /*  This is the only way buffers get added to the validate list.
 195  */
 196 GLboolean
 197 intel_batchbuffer_emit_reloc(struct intel_context *intel,
 198                              drm_intel_bo *buffer,
 199                              uint32_t read_domains, uint32_t write_domain,
 200                              uint32_t delta)
 201 {
 202    int ret;
 203
 204    ret = drm_intel_bo_emit_reloc(intel->batch.bo, 4*intel->batch.used,
 205                                  buffer, delta,
 206                                  read_domains, write_domain);
 207    assert(ret == 0);
 208    (void)ret;
 209
 210    /*
 211     * Using the old buffer offset, write in what the right data would be, in case
 212     * the buffer doesn't move and we can short-circuit the relocation processing
 213     * in the kernel
 214     */
 215    intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
 216
 217    return GL_TRUE;
 218 }
 219
 220 GLboolean
 221 intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
 222                                     drm_intel_bo *buffer,
 223                                     uint32_t read_domains,
 224                                     uint32_t write_domain,
 225                                     uint32_t delta)
 226 {
 227    int ret;
 228
 229    ret = drm_intel_bo_emit_reloc_fence(intel->batch.bo, 4*intel->batch.used,
 230                                        buffer, delta,
 231                                        read_domains, write_domain);
 232    assert(ret == 0);
 233    (void)ret;
 234
 235    /*
 236     * Using the old buffer offset, write in what the right data would
 237     * be, in case the buffer doesn't move and we can short-circuit the
 238     * relocation processing in the kernel
 239     */
 240    intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
 241
 242    return GL_TRUE;
 243 }
 244
 245 void
 246 intel_batchbuffer_data(struct intel_context *intel,
 247                        const void *data, GLuint bytes, bool is_blit)
 248 {
 249    assert((bytes & 3) == 0);
 250    intel_batchbuffer_require_space(intel, bytes, is_blit);
 251    __memcpy(intel->batch.map + intel->batch.used, data, bytes);
 252    intel->batch.used += bytes >> 2;
 253 }
 254
 255 void
 256 intel_batchbuffer_cached_advance(struct intel_context *intel)
 257 {
 258    struct cached_batch_item **prev = &intel->batch.cached_items, *item;
 259    uint32_t sz = (intel->batch.used - intel->batch.emit) * sizeof(uint32_t);
 260    uint32_t *start = intel->batch.map + intel->batch.emit;
 261    uint16_t op = *start >> 16;
 262
 263    while (*prev) {
 264       uint32_t *old;
 265
 266       item = *prev;
 267       old = intel->batch.map + item->header;
 268       if (op == *old >> 16) {
 269          if (item->size == sz && memcmp(old, start, sz) == 0) {
 270             if (prev != &intel->batch.cached_items) {
 271                *prev = item->next;
 272                item->next = intel->batch.cached_items;
 273                intel->batch.cached_items = item;
 274             }
 275             intel->batch.used = intel->batch.emit;
 276             return;
 277          }
 278
 279          goto emit;
 280       }
 281       prev = &item->next;
 282    }
 283
 284    item = malloc(sizeof(struct cached_batch_item));
 285    if (item == NULL)
 286       return;
 287
 288    item->next = intel->batch.cached_items;
 289    intel->batch.cached_items = item;
 290
 291 emit:
 292    item->size = sz;
 293    item->header = intel->batch.emit;
 294 }
 295
 296 /**
 297  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 298  * implementing two workarounds on gen6.  From section 1.4.7.1
 299  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 300  *
 301  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 302  * produced by non-pipelined state commands), software needs to first
 303  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 304  * 0.
 305  *
 306  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 307  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 308  *
 309  * XXX: There is also a workaround that would appear to apply to this
 310  * workaround, but it doesn't appear to be necessary so far:
 311  *
 312  * Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 313  * BEFORE the pipe-control with a post-sync op and no write-cache
 314  * flushes.
 315  */
 316 void
 317 intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
 318 {
 319    if (!intel->batch.need_workaround_flush)
 320       return;
 321
 322    BEGIN_BATCH(4);
 323    OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 324    OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
 325    OUT_RELOC(intel->batch.workaround_bo,
 326              I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT, 0);
 327    OUT_BATCH(0); /* write data */
 328    ADVANCE_BATCH();
 329
 330    intel->batch.need_workaround_flush = false;
 331 }
 332
 333 /* Emit a pipelined flush to either flush render and texture cache for
 334  * reading from a FBO-drawn texture, or flush so that frontbuffer
 335  * render appears on the screen in DRI1.
 336  *
 337  * This is also used for the always_flush_cache driconf debug option.
 338  */
 339 void
 340 intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
 341 {
 342    if (intel->gen >= 6) {
 343       if (intel->batch.is_blit) {
 344          BEGIN_BATCH_BLT(4);
 345          OUT_BATCH(MI_FLUSH_DW);
 346          OUT_BATCH(0);
 347          OUT_BATCH(0);
 348          OUT_BATCH(0);
 349          ADVANCE_BATCH();
 350       } else {
 351          if (intel->gen == 6) {
 352             /* Hardware workaround: SNB B-Spec says:
 353              *
 354              * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
 355              * Flush Enable =1, a PIPE_CONTROL with any non-zero
 356              * post-sync-op is required.
 357              */
 358             intel_emit_post_sync_nonzero_flush(intel);
 359          }
 360
 361          BEGIN_BATCH(4);
 362          OUT_BATCH(_3DSTATE_PIPE_CONTROL);
 363          OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
 364                    PIPE_CONTROL_WRITE_FLUSH |
 365                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 366                    PIPE_CONTROL_NO_WRITE);
 367          OUT_BATCH(0); /* write address */
 368          OUT_BATCH(0); /* write data */
 369          ADVANCE_BATCH();
 370       }
 371    } else if (intel->gen >= 4) {
 372       BEGIN_BATCH(4);
 373       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
 374                 PIPE_CONTROL_WRITE_FLUSH |
 375                 PIPE_CONTROL_NO_WRITE);
 376       OUT_BATCH(0); /* write address */
 377       OUT_BATCH(0); /* write data */
 378       OUT_BATCH(0); /* write data */
 379       ADVANCE_BATCH();
 380    } else {
 381       BEGIN_BATCH(1);
 382       OUT_BATCH(MI_FLUSH);
 383       ADVANCE_BATCH();
 384    }
 385 }