Merge remote branch 'origin/7.8'
[mesa.git] / src / mesa / drivers / dri / nouveau / nv20_context.c
1 /*
2 * Copyright (C) 2009-2010 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #include "nouveau_driver.h"
28 #include "nouveau_context.h"
29 #include "nouveau_class.h"
30 #include "nv04_driver.h"
31 #include "nv10_driver.h"
32 #include "nv20_driver.h"
33
34 static const struct dri_extension nv20_extensions[] = {
35 { "GL_EXT_texture_rectangle", NULL },
36 { NULL, NULL }
37 };
38
39 static void
40 nv20_hwctx_init(GLcontext *ctx)
41 {
42 struct nouveau_channel *chan = context_chan(ctx);
43 struct nouveau_grobj *kelvin = context_eng3d(ctx);
44 struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw;
45 int i;
46
47 BEGIN_RING(chan, kelvin, NV20TCL_DMA_NOTIFY, 1);
48 OUT_RING (chan, hw->ntfy->handle);
49 BEGIN_RING(chan, kelvin, NV20TCL_DMA_TEXTURE0, 2);
50 OUT_RING (chan, chan->vram->handle);
51 OUT_RING (chan, chan->gart->handle);
52 BEGIN_RING(chan, kelvin, NV20TCL_DMA_COLOR, 2);
53 OUT_RING (chan, chan->vram->handle);
54 OUT_RING (chan, chan->vram->handle);
55 BEGIN_RING(chan, kelvin, NV20TCL_DMA_VTXBUF0, 2);
56 OUT_RING(chan, chan->vram->handle);
57 OUT_RING(chan, chan->gart->handle);
58
59 BEGIN_RING(chan, kelvin, NV20TCL_DMA_QUERY, 1);
60 OUT_RING (chan, 0);
61
62 BEGIN_RING(chan, kelvin, NV20TCL_RT_HORIZ, 2);
63 OUT_RING (chan, 0);
64 OUT_RING (chan, 0);
65
66 BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(0), 1);
67 OUT_RING (chan, 0xfff << 16 | 0x0);
68 BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_VERT(0), 1);
69 OUT_RING (chan, 0xfff << 16 | 0x0);
70
71 for (i = 1; i < NV20TCL_VIEWPORT_CLIP_HORIZ__SIZE; i++) {
72 BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(i), 1);
73 OUT_RING (chan, 0);
74 BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_VERT(i), 1);
75 OUT_RING (chan, 0);
76 }
77
78 BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_MODE, 1);
79 OUT_RING (chan, 0);
80
81 BEGIN_RING(chan, kelvin, 0x17e0, 3);
82 OUT_RINGf (chan, 0.0);
83 OUT_RINGf (chan, 0.0);
84 OUT_RINGf (chan, 1.0);
85
86 if (context_chipset(ctx) >= 0x25) {
87 BEGIN_RING(chan, kelvin, NV20TCL_TX_RCOMP, 1);
88 OUT_RING (chan, NV20TCL_TX_RCOMP_LEQUAL | 0xdb0);
89 } else {
90 BEGIN_RING(chan, kelvin, 0x1e68, 1);
91 OUT_RING (chan, 0x4b800000); /* 16777216.000000 */
92 BEGIN_RING(chan, kelvin, NV20TCL_TX_RCOMP, 1);
93 OUT_RING (chan, NV20TCL_TX_RCOMP_LEQUAL);
94 }
95
96 BEGIN_RING(chan, kelvin, 0x290, 1);
97 OUT_RING (chan, 0x10 << 16 | 1);
98 BEGIN_RING(chan, kelvin, 0x9fc, 1);
99 OUT_RING (chan, 0);
100 BEGIN_RING(chan, kelvin, 0x1d80, 1);
101 OUT_RING (chan, 1);
102 BEGIN_RING(chan, kelvin, 0x9f8, 1);
103 OUT_RING (chan, 4);
104 BEGIN_RING(chan, kelvin, 0x17ec, 3);
105 OUT_RINGf (chan, 0.0);
106 OUT_RINGf (chan, 1.0);
107 OUT_RINGf (chan, 0.0);
108
109 if (context_chipset(ctx) >= 0x25) {
110 BEGIN_RING(chan, kelvin, 0x1d88, 1);
111 OUT_RING (chan, 3);
112
113 BEGIN_RING(chan, kelvin, NV25TCL_DMA_IN_MEMORY9, 1);
114 OUT_RING (chan, chan->vram->handle);
115 BEGIN_RING(chan, kelvin, NV25TCL_DMA_IN_MEMORY8, 1);
116 OUT_RING (chan, chan->vram->handle);
117 }
118
119 BEGIN_RING(chan, kelvin, NV20TCL_DMA_FENCE, 1);
120 OUT_RING (chan, 0);
121
122 BEGIN_RING(chan, kelvin, 0x1e98, 1);
123 OUT_RING (chan, 0);
124
125 BEGIN_RING(chan, kelvin, NV20TCL_NOTIFY, 1);
126 OUT_RING (chan, 0);
127
128 BEGIN_RING(chan, kelvin, 0x120, 3);
129 OUT_RING (chan, 0);
130 OUT_RING (chan, 1);
131 OUT_RING (chan, 2);
132
133 if (context_chipset(ctx) >= 0x25) {
134 BEGIN_RING(chan, kelvin, 0x022c, 2);
135 OUT_RING (chan, 0x280);
136 OUT_RING (chan, 0x07d28000);
137
138 BEGIN_RING(chan, kelvin, 0x1da4, 1);
139 OUT_RING (chan, 0);
140 }
141
142 BEGIN_RING(chan, kelvin, NV20TCL_RT_HORIZ, 2);
143 OUT_RING (chan, 0 << 16 | 0);
144 OUT_RING (chan, 0 << 16 | 0);
145
146 BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_ENABLE, 1);
147 OUT_RING (chan, 0);
148 BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_FUNC, 2);
149 OUT_RING (chan, NV20TCL_ALPHA_FUNC_FUNC_ALWAYS);
150 OUT_RING (chan, 0);
151
152 for (i = 0; i < NV20TCL_TX_ENABLE__SIZE; i++) {
153 BEGIN_RING(chan, kelvin, NV20TCL_TX_ENABLE(i), 1);
154 OUT_RING (chan, 0);
155 }
156
157 BEGIN_RING(chan, kelvin, NV20TCL_TX_SHADER_OP, 1);
158 OUT_RING (chan, 0);
159 BEGIN_RING(chan, kelvin, NV20TCL_TX_SHADER_CULL_MODE, 1);
160 OUT_RING (chan, 0);
161
162 BEGIN_RING(chan, kelvin, NV20TCL_RC_IN_ALPHA(0), 4);
163 OUT_RING (chan, 0x30d410d0);
164 OUT_RING (chan, 0);
165 OUT_RING (chan, 0);
166 OUT_RING (chan, 0);
167 BEGIN_RING(chan, kelvin, NV20TCL_RC_OUT_RGB(0), 4);
168 OUT_RING (chan, 0x00000c00);
169 OUT_RING (chan, 0);
170 OUT_RING (chan, 0);
171 OUT_RING (chan, 0);
172 BEGIN_RING(chan, kelvin, NV20TCL_RC_ENABLE, 1);
173 OUT_RING (chan, 0x00011101);
174 BEGIN_RING(chan, kelvin, NV20TCL_RC_FINAL0, 2);
175 OUT_RING (chan, 0x130e0300);
176 OUT_RING (chan, 0x0c091c80);
177 BEGIN_RING(chan, kelvin, NV20TCL_RC_OUT_ALPHA(0), 4);
178 OUT_RING (chan, 0x00000c00);
179 OUT_RING (chan, 0);
180 OUT_RING (chan, 0);
181 OUT_RING (chan, 0);
182 BEGIN_RING(chan, kelvin, NV20TCL_RC_IN_RGB(0), 4);
183 OUT_RING (chan, 0x20c400c0);
184 OUT_RING (chan, 0);
185 OUT_RING (chan, 0);
186 OUT_RING (chan, 0);
187 BEGIN_RING(chan, kelvin, NV20TCL_RC_COLOR0, 2);
188 OUT_RING (chan, 0);
189 OUT_RING (chan, 0);
190 BEGIN_RING(chan, kelvin, NV20TCL_RC_CONSTANT_COLOR0(0), 4);
191 OUT_RING (chan, 0x035125a0);
192 OUT_RING (chan, 0);
193 OUT_RING (chan, 0x40002000);
194 OUT_RING (chan, 0);
195
196 BEGIN_RING(chan, kelvin, NV20TCL_MULTISAMPLE_CONTROL, 1);
197 OUT_RING (chan, 0xffff0000);
198 BEGIN_RING(chan, kelvin, NV20TCL_BLEND_FUNC_ENABLE, 1);
199 OUT_RING (chan, 0);
200 BEGIN_RING(chan, kelvin, NV20TCL_DITHER_ENABLE, 1);
201 OUT_RING (chan, 0);
202 BEGIN_RING(chan, kelvin, NV20TCL_STENCIL_ENABLE, 1);
203 OUT_RING (chan, 0);
204 BEGIN_RING(chan, kelvin, NV20TCL_BLEND_FUNC_SRC, 4);
205 OUT_RING (chan, NV20TCL_BLEND_FUNC_SRC_ONE);
206 OUT_RING (chan, NV20TCL_BLEND_FUNC_DST_ZERO);
207 OUT_RING (chan, 0);
208 OUT_RING (chan, NV20TCL_BLEND_EQUATION_FUNC_ADD);
209 BEGIN_RING(chan, kelvin, NV20TCL_STENCIL_MASK, 7);
210 OUT_RING (chan, 0xff);
211 OUT_RING (chan, NV20TCL_STENCIL_FUNC_FUNC_ALWAYS);
212 OUT_RING (chan, 0);
213 OUT_RING (chan, 0xff);
214 OUT_RING (chan, NV20TCL_STENCIL_OP_FAIL_KEEP);
215 OUT_RING (chan, NV20TCL_STENCIL_OP_ZFAIL_KEEP);
216 OUT_RING (chan, NV20TCL_STENCIL_OP_ZPASS_KEEP);
217
218 BEGIN_RING(chan, kelvin, NV20TCL_COLOR_LOGIC_OP_ENABLE, 2);
219 OUT_RING (chan, 0);
220 OUT_RING (chan, NV20TCL_COLOR_LOGIC_OP_OP_COPY);
221 BEGIN_RING(chan, kelvin, 0x17cc, 1);
222 OUT_RING (chan, 0);
223 if (context_chipset(ctx) >= 0x25) {
224 BEGIN_RING(chan, kelvin, 0x1d84, 1);
225 OUT_RING (chan, 1);
226 }
227 BEGIN_RING(chan, kelvin, NV20TCL_LIGHTING_ENABLE, 1);
228 OUT_RING (chan, 0);
229 BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_MODEL, 1);
230 OUT_RING (chan, NV20TCL_LIGHT_MODEL_VIEWER_NONLOCAL);
231 BEGIN_RING(chan, kelvin, NV20TCL_SEPARATE_SPECULAR_ENABLE, 1);
232 OUT_RING (chan, 0);
233 BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE, 1);
234 OUT_RING (chan, 0);
235 BEGIN_RING(chan, kelvin, NV20TCL_ENABLED_LIGHTS, 1);
236 OUT_RING (chan, 0);
237 BEGIN_RING(chan, kelvin, NV20TCL_NORMALIZE_ENABLE, 1);
238 OUT_RING (chan, 0);
239 BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_STIPPLE_PATTERN(0),
240 NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE);
241 for (i = 0; i < NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE; i++) {
242 OUT_RING(chan, 0xffffffff);
243 }
244
245 BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
246 OUT_RING (chan, 0);
247 OUT_RING (chan, 0);
248 OUT_RING (chan, 0);
249 BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_FUNC, 1);
250 OUT_RING (chan, NV20TCL_DEPTH_FUNC_LESS);
251 BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_WRITE_ENABLE, 1);
252 OUT_RING (chan, 0);
253 BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_TEST_ENABLE, 1);
254 OUT_RING (chan, 0);
255 BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_OFFSET_FACTOR, 2);
256 OUT_RINGf (chan, 0.0);
257 OUT_RINGf (chan, 0.0);
258 BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_UNK17D8, 1);
259 OUT_RING (chan, 1);
260 if (context_chipset(ctx) < 0x25) {
261 BEGIN_RING(chan, kelvin, 0x1d84, 1);
262 OUT_RING (chan, 3);
263 }
264 BEGIN_RING(chan, kelvin, NV20TCL_POINT_SIZE, 1);
265 if (context_chipset(ctx) >= 0x25)
266 OUT_RINGf (chan, 1.0);
267 else
268 OUT_RING (chan, 8);
269
270 if (context_chipset(ctx) >= 0x25) {
271 BEGIN_RING(chan, kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 1);
272 OUT_RING (chan, 0);
273 BEGIN_RING(chan, kelvin, 0x0a1c, 1);
274 OUT_RING (chan, 0x800);
275 } else {
276 BEGIN_RING(chan, kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 2);
277 OUT_RING (chan, 0);
278 OUT_RING (chan, 0);
279 }
280
281 BEGIN_RING(chan, kelvin, NV20TCL_LINE_WIDTH, 1);
282 OUT_RING (chan, 8);
283 BEGIN_RING(chan, kelvin, NV20TCL_LINE_SMOOTH_ENABLE, 1);
284 OUT_RING (chan, 0);
285 BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_MODE_FRONT, 2);
286 OUT_RING (chan, NV20TCL_POLYGON_MODE_FRONT_FILL);
287 OUT_RING (chan, NV20TCL_POLYGON_MODE_BACK_FILL);
288 BEGIN_RING(chan, kelvin, NV20TCL_CULL_FACE, 2);
289 OUT_RING (chan, NV20TCL_CULL_FACE_BACK);
290 OUT_RING (chan, NV20TCL_FRONT_FACE_CCW);
291 BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_SMOOTH_ENABLE, 1);
292 OUT_RING (chan, 0);
293 BEGIN_RING(chan, kelvin, NV20TCL_CULL_FACE_ENABLE, 1);
294 OUT_RING (chan, 0);
295 BEGIN_RING(chan, kelvin, NV20TCL_SHADE_MODEL, 1);
296 OUT_RING (chan, NV20TCL_SHADE_MODEL_SMOOTH);
297 BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_STIPPLE_ENABLE, 1);
298 OUT_RING (chan, 0);
299
300 BEGIN_RING(chan, kelvin, NV20TCL_TX_GEN_MODE_S(0),
301 4 * NV20TCL_TX_GEN_MODE_S__SIZE);
302 for (i=0; i < 4 * NV20TCL_TX_GEN_MODE_S__SIZE; i++)
303 OUT_RING(chan, 0);
304
305 BEGIN_RING(chan, kelvin, NV20TCL_FOG_EQUATION_CONSTANT, 3);
306 OUT_RINGf (chan, 1.5);
307 OUT_RINGf (chan, -0.090168);
308 OUT_RINGf (chan, 0.0);
309 BEGIN_RING(chan, kelvin, NV20TCL_FOG_MODE, 2);
310 OUT_RING (chan, NV20TCL_FOG_MODE_EXP_SIGNED);
311 OUT_RING (chan, NV20TCL_FOG_COORD_FOG);
312 BEGIN_RING(chan, kelvin, NV20TCL_FOG_ENABLE, 2);
313 OUT_RING (chan, 0);
314 OUT_RING (chan, 0);
315
316 BEGIN_RING(chan, kelvin, NV20TCL_ENGINE, 1);
317 OUT_RING (chan, NV20TCL_ENGINE_FIXED);
318
319 for (i = 0; i < NV20TCL_TX_MATRIX_ENABLE__SIZE; i++) {
320 BEGIN_RING(chan, kelvin, NV20TCL_TX_MATRIX_ENABLE(i), 1);
321 OUT_RING (chan, 0);
322 }
323
324 BEGIN_RING(chan, kelvin, NV20TCL_VTX_ATTR_4F_X(1), 4 * 15);
325 OUT_RINGf(chan, 1.0);
326 OUT_RINGf(chan, 0.0);
327 OUT_RINGf(chan, 0.0);
328 OUT_RINGf(chan, 1.0);
329 OUT_RINGf(chan, 0.0);
330 OUT_RINGf(chan, 0.0);
331 OUT_RINGf(chan, 1.0);
332 OUT_RINGf(chan, 1.0);
333 OUT_RINGf(chan, 1.0);
334 OUT_RINGf(chan, 1.0);
335 OUT_RINGf(chan, 1.0);
336 OUT_RINGf(chan, 1.0);
337 for (i = 0; i < 12; i++) {
338 OUT_RINGf(chan, 0.0);
339 OUT_RINGf(chan, 0.0);
340 OUT_RINGf(chan, 0.0);
341 OUT_RINGf(chan, 1.0);
342 }
343
344 BEGIN_RING(chan, kelvin, NV20TCL_EDGEFLAG_ENABLE, 1);
345 OUT_RING (chan, 1);
346 BEGIN_RING(chan, kelvin, NV20TCL_COLOR_MASK, 1);
347 OUT_RING (chan, 0x00010101);
348 BEGIN_RING(chan, kelvin, NV20TCL_CLEAR_VALUE, 1);
349 OUT_RING (chan, 0);
350
351 BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_RANGE_NEAR, 2);
352 OUT_RINGf (chan, 0.0);
353 OUT_RINGf (chan, 16777216.0);
354
355 BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_TRANSLATE_X, 4);
356 OUT_RINGf (chan, 0.0);
357 OUT_RINGf (chan, 0.0);
358 OUT_RINGf (chan, 0.0);
359 OUT_RINGf (chan, 16777215.0);
360
361 BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_SCALE_X, 4);
362 OUT_RINGf (chan, 0.0);
363 OUT_RINGf (chan, 0.0);
364 OUT_RINGf (chan, 16777215.0 * 0.5);
365 OUT_RINGf (chan, 65535.0);
366
367 FIRE_RING(chan);
368 }
369
370 static void
371 nv20_context_destroy(GLcontext *ctx)
372 {
373 struct nouveau_context *nctx = to_nouveau_context(ctx);
374
375 nv04_surface_takedown(ctx);
376 nv20_render_destroy(ctx);
377
378 nouveau_grobj_free(&nctx->hw.eng3d);
379
380 nouveau_context_deinit(ctx);
381 FREE(ctx);
382 }
383
384 static GLcontext *
385 nv20_context_create(struct nouveau_screen *screen, const GLvisual *visual,
386 GLcontext *share_ctx)
387 {
388 struct nouveau_context *nctx;
389 GLcontext *ctx;
390 unsigned kelvin_class;
391 int ret;
392
393 nctx = CALLOC_STRUCT(nouveau_context);
394 if (!nctx)
395 return NULL;
396
397 ctx = &nctx->base;
398
399 if (!nouveau_context_init(ctx, screen, visual, share_ctx))
400 goto fail;
401
402 driInitExtensions(ctx, nv20_extensions, GL_FALSE);
403
404 /* GL constants. */
405 ctx->Const.MaxTextureCoordUnits = NV20_TEXTURE_UNITS;
406 ctx->Const.MaxTextureImageUnits = NV20_TEXTURE_UNITS;
407 ctx->Const.MaxTextureUnits = NV20_TEXTURE_UNITS;
408 ctx->Const.MaxTextureMaxAnisotropy = 8;
409 ctx->Const.MaxTextureLodBias = 15;
410
411 /* 2D engine. */
412 ret = nv04_surface_init(ctx);
413 if (!ret)
414 goto fail;
415
416 /* 3D engine. */
417 if (context_chipset(ctx) >= 0x25)
418 kelvin_class = NV25TCL;
419 else
420 kelvin_class = NV20TCL;
421
422 ret = nouveau_grobj_alloc(context_chan(ctx), 0xbeef0001, kelvin_class,
423 &nctx->hw.eng3d);
424 if (ret)
425 goto fail;
426
427 nv20_hwctx_init(ctx);
428 nv20_render_init(ctx);
429
430 return ctx;
431
432 fail:
433 nv20_context_destroy(ctx);
434 return NULL;
435 }
436
437 const struct nouveau_driver nv20_driver = {
438 .context_create = nv20_context_create,
439 .context_destroy = nv20_context_destroy,
440 .surface_copy = nv04_surface_copy,
441 .surface_fill = nv04_surface_fill,
442 .emit = (nouveau_state_func[]) {
443 nv10_emit_alpha_func,
444 nv10_emit_blend_color,
445 nv10_emit_blend_equation,
446 nv10_emit_blend_func,
447 nv20_emit_clip_plane,
448 nv20_emit_clip_plane,
449 nv20_emit_clip_plane,
450 nv20_emit_clip_plane,
451 nv20_emit_clip_plane,
452 nv20_emit_clip_plane,
453 nv10_emit_color_mask,
454 nv20_emit_color_material,
455 nv10_emit_cull_face,
456 nv10_emit_front_face,
457 nv10_emit_depth,
458 nv10_emit_dither,
459 nv20_emit_frag,
460 nv20_emit_framebuffer,
461 nv20_emit_fog,
462 nv10_emit_light_enable,
463 nv20_emit_light_model,
464 nv20_emit_light_source,
465 nv20_emit_light_source,
466 nv20_emit_light_source,
467 nv20_emit_light_source,
468 nv20_emit_light_source,
469 nv20_emit_light_source,
470 nv20_emit_light_source,
471 nv20_emit_light_source,
472 nv10_emit_line_stipple,
473 nv10_emit_line_mode,
474 nv20_emit_logic_opcode,
475 nv20_emit_material_ambient,
476 nv20_emit_material_ambient,
477 nv20_emit_material_diffuse,
478 nv20_emit_material_diffuse,
479 nv20_emit_material_specular,
480 nv20_emit_material_specular,
481 nv20_emit_material_shininess,
482 nv20_emit_material_shininess,
483 nv20_emit_modelview,
484 nv20_emit_point_mode,
485 nv10_emit_point_parameter,
486 nv10_emit_polygon_mode,
487 nv10_emit_polygon_offset,
488 nv10_emit_polygon_stipple,
489 nv20_emit_projection,
490 nv10_emit_render_mode,
491 nv10_emit_scissor,
492 nv10_emit_shade_model,
493 nv10_emit_stencil_func,
494 nv10_emit_stencil_mask,
495 nv10_emit_stencil_op,
496 nv20_emit_tex_env,
497 nv20_emit_tex_env,
498 nv20_emit_tex_env,
499 nv20_emit_tex_env,
500 nv20_emit_tex_gen,
501 nv20_emit_tex_gen,
502 nv20_emit_tex_gen,
503 nv20_emit_tex_gen,
504 nv20_emit_tex_mat,
505 nv20_emit_tex_mat,
506 nv20_emit_tex_mat,
507 nv20_emit_tex_mat,
508 nv20_emit_tex_obj,
509 nv20_emit_tex_obj,
510 nv20_emit_tex_obj,
511 nv20_emit_tex_obj,
512 nv20_emit_viewport,
513 nv20_emit_tex_shader
514 },
515 .num_emit = NUM_NV20_STATE,
516 };