src/mesa/drivers/dri/r200/r200_blit.c

   1 /*
   2  * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r200_context.h"
  30 #include "r200_blit.h"
  31
  32 static inline uint32_t cmdpacket0(struct radeon_screen *rscrn,
  33                                   int reg, int count)
  34 {
  35     if (count)
  36             return CP_PACKET0(reg, count - 1);
  37     return CP_PACKET2;
  38 }
  39
  40 /* common formats supported as both textures and render targets */
  41 static unsigned is_blit_supported(gl_format mesa_format)
  42 {
  43     /* XXX others?  BE/LE? */
  44     switch (mesa_format) {
  45     case MESA_FORMAT_ARGB8888:
  46     case MESA_FORMAT_XRGB8888:
  47     case MESA_FORMAT_RGB565:
  48     case MESA_FORMAT_ARGB4444:
  49     case MESA_FORMAT_ARGB1555:
  50     case MESA_FORMAT_A8:
  51             break;
  52     default:
  53             return 0;
  54     }
  55
  56     /* ??? */
  57     if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
  58             return 0;
  59
  60     return 1;
  61 }
  62
  63 static inline void emit_vtx_state(struct r200_context *r200)
  64 {
  65     BATCH_LOCALS(&r200->radeon);
  66
  67     BEGIN_BATCH(14);
  68     if (r200->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
  69             OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, 0);
  70     } else {
  71             OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
  72     }
  73     OUT_BATCH_REGVAL(R200_SE_VAP_CNTL, (R200_VAP_FORCE_W_TO_ONE |
  74                                         (9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT)));
  75     OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL, 0);
  76     OUT_BATCH_REGVAL(R200_SE_VTE_CNTL, 0);
  77     OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0, R200_VTX_XY);
  78     OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
  79     OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
  80                                       RADEON_BFACE_SOLID |
  81                                       RADEON_FFACE_SOLID |
  82                                       RADEON_VTX_PIX_CENTER_OGL |
  83                                       RADEON_ROUND_MODE_ROUND |
  84                                       RADEON_ROUND_PREC_4TH_PIX));
  85     END_BATCH();
  86 }
  87
  88 static void inline emit_tx_setup(struct r200_context *r200,
  89                                  gl_format mesa_format,
  90                                  struct radeon_bo *bo,
  91                                  intptr_t offset,
  92                                  unsigned width,
  93                                  unsigned height,
  94                                  unsigned pitch)
  95 {
  96     uint32_t txformat = R200_TXFORMAT_NON_POWER2;
  97     BATCH_LOCALS(&r200->radeon);
  98
  99     assert(width <= 2047);
 100     assert(height <= 2047);
 101     assert(offset % 32 == 0);
 102
 103     /* XXX others?  BE/LE? */
 104     switch (mesa_format) {
 105     case MESA_FORMAT_ARGB8888:
 106             txformat |= R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP;
 107             break;
 108     case MESA_FORMAT_XRGB8888:
 109             txformat |= R200_TXFORMAT_ARGB8888;
 110             break;
 111     case MESA_FORMAT_RGB565:
 112             txformat |= R200_TXFORMAT_RGB565;
 113             break;
 114     case MESA_FORMAT_ARGB4444:
 115             txformat |= R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP;
 116             break;
 117     case MESA_FORMAT_ARGB1555:
 118             txformat |= R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP;
 119             break;
 120     case MESA_FORMAT_A8:
 121             txformat |= R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP;
 122             break;
 123     default:
 124             break;
 125     }
 126
 127     BEGIN_BATCH(28);
 128     OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
 129     OUT_BATCH_REGVAL(R200_PP_CNTL_X, 0);
 130     OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0, 0);
 131     OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO |
 132                                           R200_TXC_ARG_B_ZERO |
 133                                           R200_TXC_ARG_C_R0_COLOR |
 134                                           R200_TXC_OP_MADD));
 135     OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
 136     OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO |
 137                                           R200_TXA_ARG_B_ZERO |
 138                                           R200_TXA_ARG_C_R0_ALPHA |
 139                                           R200_TXA_OP_MADD));
 140     OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
 141     OUT_BATCH_REGVAL(R200_PP_TXFILTER_0, (R200_CLAMP_S_CLAMP_LAST |
 142                                           R200_CLAMP_T_CLAMP_LAST |
 143                                           R200_MAG_FILTER_NEAREST |
 144                                           R200_MIN_FILTER_NEAREST));
 145     OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0, txformat);
 146     OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0, 0);
 147     OUT_BATCH_REGVAL(R200_PP_TXSIZE_0, ((width - 1) |
 148                                         ((height - 1) << RADEON_TEX_VSIZE_SHIFT)));
 149     OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32);
 150
 151     OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1);
 152     OUT_BATCH_RELOC(0, bo, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 153
 154     END_BATCH();
 155 }
 156
 157 static inline void emit_cb_setup(struct r200_context *r200,
 158                                  struct radeon_bo *bo,
 159                                  intptr_t offset,
 160                                  gl_format mesa_format,
 161                                  unsigned pitch,
 162                                  unsigned width,
 163                                  unsigned height)
 164 {
 165     uint32_t dst_pitch = pitch;
 166     uint32_t dst_format = 0;
 167     BATCH_LOCALS(&r200->radeon);
 168
 169     /* XXX others?  BE/LE? */
 170     switch (mesa_format) {
 171     case MESA_FORMAT_ARGB8888:
 172     case MESA_FORMAT_XRGB8888:
 173             dst_format = RADEON_COLOR_FORMAT_ARGB8888;
 174             break;
 175     case MESA_FORMAT_RGB565:
 176             dst_format = RADEON_COLOR_FORMAT_RGB565;
 177             break;
 178     case MESA_FORMAT_ARGB4444:
 179             dst_format = RADEON_COLOR_FORMAT_ARGB4444;
 180             break;
 181     case MESA_FORMAT_ARGB1555:
 182             dst_format = RADEON_COLOR_FORMAT_ARGB1555;
 183             break;
 184     case MESA_FORMAT_A8:
 185             dst_format = RADEON_COLOR_FORMAT_RGB8;
 186             break;
 187     default:
 188             break;
 189     }
 190
 191     BEGIN_BATCH_NO_AUTOSTATE(22);
 192     OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0);
 193     OUT_BATCH_REGVAL(R200_RE_CNTL, 0);
 194     OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0);
 195     OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, ((width << RADEON_RE_WIDTH_SHIFT) |
 196                                               (height << RADEON_RE_HEIGHT_SHIFT)));
 197     OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff);
 198     OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO);
 199     OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format);
 200
 201     OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1);
 202     OUT_BATCH_RELOC(0, bo, 0, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 203     OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1);
 204     OUT_BATCH_RELOC(dst_pitch, bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
 205
 206     END_BATCH();
 207 }
 208
 209 static GLboolean validate_buffers(struct r200_context *r200,
 210                                   struct radeon_bo *src_bo,
 211                                   struct radeon_bo *dst_bo)
 212 {
 213     int ret;
 214     radeon_cs_space_add_persistent_bo(r200->radeon.cmdbuf.cs,
 215                                       src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
 216
 217     radeon_cs_space_add_persistent_bo(r200->radeon.cmdbuf.cs,
 218                                       dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
 219
 220     ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs,
 221                                         first_elem(&r200->radeon.dma.reserved)->bo,
 222                                         RADEON_GEM_DOMAIN_GTT, 0);
 223     if (ret)
 224         return GL_FALSE;
 225
 226     return GL_TRUE;
 227 }
 228
 229 /**
 230  * Calculate texcoords for given image region.
 231  * Output values are [minx, maxx, miny, maxy]
 232  */
 233 static inline void calc_tex_coords(float img_width, float img_height,
 234                                    float x, float y,
 235                                    float reg_width, float reg_height,
 236                                    unsigned flip_y, float *buf)
 237 {
 238     buf[0] = x / img_width;
 239     buf[1] = buf[0] + reg_width / img_width;
 240     buf[2] = y / img_height;
 241     buf[3] = buf[2] + reg_height / img_height;
 242     if (flip_y)
 243     {
 244         buf[2] = 1.0 - buf[2];
 245         buf[3] = 1.0 - buf[3];
 246     }
 247 }
 248
 249 static inline void emit_draw_packet(struct r200_context *r200,
 250                                     unsigned src_width, unsigned src_height,
 251                                     unsigned src_x_offset, unsigned src_y_offset,
 252                                     unsigned dst_x_offset, unsigned dst_y_offset,
 253                                     unsigned reg_width, unsigned reg_height,
 254                                     unsigned flip_y)
 255 {
 256     float texcoords[4];
 257     float verts[12];
 258     BATCH_LOCALS(&r200->radeon);
 259
 260     calc_tex_coords(src_width, src_height,
 261                     src_x_offset, src_y_offset,
 262                     reg_width, reg_height,
 263                     flip_y, texcoords);
 264
 265     verts[0] = dst_x_offset;
 266     verts[1] = dst_y_offset + reg_height;
 267     verts[2] = texcoords[0];
 268     verts[3] = texcoords[3];
 269
 270     verts[4] = dst_x_offset + reg_width;
 271     verts[5] = dst_y_offset + reg_height;
 272     verts[6] = texcoords[1];
 273     verts[7] = texcoords[3];
 274
 275     verts[8] = dst_x_offset + reg_width;
 276     verts[9] = dst_y_offset;
 277     verts[10] = texcoords[1];
 278     verts[11] = texcoords[2];
 279
 280     BEGIN_BATCH(14);
 281     OUT_BATCH(R200_CP_CMD_3D_DRAW_IMMD_2 | (12 << 16));
 282     OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING |
 283               RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
 284               (3 << 16));
 285     OUT_BATCH_TABLE(verts, 12);
 286     END_BATCH();
 287 }
 288
 289 /**
 290  * Copy a region of [@a width x @a height] pixels from source buffer
 291  * to destination buffer.
 292  * @param[in] r200 r200 context
 293  * @param[in] src_bo source radeon buffer object
 294  * @param[in] src_offset offset of the source image in the @a src_bo
 295  * @param[in] src_mesaformat source image format
 296  * @param[in] src_pitch aligned source image width
 297  * @param[in] src_width source image width
 298  * @param[in] src_height source image height
 299  * @param[in] src_x_offset x offset in the source image
 300  * @param[in] src_y_offset y offset in the source image
 301  * @param[in] dst_bo destination radeon buffer object
 302  * @param[in] dst_offset offset of the destination image in the @a dst_bo
 303  * @param[in] dst_mesaformat destination image format
 304  * @param[in] dst_pitch aligned destination image width
 305  * @param[in] dst_width destination image width
 306  * @param[in] dst_height destination image height
 307  * @param[in] dst_x_offset x offset in the destination image
 308  * @param[in] dst_y_offset y offset in the destination image
 309  * @param[in] width region width
 310  * @param[in] height region height
 311  * @param[in] flip_y set if y coords of the source image need to be flipped
 312  */
 313 unsigned r200_blit(GLcontext *ctx,
 314                    struct radeon_bo *src_bo,
 315                    intptr_t src_offset,
 316                    gl_format src_mesaformat,
 317                    unsigned src_pitch,
 318                    unsigned src_width,
 319                    unsigned src_height,
 320                    unsigned src_x_offset,
 321                    unsigned src_y_offset,
 322                    struct radeon_bo *dst_bo,
 323                    intptr_t dst_offset,
 324                    gl_format dst_mesaformat,
 325                    unsigned dst_pitch,
 326                    unsigned dst_width,
 327                    unsigned dst_height,
 328                    unsigned dst_x_offset,
 329                    unsigned dst_y_offset,
 330                    unsigned reg_width,
 331                    unsigned reg_height,
 332                    unsigned flip_y)
 333 {
 334     struct r200_context *r200 = R200_CONTEXT(ctx);
 335
 336     if (!is_blit_supported(dst_mesaformat))
 337         return GL_FALSE;
 338
 339     /* Make sure that colorbuffer has even width - hw limitation */
 340     if (dst_pitch % 2 > 0)
 341         ++dst_pitch;
 342
 343     /* Rendering to small buffer doesn't work.
 344      * Looks like a hw limitation.
 345      */
 346     if (dst_pitch < 32)
 347         return GL_FALSE;
 348
 349     /* Need to clamp the region size to make sure
 350      * we don't read outside of the source buffer
 351      * or write outside of the destination buffer.
 352      */
 353     if (reg_width + src_x_offset > src_width)
 354         reg_width = src_width - src_x_offset;
 355     if (reg_height + src_y_offset > src_height)
 356         reg_height = src_height - src_y_offset;
 357     if (reg_width + dst_x_offset > dst_width)
 358         reg_width = dst_width - dst_x_offset;
 359     if (reg_height + dst_y_offset > dst_height)
 360         reg_height = dst_height - dst_y_offset;
 361
 362     if (src_bo == dst_bo) {
 363         return GL_FALSE;
 364     }
 365
 366     if (src_offset % 32 || dst_offset % 32) {
 367         return GL_FALSE;
 368     }
 369
 370     if (0) {
 371         fprintf(stderr, "src: size [%d x %d], pitch %d, "
 372                 "offset [%d x %d], format %s, bo %p\n",
 373                 src_width, src_height, src_pitch,
 374                 src_x_offset, src_y_offset,
 375                 _mesa_get_format_name(src_mesaformat),
 376                 src_bo);
 377         fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
 378                 dst_pitch, dst_x_offset, dst_y_offset,
 379                 _mesa_get_format_name(dst_mesaformat), dst_bo);
 380         fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
 381     }
 382
 383     /* Flush is needed to make sure that source buffer has correct data */
 384     radeonFlush(r200->radeon.glCtx);
 385
 386     rcommonEnsureCmdBufSpace(&r200->radeon, 78, __FUNCTION__);
 387
 388     if (!validate_buffers(r200, src_bo, dst_bo))
 389         return GL_FALSE;
 390
 391     /* 14 */
 392     emit_vtx_state(r200);
 393     /* 28 */
 394     emit_tx_setup(r200, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
 395     /* 22 */
 396     emit_cb_setup(r200, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
 397     /* 14 */
 398     emit_draw_packet(r200, src_width, src_height,
 399                      src_x_offset, src_y_offset,
 400                      dst_x_offset, dst_y_offset,
 401                      reg_width, reg_height,
 402                      flip_y);
 403
 404     radeonFlush(ctx);
 405
 406     return GL_TRUE;
 407 }