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[mesa.git] / src / mesa / drivers / dri / r200 / r200_state_init.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 /*
30 * Authors:
31 * Keith Whitwell <keithw@vmware.com>
32 */
33
34 #include "main/errors.h"
35 #include "main/glheader.h"
36
37 #include "main/enums.h"
38 #include "main/api_arrayelt.h"
39 #include "main/state.h"
40
41 #include "swrast/swrast.h"
42 #include "vbo/vbo.h"
43 #include "tnl/t_pipeline.h"
44 #include "swrast_setup/swrast_setup.h"
45
46 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
48 #include "r200_context.h"
49 #include "r200_ioctl.h"
50 #include "r200_state.h"
51 #include "radeon_queryobj.h"
52
53 #include "util/xmlpool.h"
54
55 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
56 * 1.3 cmdbuffers allow all previous state to be updated as well as
57 * the tcl scalar and vector areas.
58 */
59 static struct {
60 int start;
61 int len;
62 const char *name;
63 } packet[RADEON_MAX_STATE_PACKETS] = {
64 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
65 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
66 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
67 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
68 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
69 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
70 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
71 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
72 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
73 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
74 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
75 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
76 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
77 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
78 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
79 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
80 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
81 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
82 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
83 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
84 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
85 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
86 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
87 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
88 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
89 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
90 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
91 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
92 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
93 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
94 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
95 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
96 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
97 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
98 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
99 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
100 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
101 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
102 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
103 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
104 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
105 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
106 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
107 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
108 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
109 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
110 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
111 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
112 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
113 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
114 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
115 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
116 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
117 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
118 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
119 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
120 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
121 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
122 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
123 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
124 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
125 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
126 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
127 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
128 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
129 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
130 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
131 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
132 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
133 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
134 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
135 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
136 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
137 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
138 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
139 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
140 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
141 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
142 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
143 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
144 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
145 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
146 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
147 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
148 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
149 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
150 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
151 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
152 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
153 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
154 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
155 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
156 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
157 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
158 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
159 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
160 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
161 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
162 };
163
164 /* =============================================================
165 * State initialization
166 */
167 static int cmdpkt( r200ContextPtr rmesa, int id )
168 {
169 return CP_PACKET0(packet[id].start, packet[id].len - 1);
170 }
171
172 static int cmdvec( int offset, int stride, int count )
173 {
174 drm_radeon_cmd_header_t h;
175 h.i = 0;
176 h.vectors.cmd_type = RADEON_CMD_VECTORS;
177 h.vectors.offset = offset;
178 h.vectors.stride = stride;
179 h.vectors.count = count;
180 return h.i;
181 }
182
183 /* warning: the count here is divided by 4 compared to other cmds
184 (so it doesn't exceed the char size)! */
185 static int cmdveclinear( int offset, int count )
186 {
187 drm_radeon_cmd_header_t h;
188 h.i = 0;
189 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR;
190 h.veclinear.addr_lo = offset & 0xff;
191 h.veclinear.addr_hi = (offset & 0xff00) >> 8;
192 h.veclinear.count = count;
193 return h.i;
194 }
195
196 static int cmdscl( int offset, int stride, int count )
197 {
198 drm_radeon_cmd_header_t h;
199 h.i = 0;
200 h.scalars.cmd_type = RADEON_CMD_SCALARS;
201 h.scalars.offset = offset;
202 h.scalars.stride = stride;
203 h.scalars.count = count;
204 return h.i;
205 }
206
207 static int cmdscl2( int offset, int stride, int count )
208 {
209 drm_radeon_cmd_header_t h;
210 h.i = 0;
211 h.scalars.cmd_type = RADEON_CMD_SCALARS2;
212 h.scalars.offset = offset - 0x100;
213 h.scalars.stride = stride;
214 h.scalars.count = count;
215 return h.i;
216 }
217
218 /**
219 * Check functions are used to check if state is active.
220 * If it is active check function returns maximum emit size.
221 */
222 #define CHECK( NM, FLAG, ADD ) \
223 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \
224 { \
225 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
226 (void) rmesa; \
227 return (FLAG) ? atom->cmd_size + (ADD) : 0; \
228 }
229
230 #define TCL_CHECK( NM, FLAG, ADD ) \
231 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \
232 { \
233 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
234 return (!rmesa->radeon.TclFallback && !_mesa_arb_vertex_program_enabled(ctx) && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
235 }
236
237 #define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \
238 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \
239 { \
240 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
241 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
242 }
243
244 #define VP_CHECK( NM, FLAG, ADD ) \
245 static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \
246 { \
247 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
248 (void) atom; \
249 return (!rmesa->radeon.TclFallback && _mesa_arb_vertex_program_enabled(ctx) && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
250 }
251
252 CHECK( always, GL_TRUE, 0 )
253 CHECK( always_add4, GL_TRUE, 4 )
254 CHECK( never, GL_FALSE, 0 )
255 CHECK( tex_any, ctx->Texture._MaxEnabledTexImageUnit != -1, 0 )
256 CHECK( tf, (ctx->Texture._MaxEnabledTexImageUnit != -1 && !_mesa_ati_fragment_shader_enabled(ctx)), 0 );
257 CHECK( pix_zero, !_mesa_ati_fragment_shader_enabled(ctx), 0 )
258 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !_mesa_ati_fragment_shader_enabled(ctx)), 0 )
259 CHECK( afs_pass1, (_mesa_ati_fragment_shader_enabled(ctx) && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 )
260 CHECK( afs, _mesa_ati_fragment_shader_enabled(ctx), 0 )
261 CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE )
262 CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 + 4*5 - CUBE_STATE_SIZE )
263 TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 )
264 TCL_CHECK( tcl, GL_TRUE, 0 )
265 TCL_CHECK( tcl_add8, GL_TRUE, 8 )
266 TCL_CHECK( tcl_add4, GL_TRUE, 4 )
267 TCL_CHECK( tcl_tex_add4, rmesa->state.texture.unit[atom->idx].unitneeded, 4 )
268 TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 )
269 TCL_CHECK( tcl_lighting_add6, ctx->Light.Enabled, 6 )
270 TCL_CHECK( tcl_light_add6, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 6 )
271 TCL_OR_VP_CHECK( tcl_ucp_add4, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 4 )
272 TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE, 0 )
273 TCL_OR_VP_CHECK( tcl_or_vp_add2, GL_TRUE, 2 )
274 VP_CHECK( tcl_vp, GL_TRUE, 0 )
275 VP_CHECK( tcl_vp_add4, GL_TRUE, 4 )
276 VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->arb.NumNativeInstructions > 64, 4 )
277 VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->arb.NumNativeParameters > 96, 4 )
278
279 #define OUT_VEC(hdr, data) do { \
280 drm_radeon_cmd_header_t h; \
281 h.i = hdr; \
282 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
283 OUT_BATCH(0); \
284 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
285 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
286 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
287 OUT_BATCH_TABLE((data), h.vectors.count); \
288 } while(0)
289
290 #define OUT_VECLINEAR(hdr, data) do { \
291 drm_radeon_cmd_header_t h; \
292 uint32_t _start, _sz; \
293 h.i = hdr; \
294 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \
295 _sz = h.veclinear.count * 4; \
296 if (_sz) { \
297 BEGIN_BATCH(dwords); \
298 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
299 OUT_BATCH(0); \
300 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
301 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
302 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \
303 OUT_BATCH_TABLE((data), _sz); \
304 END_BATCH(); \
305 } \
306 } while(0)
307
308 #define OUT_SCL(hdr, data) do { \
309 drm_radeon_cmd_header_t h; \
310 h.i = hdr; \
311 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
312 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
313 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
314 OUT_BATCH_TABLE((data), h.scalars.count); \
315 } while(0)
316
317 #define OUT_SCL2(hdr, data) do { \
318 drm_radeon_cmd_header_t h; \
319 h.i = hdr; \
320 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
321 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
322 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
323 OUT_BATCH_TABLE((data), h.scalars.count); \
324 } while(0)
325 static int check_rrb(struct gl_context *ctx, struct radeon_state_atom *atom)
326 {
327 r200ContextPtr r200 = R200_CONTEXT(ctx);
328 struct radeon_renderbuffer *rrb;
329 rrb = radeon_get_colorbuffer(&r200->radeon);
330 if (!rrb || !rrb->bo)
331 return 0;
332 return atom->cmd_size;
333 }
334
335 static int check_polygon_stipple(struct gl_context *ctx,
336 struct radeon_state_atom *atom)
337 {
338 r200ContextPtr r200 = R200_CONTEXT(ctx);
339 if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE)
340 return atom->cmd_size;
341 return 0;
342 }
343
344 static void mtl_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
345 {
346 r200ContextPtr r200 = R200_CONTEXT(ctx);
347 BATCH_LOCALS(&r200->radeon);
348 uint32_t dwords = atom->check(ctx, atom);
349
350 BEGIN_BATCH(dwords);
351 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1));
352 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18));
353 END_BATCH();
354 }
355
356 static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
357 {
358 r200ContextPtr r200 = R200_CONTEXT(ctx);
359 BATCH_LOCALS(&r200->radeon);
360 uint32_t dwords = atom->check(ctx, atom);
361
362 BEGIN_BATCH(dwords);
363 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
364 OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
365 END_BATCH();
366 }
367
368 static void ptp_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
369 {
370 r200ContextPtr r200 = R200_CONTEXT(ctx);
371 BATCH_LOCALS(&r200->radeon);
372 uint32_t dwords = atom->check(ctx, atom);
373
374 BEGIN_BATCH(dwords);
375 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1);
376 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1);
377 END_BATCH();
378 }
379
380 static void veclinear_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
381 {
382 r200ContextPtr r200 = R200_CONTEXT(ctx);
383 BATCH_LOCALS(&r200->radeon);
384 uint32_t dwords = atom->check(ctx, atom);
385
386 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1);
387 }
388
389 static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
390 {
391 r200ContextPtr r200 = R200_CONTEXT(ctx);
392 BATCH_LOCALS(&r200->radeon);
393 uint32_t dwords = atom->check(ctx, atom);
394
395 BEGIN_BATCH(dwords);
396 OUT_SCL(atom->cmd[0], atom->cmd+1);
397 END_BATCH();
398 }
399
400
401 static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
402 {
403 r200ContextPtr r200 = R200_CONTEXT(ctx);
404 BATCH_LOCALS(&r200->radeon);
405 uint32_t dwords = atom->check(ctx, atom);
406
407 BEGIN_BATCH(dwords);
408 OUT_VEC(atom->cmd[0], atom->cmd+1);
409 END_BATCH();
410 }
411
412 static int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom)
413 {
414 r200ContextPtr r200 = R200_CONTEXT(ctx);
415 struct radeon_renderbuffer *rrb, *drb;
416 uint32_t dwords;
417
418 rrb = radeon_get_colorbuffer(&r200->radeon);
419 if (!rrb || !rrb->bo) {
420 return 0;
421 }
422
423 drb = radeon_get_depthbuffer(&r200->radeon);
424
425 dwords = 10;
426 if (drb)
427 dwords += 6;
428 if (rrb)
429 dwords += 8;
430 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM)
431 dwords += 4;
432
433
434 return dwords;
435 }
436
437 static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
438 {
439 r200ContextPtr r200 = R200_CONTEXT(ctx);
440 BATCH_LOCALS(&r200->radeon);
441 struct radeon_renderbuffer *rrb, *drb;
442 uint32_t cbpitch = 0;
443 uint32_t zbpitch = 0;
444 uint32_t dwords = atom->check(ctx, atom);
445 uint32_t depth_fmt;
446
447 rrb = radeon_get_colorbuffer(&r200->radeon);
448 if (!rrb || !rrb->bo) {
449 return;
450 }
451
452 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
453 if (rrb->cpp == 4)
454 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
455 else switch (rrb->base.Base.Format) {
456 case MESA_FORMAT_B5G6R5_UNORM:
457 case MESA_FORMAT_R5G6B5_UNORM:
458 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
459 break;
460 case MESA_FORMAT_B4G4R4A4_UNORM:
461 case MESA_FORMAT_A4R4G4B4_UNORM:
462 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
463 break;
464 case MESA_FORMAT_B5G5R5A1_UNORM:
465 case MESA_FORMAT_A1R5G5B5_UNORM:
466 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
467 break;
468 default:
469 _mesa_problem(ctx, "Unexpected format in ctx_emit_cs");
470 }
471
472 cbpitch = (rrb->pitch / rrb->cpp);
473 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
474 cbpitch |= R200_COLOR_TILE_ENABLE;
475 if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
476 cbpitch |= R200_COLOR_MICROTILE_ENABLE;
477
478
479 drb = radeon_get_depthbuffer(&r200->radeon);
480 if (drb) {
481 zbpitch = (drb->pitch / drb->cpp);
482 if (drb->cpp == 4)
483 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
484 else
485 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
486 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
487 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
488 }
489
490 /* output the first 7 bytes of context */
491 BEGIN_BATCH(dwords);
492
493 /* In the CS case we need to split this up */
494 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
495 OUT_BATCH_TABLE((atom->cmd + 1), 4);
496
497 if (drb) {
498 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
499 OUT_BATCH_RELOC(drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
500
501 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
502 OUT_BATCH(zbpitch);
503 }
504
505 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
506 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
507 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
508 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
509 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
510
511
512 if (rrb) {
513 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
514 OUT_BATCH_RELOC(rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
515
516 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
517 OUT_BATCH_RELOC(rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
518 }
519
520 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
521 OUT_BATCH_TABLE((atom->cmd + 14), 4);
522 }
523
524 END_BATCH();
525 }
526
527 static int get_tex_mm_size(struct gl_context* ctx, struct radeon_state_atom *atom)
528 {
529 r200ContextPtr r200 = R200_CONTEXT(ctx);
530 uint32_t dwords = atom->cmd_size + 2;
531 int hastexture = 1;
532 int i = atom->idx;
533 radeonTexObj *t = r200->state.texture.unit[i].texobj;
534 if (!t)
535 hastexture = 0;
536 else {
537 if (!t->mt && !t->bo)
538 hastexture = 0;
539 }
540
541 if (!hastexture)
542 dwords -= 4;
543 return dwords;
544 }
545
546 static int check_tex_pair_mm(struct gl_context* ctx, struct radeon_state_atom *atom)
547 {
548 r200ContextPtr r200 = R200_CONTEXT(ctx);
549 /** XOR is bit flip operation so use it for finding pair */
550 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded))
551 return 0;
552
553 return get_tex_mm_size(ctx, atom);
554 }
555
556 static int check_tex_mm(struct gl_context* ctx, struct radeon_state_atom *atom)
557 {
558 r200ContextPtr r200 = R200_CONTEXT(ctx);
559 if (!(r200->state.texture.unit[atom->idx].unitneeded))
560 return 0;
561
562 return get_tex_mm_size(ctx, atom);
563 }
564
565
566 static void tex_emit_mm(struct gl_context *ctx, struct radeon_state_atom *atom)
567 {
568 r200ContextPtr r200 = R200_CONTEXT(ctx);
569 BATCH_LOCALS(&r200->radeon);
570 uint32_t dwords = atom->check(ctx, atom);
571 int i = atom->idx;
572 radeonTexObj *t = r200->state.texture.unit[i].texobj;
573
574 if (!r200->state.texture.unit[i].unitneeded && !(dwords <= atom->cmd_size))
575 dwords -= 4;
576 BEGIN_BATCH(dwords);
577
578 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7));
579 OUT_BATCH_TABLE((atom->cmd + 1), 8);
580
581 if (dwords > atom->cmd_size) {
582 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
583 if (t->mt && !t->image_override) {
584 OUT_BATCH_RELOC(t->mt->bo, t->tile_bits,
585 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
586 } else {
587 if (t->bo)
588 OUT_BATCH_RELOC(t->bo, t->tile_bits,
589 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
590 }
591 }
592 END_BATCH();
593 }
594
595 static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
596 {
597 r200ContextPtr r200 = R200_CONTEXT(ctx);
598 BATCH_LOCALS(&r200->radeon);
599 uint32_t dwords = atom->check(ctx, atom);
600 int i = atom->idx, j;
601 radeonTexObj *t = r200->state.texture.unit[i].texobj;
602 radeon_mipmap_level *lvl;
603 if (!(t && !t->image_override))
604 dwords = 2;
605
606 BEGIN_BATCH(dwords);
607 OUT_BATCH_TABLE(atom->cmd, 2);
608
609 if (t && !t->image_override) {
610 lvl = &t->mt->levels[0];
611 for (j = 1; j <= 5; j++) {
612 OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0));
613 OUT_BATCH_RELOC(t->mt->bo, lvl->faces[j].offset,
614 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
615 }
616 }
617 END_BATCH();
618 }
619
620 /* Initialize the context's hardware state.
621 */
622 void r200InitState( r200ContextPtr rmesa )
623 {
624 struct gl_context *ctx = &rmesa->radeon.glCtx;
625 GLuint i;
626
627 rmesa->radeon.Fallback = 0;
628
629 rmesa->radeon.hw.max_state_size = 0;
630
631 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
632 do { \
633 rmesa->hw.ATOM.cmd_size = SZ; \
634 rmesa->hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int)); \
635 rmesa->hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int)); \
636 rmesa->hw.ATOM.name = NM; \
637 rmesa->hw.ATOM.idx = IDX; \
638 if (check_##CHK != check_never) { \
639 rmesa->hw.ATOM.check = check_##CHK; \
640 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
641 } else { \
642 rmesa->hw.ATOM.check = NULL; \
643 } \
644 rmesa->hw.ATOM.dirty = GL_FALSE; \
645 } while (0)
646
647
648 /* Allocate state buffers:
649 */
650 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
651
652 rmesa->hw.ctx.emit = ctx_emit_cs;
653 rmesa->hw.ctx.check = check_always_ctx;
654 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
655 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
656 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
657 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
658 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
659 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
660 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
661 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
662 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
663 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
664 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
665 {
666 int state_size = TEX_STATE_SIZE_NEWDRM;
667 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
668 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
669 ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 );
670 ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 );
671 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
672 }
673 else {
674 ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 );
675 ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 );
676 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
677 }
678 ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 );
679 ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 );
680 ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 );
681 ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 );
682 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
683 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
684 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
685 }
686
687 ALLOC_STATE( stp, polygon_stipple, STP_STATE_SIZE, "STP/stp", 0 );
688
689 for (i = 0; i < 6; i++)
690 rmesa->hw.tex[i].emit = tex_emit_mm;
691 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
692 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
693 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
694 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
695 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
696 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
697 for (i = 0; i < 6; i++) {
698 rmesa->hw.cube[i].emit = cube_emit_cs;
699 rmesa->hw.cube[i].check = check_tex_cube_cs;
700 }
701
702 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
703 ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
704 ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
705 ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
706 ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
707
708 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
709 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
710 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
711 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
712 ALLOC_STATE( mtl[0], tcl_lighting_add6, MTL_STATE_SIZE, "MTL0/material0", 0 );
713 ALLOC_STATE( mtl[1], tcl_lighting_add6, MTL_STATE_SIZE, "MTL1/material1", 1 );
714 ALLOC_STATE( grd, tcl_or_vp_add2, GRD_STATE_SIZE, "GRD/guard-band", 0 );
715 ALLOC_STATE( fog, tcl_fog_add4, FOG_STATE_SIZE, "FOG/fog", 0 );
716 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 0 );
717 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
718 ALLOC_STATE( mat[R200_MTX_MV], tcl_add4, MAT_STATE_SIZE, "MAT/modelview", 0 );
719 ALLOC_STATE( mat[R200_MTX_IMV], tcl_add4, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
720 ALLOC_STATE( mat[R200_MTX_MVP], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 0 );
721 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat0", 0 );
722 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 );
723 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat2", 2 );
724 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat3", 3 );
725 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat4", 4 );
726 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat5", 5 );
727 ALLOC_STATE( ucp[0], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
728 ALLOC_STATE( ucp[1], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
729 ALLOC_STATE( ucp[2], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
730 ALLOC_STATE( ucp[3], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
731 ALLOC_STATE( ucp[4], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
732 ALLOC_STATE( ucp[5], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
733 ALLOC_STATE( lit[0], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-0", 0 );
734 ALLOC_STATE( lit[1], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-1", 1 );
735 ALLOC_STATE( lit[2], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-2", 2 );
736 ALLOC_STATE( lit[3], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-3", 3 );
737 ALLOC_STATE( lit[4], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-4", 4 );
738 ALLOC_STATE( lit[5], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-5", 5 );
739 ALLOC_STATE( lit[6], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-6", 6 );
740 ALLOC_STATE( lit[7], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-7", 7 );
741 ALLOC_STATE( sci, rrb, SCI_STATE_SIZE, "SCI/scissor", 0 );
742 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
743 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
744 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
745 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
746 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
747 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
748 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
749 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
750 ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 );
751
752 r200SetUpAtomList( rmesa );
753
754 /* Fill in the packet headers:
755 */
756 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
757 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
758 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
759 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
760 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
761 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
762 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
763 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
764 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
765 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
766 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X);
767 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET);
768 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL);
769 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS);
770 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE);
771 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
772 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
773 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
774 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
775 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
776 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
777 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
778 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
779 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
780 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
781 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
782 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
783 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
784 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
785 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
786 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
787 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
788 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
789 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
790 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0);
791 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0);
792 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1);
793 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1);
794 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2);
795 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2);
796 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3);
797 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3);
798 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4);
799 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4);
800 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5);
801 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5);
802 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0);
803 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1);
804 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2);
805 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3);
806 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4);
807 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5);
808 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
809 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
810 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
811 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2);
812 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0);
813 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL);
814 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0);
815 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL);
816 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL);
817 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL);
818 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL);
819 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL);
820
821 rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0);
822 rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0);
823
824 rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
825 rmesa->hw.stp.cmd[STP_DATA_0] = 0;
826 rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
827
828 rmesa->hw.mtl[0].emit = mtl_emit;
829 rmesa->hw.mtl[1].emit = mtl_emit;
830
831 rmesa->hw.vpi[0].emit = veclinear_emit;
832 rmesa->hw.vpi[1].emit = veclinear_emit;
833 rmesa->hw.vpp[0].emit = veclinear_emit;
834 rmesa->hw.vpp[1].emit = veclinear_emit;
835
836 rmesa->hw.grd.emit = scl_emit;
837 rmesa->hw.fog.emit = vec_emit;
838 rmesa->hw.glt.emit = vec_emit;
839 rmesa->hw.eye.emit = vec_emit;
840
841 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++)
842 rmesa->hw.mat[i].emit = vec_emit;
843
844 for (i = 0; i < 8; i++)
845 rmesa->hw.lit[i].emit = lit_emit;
846
847 for (i = 0; i < 6; i++)
848 rmesa->hw.ucp[i].emit = vec_emit;
849
850 rmesa->hw.ptp.emit = ptp_emit;
851
852 rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
853 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
854 rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
855 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
856 rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
857 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
858 rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
859 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
860
861 rmesa->hw.vpi[0].cmd[VPI_CMD_0] =
862 cmdveclinear( R200_PVS_PROG0, 64 );
863 rmesa->hw.vpi[1].cmd[VPI_CMD_0] =
864 cmdveclinear( R200_PVS_PROG1, 64 );
865 rmesa->hw.vpp[0].cmd[VPP_CMD_0] =
866 cmdveclinear( R200_PVS_PARAM0, 96 );
867 rmesa->hw.vpp[1].cmd[VPP_CMD_0] =
868 cmdveclinear( R200_PVS_PARAM1, 96 );
869
870 rmesa->hw.grd.cmd[GRD_CMD_0] =
871 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
872 rmesa->hw.fog.cmd[FOG_CMD_0] =
873 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
874 rmesa->hw.glt.cmd[GLT_CMD_0] =
875 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
876 rmesa->hw.eye.cmd[EYE_CMD_0] =
877 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
878
879 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
880 cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
881 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
882 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
883 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
884 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
885 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
886 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
887 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
888 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
889 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
890 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
891 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
892 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
893 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
894 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
895 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
896 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
897
898 for (i = 0 ; i < 8; i++) {
899 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
900 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
901 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
902 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
903 }
904
905 for (i = 0 ; i < 6; i++) {
906 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
907 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
908 }
909
910 rmesa->hw.ptp.cmd[PTP_CMD_0] =
911 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 );
912 rmesa->hw.ptp.cmd[PTP_CMD_1] =
913 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 );
914
915 /* Initial Harware state:
916 */
917 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
918 /* | R200_RIGHT_HAND_CUBE_OGL*/);
919
920 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
921 R200_FOG_USE_SPEC_ALPHA);
922
923 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
924
925 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
926 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
927 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
928
929 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
930 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
931 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
932 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
933 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
934 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
935 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
936
937 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
938 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
939
940 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
941 ((rmesa->radeon.radeonScreen->depthPitch &
942 R200_DEPTHPITCH_MASK) |
943 R200_DEPTH_ENDIAN_NO_SWAP);
944
945 if (rmesa->using_hyperz)
946 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
947
948 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS |
949 R200_STENCIL_TEST_ALWAYS |
950 R200_STENCIL_FAIL_KEEP |
951 R200_STENCIL_ZPASS_KEEP |
952 R200_STENCIL_ZFAIL_KEEP |
953 R200_Z_WRITE_ENABLE);
954
955 if (rmesa->using_hyperz) {
956 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
957 R200_Z_DECOMPRESSION_ENABLE;
958 /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
959 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
960 }
961
962 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
963 | R200_TEX_BLEND_0_ENABLE);
964
965 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
966 case DRI_CONF_DITHER_XERRORDIFFRESET:
967 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
968 break;
969 case DRI_CONF_DITHER_ORDERED:
970 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
971 break;
972 }
973 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
974 DRI_CONF_ROUND_ROUND )
975 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE;
976 else
977 rmesa->radeon.state.color.roundEnable = 0;
978 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
979 DRI_CONF_COLOR_REDUCTION_DITHER )
980 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
981 else
982 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
983
984 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK *
985 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality");
986 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0;
987
988 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
989 R200_BFACE_SOLID |
990 R200_FFACE_SOLID |
991 R200_FLAT_SHADE_VTX_LAST |
992 R200_DIFFUSE_SHADE_GOURAUD |
993 R200_ALPHA_SHADE_GOURAUD |
994 R200_SPECULAR_SHADE_GOURAUD |
995 R200_FOG_SHADE_GOURAUD |
996 R200_DISC_FOG_SHADE_GOURAUD |
997 R200_VTX_PIX_CENTER_OGL |
998 R200_ROUND_MODE_TRUNC |
999 R200_ROUND_PREC_8TH_PIX);
1000
1001 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
1002 R200_SCISSOR_ENABLE);
1003
1004 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
1005
1006 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
1007 ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
1008 (1 << R200_LINE_CURRENT_COUNT_SHIFT));
1009
1010 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1011
1012 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1013 ((0x00 << R200_STENCIL_REF_SHIFT) |
1014 (0xff << R200_STENCIL_MASK_SHIFT) |
1015 (0xff << R200_STENCIL_WRITEMASK_SHIFT));
1016
1017 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
1018 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1019
1020 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
1021
1022 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1023 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
1024 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
1025 R200_STIPPLE_BIG_BIT_ORDER);
1026
1027
1028 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
1029 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
1030 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
1031 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
1032 #ifdef MESA_BIG_ENDIAN
1033 R200_VC_32BIT_SWAP;
1034 #else
1035 R200_VC_NO_SWAP;
1036 #endif
1037
1038 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
1039 /* Bypass TCL */
1040 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
1041 }
1042
1043 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] =
1044 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10;
1045 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
1046 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
1047 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
1048 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
1049 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
1050 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
1051 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
1052 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
1053 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
1054 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
1055 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
1056 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
1057 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
1058
1059
1060 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1061 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1062 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1063 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1064 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1065 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1066
1067 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1068 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
1069 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1070 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */
1071 (2 << R200_TXFORMAT_WIDTH_SHIFT) |
1072 (2 << R200_TXFORMAT_HEIGHT_SHIFT));
1073 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1074 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
1075 (/* R200_TEXCOORD_PROJ | */
1076 R200_LOD_BIAS_CORRECTION); /* Small default bias */
1077 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
1078 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1079 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
1080 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
1081
1082 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1083 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
1084 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1085 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
1086 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1087 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
1088 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1089 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
1090 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1091 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
1092 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1093
1094 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
1095 (R200_TXC_ARG_A_ZERO |
1096 R200_TXC_ARG_B_ZERO |
1097 R200_TXC_ARG_C_DIFFUSE_COLOR |
1098 R200_TXC_OP_MADD);
1099
1100 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
1101 ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
1102 R200_TXC_SCALE_1X |
1103 R200_TXC_CLAMP_0_1 |
1104 R200_TXC_OUTPUT_REG_R0);
1105
1106 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
1107 (R200_TXA_ARG_A_ZERO |
1108 R200_TXA_ARG_B_ZERO |
1109 R200_TXA_ARG_C_DIFFUSE_ALPHA |
1110 R200_TXA_OP_MADD);
1111
1112 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
1113 ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
1114 R200_TXA_SCALE_1X |
1115 R200_TXA_CLAMP_0_1 |
1116 R200_TXA_OUTPUT_REG_R0);
1117 }
1118
1119 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
1120 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
1121 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
1122 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
1123 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
1124 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
1125
1126 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
1127 (R200_VAP_TCL_ENABLE |
1128 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
1129
1130 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
1131 (R200_VPORT_X_SCALE_ENA |
1132 R200_VPORT_Y_SCALE_ENA |
1133 R200_VPORT_Z_SCALE_ENA |
1134 R200_VPORT_X_OFFSET_ENA |
1135 R200_VPORT_Y_OFFSET_ENA |
1136 R200_VPORT_Z_OFFSET_ENA |
1137 /* FIXME: Turn on for tex rect only */
1138 R200_VTX_ST_DENORMALIZED |
1139 R200_VTX_W0_FMT);
1140
1141
1142 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
1143 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
1144 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
1145 ((R200_VTX_Z0 | R200_VTX_W0 |
1146 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
1147 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
1148 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
1149 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
1150
1151
1152 /* Matrix selection */
1153 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
1154 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
1155
1156 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
1157 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
1158
1159 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
1160 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
1161
1162 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
1163 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
1164 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
1165 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
1166 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
1167
1168 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
1169 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
1170 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
1171
1172
1173 /* General TCL state */
1174 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
1175 (R200_SPECULAR_LIGHTS |
1176 R200_DIFFUSE_SPECULAR_COMBINE |
1177 R200_LOCAL_LIGHT_VEC_GL |
1178 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
1179 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
1180
1181 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
1182 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
1183 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
1184 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
1185 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
1186 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
1187 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
1188 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
1189 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
1190
1191 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
1192 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
1193 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
1194 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
1195
1196 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1197 (R200_UCP_IN_CLIP_SPACE |
1198 R200_CULL_FRONT_IS_CCW);
1199
1200 /* Texgen/Texmat state */
1201 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
1202 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
1203 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
1204 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
1205 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
1206 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
1207 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
1208 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
1209 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
1210 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
1211 ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
1212 (1 << R200_TEXGEN_1_INPUT_SHIFT) |
1213 (2 << R200_TEXGEN_2_INPUT_SHIFT) |
1214 (3 << R200_TEXGEN_3_INPUT_SHIFT) |
1215 (4 << R200_TEXGEN_4_INPUT_SHIFT) |
1216 (5 << R200_TEXGEN_5_INPUT_SHIFT));
1217 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
1218
1219
1220 for (i = 0 ; i < 8; i++) {
1221 struct gl_light *l = &ctx->Light.Light[i];
1222 GLenum p = GL_LIGHT0 + i;
1223 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1224
1225 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1226 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1227 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1228 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1229 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1230 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1231 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1232 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1233 &l->ConstantAttenuation );
1234 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1235 &l->LinearAttenuation );
1236 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1237 &l->QuadraticAttenuation );
1238 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1239 }
1240
1241 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1242 ctx->Light.Model.Ambient );
1243
1244 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1245
1246 for (i = 0 ; i < 6; i++) {
1247 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1248 }
1249
1250 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1251 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1252 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1253 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1254 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1255 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1256
1257 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1258 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1259 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1260 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1261
1262 rmesa->hw.eye.cmd[EYE_X] = 0;
1263 rmesa->hw.eye.cmd[EYE_Y] = 0;
1264 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1265 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1266
1267 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] =
1268 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST;
1269
1270 /* ptp_eye is presumably used to calculate the attenuation wrt a different
1271 location? In any case, since point attenuation triggers _needeyecoords,
1272 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC
1273 isn't set */
1274 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0;
1275 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0;
1276 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */
1277 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0;
1278 /* no idea what the ptp_vport_scale values are good for, except the
1279 PTSIZE one - hopefully doesn't matter */
1280 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE;
1281 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE;
1282 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE;
1283 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE;
1284 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0;
1285 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0;
1286 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE;
1287 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0;
1288 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE;
1289 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */
1290 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0;
1291 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0;
1292
1293 r200LightingSpaceChange( ctx );
1294
1295 radeon_init_query_stateobj(&rmesa->radeon, R200_QUERYOBJ_CMDSIZE);
1296 rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0);
1297 rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_DATA_0] = 0;
1298
1299 rmesa->radeon.hw.all_dirty = GL_TRUE;
1300
1301 rcommonInitCmdBuf(&rmesa->radeon);
1302 }