src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c

   1 /*
   2  * Copyright (C) 2008 Nicolai Haehnle.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /**
  29  * @file
  30  *
  31  * Shareable transformations that transform "special" ALU instructions
  32  * into ALU instructions that are supported by hardware.
  33  *
  34  */
  35
  36 #include "radeon_program_alu.h"
  37
  38 #include "radeon_compiler.h"
  39
  40
  41 static struct rc_instruction *emit1(
  42         struct radeon_compiler * c, struct rc_instruction * after,
  43         rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
  44         struct rc_src_register SrcReg)
  45 {
  46         struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
  47
  48         fpi->U.I.Opcode = Opcode;
  49         fpi->U.I.SaturateMode = Saturate;
  50         fpi->U.I.DstReg = DstReg;
  51         fpi->U.I.SrcReg[0] = SrcReg;
  52         return fpi;
  53 }
  54
  55 static struct rc_instruction *emit2(
  56         struct radeon_compiler * c, struct rc_instruction * after,
  57         rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
  58         struct rc_src_register SrcReg0, struct rc_src_register SrcReg1)
  59 {
  60         struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
  61
  62         fpi->U.I.Opcode = Opcode;
  63         fpi->U.I.SaturateMode = Saturate;
  64         fpi->U.I.DstReg = DstReg;
  65         fpi->U.I.SrcReg[0] = SrcReg0;
  66         fpi->U.I.SrcReg[1] = SrcReg1;
  67         return fpi;
  68 }
  69
  70 static struct rc_instruction *emit3(
  71         struct radeon_compiler * c, struct rc_instruction * after,
  72         rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
  73         struct rc_src_register SrcReg0, struct rc_src_register SrcReg1,
  74         struct rc_src_register SrcReg2)
  75 {
  76         struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
  77
  78         fpi->U.I.Opcode = Opcode;
  79         fpi->U.I.SaturateMode = Saturate;
  80         fpi->U.I.DstReg = DstReg;
  81         fpi->U.I.SrcReg[0] = SrcReg0;
  82         fpi->U.I.SrcReg[1] = SrcReg1;
  83         fpi->U.I.SrcReg[2] = SrcReg2;
  84         return fpi;
  85 }
  86
  87 static struct rc_dst_register dstreg(int file, int index)
  88 {
  89         struct rc_dst_register dst;
  90         dst.File = file;
  91         dst.Index = index;
  92         dst.WriteMask = RC_MASK_XYZW;
  93         dst.RelAddr = 0;
  94         return dst;
  95 }
  96
  97 static struct rc_dst_register dstregtmpmask(int index, int mask)
  98 {
  99         struct rc_dst_register dst = {0};
 100         dst.File = RC_FILE_TEMPORARY;
 101         dst.Index = index;
 102         dst.WriteMask = mask;
 103         dst.RelAddr = 0;
 104         return dst;
 105 }
 106
 107 static const struct rc_src_register builtin_zero = {
 108         .File = RC_FILE_NONE,
 109         .Index = 0,
 110         .Swizzle = RC_SWIZZLE_0000
 111 };
 112 static const struct rc_src_register builtin_one = {
 113         .File = RC_FILE_NONE,
 114         .Index = 0,
 115         .Swizzle = RC_SWIZZLE_1111
 116 };
 117 static const struct rc_src_register srcreg_undefined = {
 118         .File = RC_FILE_NONE,
 119         .Index = 0,
 120         .Swizzle = RC_SWIZZLE_XYZW
 121 };
 122
 123 static struct rc_src_register srcreg(int file, int index)
 124 {
 125         struct rc_src_register src = srcreg_undefined;
 126         src.File = file;
 127         src.Index = index;
 128         return src;
 129 }
 130
 131 static struct rc_src_register srcregswz(int file, int index, int swz)
 132 {
 133         struct rc_src_register src = srcreg_undefined;
 134         src.File = file;
 135         src.Index = index;
 136         src.Swizzle = swz;
 137         return src;
 138 }
 139
 140 static struct rc_src_register absolute(struct rc_src_register reg)
 141 {
 142         struct rc_src_register newreg = reg;
 143         newreg.Abs = 1;
 144         newreg.Negate = RC_MASK_NONE;
 145         return newreg;
 146 }
 147
 148 static struct rc_src_register negate(struct rc_src_register reg)
 149 {
 150         struct rc_src_register newreg = reg;
 151         newreg.Negate = newreg.Negate ^ RC_MASK_XYZW;
 152         return newreg;
 153 }
 154
 155 static struct rc_src_register swizzle(struct rc_src_register reg,
 156                 rc_swizzle x, rc_swizzle y, rc_swizzle z, rc_swizzle w)
 157 {
 158         struct rc_src_register swizzled = reg;
 159         swizzled.Swizzle = combine_swizzles4(reg.Swizzle, x, y, z, w);
 160         return swizzled;
 161 }
 162
 163 static struct rc_src_register scalar(struct rc_src_register reg)
 164 {
 165         return swizzle(reg, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X);
 166 }
 167
 168 static void transform_ABS(struct radeon_compiler* c,
 169         struct rc_instruction* inst)
 170 {
 171         struct rc_src_register src = inst->U.I.SrcReg[0];
 172         src.Abs = 1;
 173         src.Negate = RC_MASK_NONE;
 174         emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode, inst->U.I.DstReg, src);
 175         rc_remove_instruction(inst);
 176 }
 177
 178 static void transform_DP3(struct radeon_compiler* c,
 179         struct rc_instruction* inst)
 180 {
 181         struct rc_src_register src0 = inst->U.I.SrcReg[0];
 182         struct rc_src_register src1 = inst->U.I.SrcReg[1];
 183         src0.Negate &= ~RC_MASK_W;
 184         src0.Swizzle &= ~(7 << (3 * 3));
 185         src0.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
 186         src1.Negate &= ~RC_MASK_W;
 187         src1.Swizzle &= ~(7 << (3 * 3));
 188         src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
 189         emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
 190         rc_remove_instruction(inst);
 191 }
 192
 193 static void transform_DPH(struct radeon_compiler* c,
 194         struct rc_instruction* inst)
 195 {
 196         struct rc_src_register src0 = inst->U.I.SrcReg[0];
 197         src0.Negate &= ~RC_MASK_W;
 198         src0.Swizzle &= ~(7 << (3 * 3));
 199         src0.Swizzle |= RC_SWIZZLE_ONE << (3 * 3);
 200         emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, inst->U.I.SrcReg[1]);
 201         rc_remove_instruction(inst);
 202 }
 203
 204 /**
 205  * [1, src0.y*src1.y, src0.z, src1.w]
 206  * So basically MUL with lotsa swizzling.
 207  */
 208 static void transform_DST(struct radeon_compiler* c,
 209         struct rc_instruction* inst)
 210 {
 211         emit2(c, inst->Prev, RC_OPCODE_MUL, inst->U.I.SaturateMode, inst->U.I.DstReg,
 212                 swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ONE),
 213                 swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_ONE, RC_SWIZZLE_W));
 214         rc_remove_instruction(inst);
 215 }
 216
 217 static void transform_FLR(struct radeon_compiler* c,
 218         struct rc_instruction* inst)
 219 {
 220         int tempreg = rc_find_free_temporary(c);
 221         emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0]);
 222         emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
 223                 inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, tempreg)));
 224         rc_remove_instruction(inst);
 225 }
 226
 227 /**
 228  * Definition of LIT (from ARB_fragment_program):
 229  *
 230  *  tmp = VectorLoad(op0);
 231  *  if (tmp.x < 0) tmp.x = 0;
 232  *  if (tmp.y < 0) tmp.y = 0;
 233  *  if (tmp.w < -(128.0-epsilon)) tmp.w = -(128.0-epsilon);
 234  *  else if (tmp.w > 128-epsilon) tmp.w = 128-epsilon;
 235  *  result.x = 1.0;
 236  *  result.y = tmp.x;
 237  *  result.z = (tmp.x > 0) ? RoughApproxPower(tmp.y, tmp.w) : 0.0;
 238  *  result.w = 1.0;
 239  *
 240  * The longest path of computation is the one leading to result.z,
 241  * consisting of 5 operations. This implementation of LIT takes
 242  * 5 slots, if the subsequent optimization passes are clever enough
 243  * to pair instructions correctly.
 244  */
 245 static void transform_LIT(struct radeon_compiler* c,
 246         struct rc_instruction* inst)
 247 {
 248         unsigned int constant;
 249         unsigned int constant_swizzle;
 250         unsigned int temp;
 251         struct rc_src_register srctemp;
 252
 253         constant = rc_constants_add_immediate_scalar(&c->Program.Constants, -127.999999, &constant_swizzle);
 254
 255         if (inst->U.I.DstReg.WriteMask != RC_MASK_XYZW || inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
 256                 struct rc_instruction * inst_mov;
 257
 258                 inst_mov = emit1(c, inst,
 259                         RC_OPCODE_MOV, 0, inst->U.I.DstReg,
 260                         srcreg(RC_FILE_TEMPORARY, rc_find_free_temporary(c)));
 261
 262                 inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
 263                 inst->U.I.DstReg.Index = inst_mov->U.I.SrcReg[0].Index;
 264                 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
 265         }
 266
 267         temp = inst->U.I.DstReg.Index;
 268         srctemp = srcreg(RC_FILE_TEMPORARY, temp);
 269
 270         /* tmp.x = max(0.0, Src.x); */
 271         /* tmp.y = max(0.0, Src.y); */
 272         /* tmp.w = clamp(Src.z, -128+eps, 128-eps); */
 273         emit2(c, inst->Prev, RC_OPCODE_MAX, 0,
 274                 dstregtmpmask(temp, RC_MASK_XYW),
 275                 inst->U.I.SrcReg[0],
 276                 swizzle(srcreg(RC_FILE_CONSTANT, constant),
 277                         RC_SWIZZLE_ZERO, RC_SWIZZLE_ZERO, RC_SWIZZLE_ZERO, constant_swizzle&3));
 278         emit2(c, inst->Prev, RC_OPCODE_MIN, 0,
 279                 dstregtmpmask(temp, RC_MASK_Z),
 280                 swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 281                 negate(srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle)));
 282
 283         /* tmp.w = Pow(tmp.y, tmp.w) */
 284         emit1(c, inst->Prev, RC_OPCODE_LG2, 0,
 285                 dstregtmpmask(temp, RC_MASK_W),
 286                 swizzle(srctemp, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y));
 287         emit2(c, inst->Prev, RC_OPCODE_MUL, 0,
 288                 dstregtmpmask(temp, RC_MASK_W),
 289                 swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 290                 swizzle(srctemp, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z));
 291         emit1(c, inst->Prev, RC_OPCODE_EX2, 0,
 292                 dstregtmpmask(temp, RC_MASK_W),
 293                 swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W));
 294
 295         /* tmp.z = (tmp.x > 0) ? tmp.w : 0.0 */
 296         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode,
 297                 dstregtmpmask(temp, RC_MASK_Z),
 298                 negate(swizzle(srctemp, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)),
 299                 swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 300                 builtin_zero);
 301
 302         /* tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0 */
 303         emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode,
 304                 dstregtmpmask(temp, RC_MASK_XYW),
 305                 swizzle(srctemp, RC_SWIZZLE_ONE, RC_SWIZZLE_X, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE));
 306
 307         rc_remove_instruction(inst);
 308 }
 309
 310 static void transform_LRP(struct radeon_compiler* c,
 311         struct rc_instruction* inst)
 312 {
 313         int tempreg = rc_find_free_temporary(c);
 314
 315         emit2(c, inst->Prev, RC_OPCODE_ADD, 0,
 316                 dstreg(RC_FILE_TEMPORARY, tempreg),
 317                 inst->U.I.SrcReg[1], negate(inst->U.I.SrcReg[2]));
 318         emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode,
 319                 inst->U.I.DstReg,
 320                 inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[2]);
 321
 322         rc_remove_instruction(inst);
 323 }
 324
 325 static void transform_POW(struct radeon_compiler* c,
 326         struct rc_instruction* inst)
 327 {
 328         int tempreg = rc_find_free_temporary(c);
 329         struct rc_dst_register tempdst = dstreg(RC_FILE_TEMPORARY, tempreg);
 330         struct rc_src_register tempsrc = srcreg(RC_FILE_TEMPORARY, tempreg);
 331         tempdst.WriteMask = RC_MASK_W;
 332         tempsrc.Swizzle = RC_SWIZZLE_WWWW;
 333
 334         emit1(c, inst->Prev, RC_OPCODE_LG2, 0, tempdst, scalar(inst->U.I.SrcReg[0]));
 335         emit2(c, inst->Prev, RC_OPCODE_MUL, 0, tempdst, tempsrc, scalar(inst->U.I.SrcReg[1]));
 336         emit1(c, inst->Prev, RC_OPCODE_EX2, inst->U.I.SaturateMode, inst->U.I.DstReg, tempsrc);
 337
 338         rc_remove_instruction(inst);
 339 }
 340
 341 static void transform_RSQ(struct radeon_compiler* c,
 342         struct rc_instruction* inst)
 343 {
 344         inst->U.I.SrcReg[0] = absolute(inst->U.I.SrcReg[0]);
 345 }
 346
 347 static void transform_SEQ(struct radeon_compiler* c,
 348         struct rc_instruction* inst)
 349 {
 350         int tempreg = rc_find_free_temporary(c);
 351
 352         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 353         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 354                 negate(absolute(srcreg(RC_FILE_TEMPORARY, tempreg))), builtin_zero, builtin_one);
 355
 356         rc_remove_instruction(inst);
 357 }
 358
 359 static void transform_SFL(struct radeon_compiler* c,
 360         struct rc_instruction* inst)
 361 {
 362         emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode, inst->U.I.DstReg, builtin_zero);
 363         rc_remove_instruction(inst);
 364 }
 365
 366 static void transform_SGE(struct radeon_compiler* c,
 367         struct rc_instruction* inst)
 368 {
 369         int tempreg = rc_find_free_temporary(c);
 370
 371         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 372         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 373                 srcreg(RC_FILE_TEMPORARY, tempreg), builtin_zero, builtin_one);
 374
 375         rc_remove_instruction(inst);
 376 }
 377
 378 static void transform_SGT(struct radeon_compiler* c,
 379         struct rc_instruction* inst)
 380 {
 381         int tempreg = rc_find_free_temporary(c);
 382
 383         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
 384         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 385                 srcreg(RC_FILE_TEMPORARY, tempreg), builtin_one, builtin_zero);
 386
 387         rc_remove_instruction(inst);
 388 }
 389
 390 static void transform_SLE(struct radeon_compiler* c,
 391         struct rc_instruction* inst)
 392 {
 393         int tempreg = rc_find_free_temporary(c);
 394
 395         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
 396         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 397                 srcreg(RC_FILE_TEMPORARY, tempreg), builtin_zero, builtin_one);
 398
 399         rc_remove_instruction(inst);
 400 }
 401
 402 static void transform_SLT(struct radeon_compiler* c,
 403         struct rc_instruction* inst)
 404 {
 405         int tempreg = rc_find_free_temporary(c);
 406
 407         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 408         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 409                 srcreg(RC_FILE_TEMPORARY, tempreg), builtin_one, builtin_zero);
 410
 411         rc_remove_instruction(inst);
 412 }
 413
 414 static void transform_SNE(struct radeon_compiler* c,
 415         struct rc_instruction* inst)
 416 {
 417         int tempreg = rc_find_free_temporary(c);
 418
 419         emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 420         emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
 421                 negate(absolute(srcreg(RC_FILE_TEMPORARY, tempreg))), builtin_one, builtin_zero);
 422
 423         rc_remove_instruction(inst);
 424 }
 425
 426 static void transform_SUB(struct radeon_compiler* c,
 427         struct rc_instruction* inst)
 428 {
 429         inst->U.I.Opcode = RC_OPCODE_ADD;
 430         inst->U.I.SrcReg[1] = negate(inst->U.I.SrcReg[1]);
 431 }
 432
 433 static void transform_SWZ(struct radeon_compiler* c,
 434         struct rc_instruction* inst)
 435 {
 436         inst->U.I.Opcode = RC_OPCODE_MOV;
 437 }
 438
 439 static void transform_XPD(struct radeon_compiler* c,
 440         struct rc_instruction* inst)
 441 {
 442         int tempreg = rc_find_free_temporary(c);
 443
 444         emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dstreg(RC_FILE_TEMPORARY, tempreg),
 445                 swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
 446                 swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W));
 447         emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode, inst->U.I.DstReg,
 448                 swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W),
 449                 swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
 450                 negate(srcreg(RC_FILE_TEMPORARY, tempreg)));
 451
 452         rc_remove_instruction(inst);
 453 }
 454
 455
 456 /**
 457  * Can be used as a transformation for @ref radeonClauseLocalTransform,
 458  * no userData necessary.
 459  *
 460  * Eliminates the following ALU instructions:
 461  *  ABS, DPH, DST, FLR, LIT, LRP, POW, SEQ, SFL, SGE, SGT, SLE, SLT, SNE, SUB, SWZ, XPD
 462  * using:
 463  *  MOV, ADD, MUL, MAD, FRC, DP3, LG2, EX2, CMP
 464  *
 465  * Transforms RSQ to Radeon's native RSQ by explicitly setting
 466  * absolute value.
 467  *
 468  * @note should be applicable to R300 and R500 fragment programs.
 469  */
 470 int radeonTransformALU(
 471         struct radeon_compiler * c,
 472         struct rc_instruction* inst,
 473         void* unused)
 474 {
 475         switch(inst->U.I.Opcode) {
 476         case RC_OPCODE_ABS: transform_ABS(c, inst); return 1;
 477         case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
 478         case RC_OPCODE_DST: transform_DST(c, inst); return 1;
 479         case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
 480         case RC_OPCODE_LIT: transform_LIT(c, inst); return 1;
 481         case RC_OPCODE_LRP: transform_LRP(c, inst); return 1;
 482         case RC_OPCODE_POW: transform_POW(c, inst); return 1;
 483         case RC_OPCODE_RSQ: transform_RSQ(c, inst); return 1;
 484         case RC_OPCODE_SEQ: transform_SEQ(c, inst); return 1;
 485         case RC_OPCODE_SFL: transform_SFL(c, inst); return 1;
 486         case RC_OPCODE_SGE: transform_SGE(c, inst); return 1;
 487         case RC_OPCODE_SGT: transform_SGT(c, inst); return 1;
 488         case RC_OPCODE_SLE: transform_SLE(c, inst); return 1;
 489         case RC_OPCODE_SLT: transform_SLT(c, inst); return 1;
 490         case RC_OPCODE_SNE: transform_SNE(c, inst); return 1;
 491         case RC_OPCODE_SUB: transform_SUB(c, inst); return 1;
 492         case RC_OPCODE_SWZ: transform_SWZ(c, inst); return 1;
 493         case RC_OPCODE_XPD: transform_XPD(c, inst); return 1;
 494         default:
 495                 return 0;
 496         }
 497 }
 498
 499
 500 static void transform_r300_vertex_ABS(struct radeon_compiler* c,
 501         struct rc_instruction* inst)
 502 {
 503         /* Note: r500 can take absolute values, but r300 cannot. */
 504         inst->U.I.Opcode = RC_OPCODE_MAX;
 505         inst->U.I.SrcReg[1] = inst->U.I.SrcReg[0];
 506         inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
 507 }
 508
 509 static void transform_r300_vertex_CMP(struct radeon_compiler* c,
 510         struct rc_instruction* inst)
 511 {
 512         /* There is no decent CMP available, so let's rig one up.
 513          * CMP is defined as dst = src0 < 0.0 ? src1 : src2
 514          * The following sequence consumes two temps and three extra slots,
 515          * but should be equivalent:
 516          *
 517          * SLT tmp0, src0, 0.0
 518          * SGE tmp1, src0, 0.0
 519          * MUL tmp0, tmp0, src1
 520          * MAD dst, src2, tmp1, tmp0
 521          *
 522          * Yes, I know, I'm a mad scientist. ~ C. */
 523         int tempreg0 = rc_find_free_temporary(c);
 524         int tempreg1 = rc_find_free_temporary(c);
 525
 526         /* SLT tmp0, src0, 0.0 */
 527         emit2(c, inst->Prev, RC_OPCODE_SLT, 0,
 528                 dstreg(RC_FILE_TEMPORARY, tempreg0),
 529                 inst->U.I.SrcReg[0], builtin_zero);
 530
 531         /* SGE tmp1, src0, 0.0 */
 532         emit2(c, inst->Prev, RC_OPCODE_SGE, 0,
 533                 dstreg(RC_FILE_TEMPORARY, tempreg1),
 534                 inst->U.I.SrcReg[0], builtin_zero);
 535
 536         /* MUL tmp0, tmp0, src1 */
 537         emit2(c, inst->Prev, RC_OPCODE_MUL, 0,
 538                 dstreg(RC_FILE_TEMPORARY, tempreg0),
 539                 srcreg(RC_FILE_TEMPORARY, tempreg0), inst->U.I.SrcReg[1]);
 540
 541         /* MAD dst, src2, tmp1, tmp0 */
 542         emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode,
 543                 inst->U.I.DstReg,
 544                 inst->U.I.SrcReg[2], srcreg(RC_FILE_TEMPORARY, tempreg1), srcreg(RC_FILE_TEMPORARY, tempreg0));
 545
 546         rc_remove_instruction(inst);
 547 }
 548
 549 /**
 550  * For use with radeonLocalTransform, this transforms non-native ALU
 551  * instructions of the r300 up to r500 vertex engine.
 552  */
 553 int r300_transform_vertex_alu(
 554         struct radeon_compiler * c,
 555         struct rc_instruction* inst,
 556         void* unused)
 557 {
 558         switch(inst->U.I.Opcode) {
 559         case RC_OPCODE_ABS: transform_r300_vertex_ABS(c, inst); return 1;
 560         case RC_OPCODE_CMP: transform_r300_vertex_CMP(c, inst); return 1;
 561         case RC_OPCODE_DP3: transform_DP3(c, inst); return 1;
 562         case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
 563         case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
 564         case RC_OPCODE_LRP: transform_LRP(c, inst); return 1;
 565         case RC_OPCODE_SUB: transform_SUB(c, inst); return 1;
 566         case RC_OPCODE_SWZ: transform_SWZ(c, inst); return 1;
 567         case RC_OPCODE_XPD: transform_XPD(c, inst); return 1;
 568         default:
 569                 return 0;
 570         }
 571 }
 572
 573 static void sincos_constants(struct radeon_compiler* c, unsigned int *constants)
 574 {
 575         static const float SinCosConsts[2][4] = {
 576                 {
 577                         1.273239545,            /* 4/PI */
 578                         -0.405284735,           /* -4/(PI*PI) */
 579                         3.141592654,            /* PI */
 580                         0.2225                  /* weight */
 581                 },
 582                 {
 583                         0.75,
 584                         0.5,
 585                         0.159154943,            /* 1/(2*PI) */
 586                         6.283185307             /* 2*PI */
 587                 }
 588         };
 589         int i;
 590
 591         for(i = 0; i < 2; ++i)
 592                 constants[i] = rc_constants_add_immediate_vec4(&c->Program.Constants, SinCosConsts[i]);
 593 }
 594
 595 /**
 596  * Approximate sin(x), where x is clamped to (-pi/2, pi/2).
 597  *
 598  * MUL tmp.xy, src, { 4/PI, -4/(PI^2) }
 599  * MAD tmp.x, tmp.y, |src|, tmp.x
 600  * MAD tmp.y, tmp.x, |tmp.x|, -tmp.x
 601  * MAD dest, tmp.y, weight, tmp.x
 602  */
 603 static void sin_approx(
 604         struct radeon_compiler* c, struct rc_instruction * inst,
 605         struct rc_dst_register dst, struct rc_src_register src, const unsigned int* constants)
 606 {
 607         unsigned int tempreg = rc_find_free_temporary(c);
 608
 609         emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dstregtmpmask(tempreg, RC_MASK_XY),
 610                 swizzle(src, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 611                 srcreg(RC_FILE_CONSTANT, constants[0]));
 612         emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_X),
 613                 swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y),
 614                 absolute(swizzle(src, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)),
 615                 swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X));
 616         emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_Y),
 617                 swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 618                 absolute(swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)),
 619                 negate(swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)));
 620         emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dst,
 621                 swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y),
 622                 swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 623                 swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X));
 624 }
 625
 626 /**
 627  * Translate the trigonometric functions COS, SIN, and SCS
 628  * using only the basic instructions
 629  *  MOV, ADD, MUL, MAD, FRC
 630  */
 631 int radeonTransformTrigSimple(struct radeon_compiler* c,
 632         struct rc_instruction* inst,
 633         void* unused)
 634 {
 635         if (inst->U.I.Opcode != RC_OPCODE_COS &&
 636             inst->U.I.Opcode != RC_OPCODE_SIN &&
 637             inst->U.I.Opcode != RC_OPCODE_SCS)
 638                 return 0;
 639
 640         unsigned int constants[2];
 641         unsigned int tempreg = rc_find_free_temporary(c);
 642
 643         sincos_constants(c, constants);
 644
 645         if (inst->U.I.Opcode == RC_OPCODE_COS) {
 646                 /* MAD tmp.x, src, 1/(2*PI), 0.75 */
 647                 /* FRC tmp.x, tmp.x */
 648                 /* MAD tmp.z, tmp.x, 2*PI, -PI */
 649                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W),
 650                         swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 651                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z),
 652                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X));
 653                 emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(tempreg, RC_MASK_W),
 654                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W));
 655                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W),
 656                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 657                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 658                         negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
 659
 660                 sin_approx(c, inst, inst->U.I.DstReg,
 661                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 662                         constants);
 663         } else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
 664                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W),
 665                         swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 666                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z),
 667                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y));
 668                 emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(tempreg, RC_MASK_W),
 669                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W));
 670                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W),
 671                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 672                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 673                         negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
 674
 675                 sin_approx(c, inst, inst->U.I.DstReg,
 676                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 677                         constants);
 678         } else {
 679                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_XY),
 680                         swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 681                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z),
 682                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_W));
 683                 emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(tempreg, RC_MASK_XY),
 684                         srcreg(RC_FILE_TEMPORARY, tempreg));
 685                 emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_XY),
 686                         srcreg(RC_FILE_TEMPORARY, tempreg),
 687                         swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
 688                         negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
 689
 690                 struct rc_dst_register dst = inst->U.I.DstReg;
 691
 692                 dst.WriteMask = inst->U.I.DstReg.WriteMask & RC_MASK_X;
 693                 sin_approx(c, inst, dst,
 694                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 695                         constants);
 696
 697                 dst.WriteMask = inst->U.I.DstReg.WriteMask & RC_MASK_Y;
 698                 sin_approx(c, inst, dst,
 699                         swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y),
 700                         constants);
 701         }
 702
 703         rc_remove_instruction(inst);
 704
 705         return 1;
 706 }
 707
 708
 709 /**
 710  * Transform the trigonometric functions COS, SIN, and SCS
 711  * to include pre-scaling by 1/(2*PI) and taking the fractional
 712  * part, so that the input to COS and SIN is always in the range [0,1).
 713  * SCS is replaced by one COS and one SIN instruction.
 714  *
 715  * @warning This transformation implicitly changes the semantics of SIN and COS!
 716  */
 717 int radeonTransformTrigScale(struct radeon_compiler* c,
 718         struct rc_instruction* inst,
 719         void* unused)
 720 {
 721         if (inst->U.I.Opcode != RC_OPCODE_COS &&
 722             inst->U.I.Opcode != RC_OPCODE_SIN &&
 723             inst->U.I.Opcode != RC_OPCODE_SCS)
 724                 return 0;
 725
 726         static const float RCP_2PI = 0.15915494309189535;
 727         unsigned int temp;
 728         unsigned int constant;
 729         unsigned int constant_swizzle;
 730
 731         temp = rc_find_free_temporary(c);
 732         constant = rc_constants_add_immediate_scalar(&c->Program.Constants, RCP_2PI, &constant_swizzle);
 733
 734         emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dstregtmpmask(temp, RC_MASK_W),
 735                 swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
 736                 srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle));
 737         emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(temp, RC_MASK_W),
 738                 srcreg(RC_FILE_TEMPORARY, temp));
 739
 740         if (inst->U.I.Opcode == RC_OPCODE_COS) {
 741                 emit1(c, inst->Prev, RC_OPCODE_COS, inst->U.I.SaturateMode, inst->U.I.DstReg,
 742                         srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
 743         } else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
 744                 emit1(c, inst->Prev, RC_OPCODE_SIN, inst->U.I.SaturateMode,
 745                         inst->U.I.DstReg, srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
 746         } else if (inst->U.I.Opcode == RC_OPCODE_SCS) {
 747                 struct rc_dst_register moddst = inst->U.I.DstReg;
 748
 749                 if (inst->U.I.DstReg.WriteMask & RC_MASK_X) {
 750                         moddst.WriteMask = RC_MASK_X;
 751                         emit1(c, inst->Prev, RC_OPCODE_COS, inst->U.I.SaturateMode, moddst,
 752                                 srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
 753                 }
 754                 if (inst->U.I.DstReg.WriteMask & RC_MASK_Y) {
 755                         moddst.WriteMask = RC_MASK_Y;
 756                         emit1(c, inst->Prev, RC_OPCODE_SIN, inst->U.I.SaturateMode, moddst,
 757                                 srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
 758                 }
 759         }
 760
 761         rc_remove_instruction(inst);
 762
 763         return 1;
 764 }
 765
 766 /**
 767  * Rewrite DDX/DDY instructions to properly work with r5xx shaders.
 768  * The r5xx MDH/MDV instruction provides per-quad partial derivatives.
 769  * It takes the form A*B+C. A and C are set by setting src0. B should be -1.
 770  *
 771  * @warning This explicitly changes the form of DDX and DDY!
 772  */
 773
 774 int radeonTransformDeriv(struct radeon_compiler* c,
 775         struct rc_instruction* inst,
 776         void* unused)
 777 {
 778         if (inst->U.I.Opcode != RC_OPCODE_DDX && inst->U.I.Opcode != RC_OPCODE_DDY)
 779                 return 0;
 780
 781         inst->U.I.SrcReg[1].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_ONE, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE);
 782         inst->U.I.SrcReg[1].Negate = RC_MASK_XYZW;
 783
 784         return 1;
 785 }