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Merge branch 'mesa_7_7_branch'
[mesa.git] / src / mesa / drivers / dri / r300 / r300_blit.c
1 /*
2 * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 #include "radeon_common.h"
29 #include "r300_context.h"
30
31 #include "r300_blit.h"
32 #include "r300_cmdbuf.h"
33 #include "r300_emit.h"
34 #include "r300_tex.h"
35 #include "compiler/radeon_compiler.h"
36 #include "compiler/radeon_opcodes.h"
37
38 static void vp_ins_outs(struct r300_vertex_program_compiler *c)
39 {
40 c->code->inputs[VERT_ATTRIB_POS] = 0;
41 c->code->inputs[VERT_ATTRIB_TEX0] = 1;
42 c->code->outputs[VERT_RESULT_HPOS] = 0;
43 c->code->outputs[VERT_RESULT_TEX0] = 1;
44 }
45
46 static void fp_allocate_hw_inputs(
47 struct r300_fragment_program_compiler * c,
48 void (*allocate)(void * data, unsigned input, unsigned hwreg),
49 void * mydata)
50 {
51 allocate(mydata, FRAG_ATTRIB_TEX0, 0);
52 }
53
54 static void create_vertex_program(struct r300_context *r300)
55 {
56 struct r300_vertex_program_compiler compiler;
57 struct rc_instruction *inst;
58
59 rc_init(&compiler.Base);
60
61 inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
62 inst->U.I.Opcode = RC_OPCODE_MOV;
63 inst->U.I.DstReg.File = RC_FILE_OUTPUT;
64 inst->U.I.DstReg.Index = VERT_RESULT_HPOS;
65 inst->U.I.DstReg.RelAddr = 0;
66 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
67 inst->U.I.SrcReg[0].Abs = 0;
68 inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
69 inst->U.I.SrcReg[0].Index = VERT_ATTRIB_POS;
70 inst->U.I.SrcReg[0].Negate = 0;
71 inst->U.I.SrcReg[0].RelAddr = 0;
72 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
73
74 inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
75 inst->U.I.Opcode = RC_OPCODE_MOV;
76 inst->U.I.DstReg.File = RC_FILE_OUTPUT;
77 inst->U.I.DstReg.Index = VERT_RESULT_TEX0;
78 inst->U.I.DstReg.RelAddr = 0;
79 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
80 inst->U.I.SrcReg[0].Abs = 0;
81 inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
82 inst->U.I.SrcReg[0].Index = VERT_ATTRIB_TEX0;
83 inst->U.I.SrcReg[0].Negate = 0;
84 inst->U.I.SrcReg[0].RelAddr = 0;
85 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
86
87 compiler.Base.Program.InputsRead = (1 << VERT_ATTRIB_POS) | (1 << VERT_ATTRIB_TEX0);
88 compiler.RequiredOutputs = compiler.Base.Program.OutputsWritten = (1 << VERT_RESULT_HPOS) | (1 << VERT_RESULT_TEX0);
89 compiler.SetHwInputOutput = vp_ins_outs;
90 compiler.code = &r300->blit.vp_code;
91
92 r3xx_compile_vertex_program(&compiler);
93 }
94
95 static void create_fragment_program(struct r300_context *r300)
96 {
97 struct r300_fragment_program_compiler compiler;
98 struct rc_instruction *inst;
99
100 rc_init(&compiler.Base);
101
102 inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
103 inst->U.I.Opcode = RC_OPCODE_TEX;
104 inst->U.I.TexSrcTarget = RC_TEXTURE_2D;
105 inst->U.I.TexSrcUnit = 0;
106 inst->U.I.DstReg.File = RC_FILE_OUTPUT;
107 inst->U.I.DstReg.Index = FRAG_RESULT_COLOR;
108 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
109 inst->U.I.SrcReg[0].Abs = 0;
110 inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
111 inst->U.I.SrcReg[0].Index = FRAG_ATTRIB_TEX0;
112 inst->U.I.SrcReg[0].Negate = 0;
113 inst->U.I.SrcReg[0].RelAddr = 0;
114 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
115
116 compiler.Base.Program.InputsRead = (1 << FRAG_ATTRIB_TEX0);
117 compiler.OutputColor = FRAG_RESULT_COLOR;
118 compiler.OutputDepth = FRAG_RESULT_DEPTH;
119 compiler.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515);
120 compiler.code = &r300->blit.fp_code;
121 compiler.AllocateHwInputs = fp_allocate_hw_inputs;
122
123 r3xx_compile_fragment_program(&compiler);
124 }
125
126 void r300_blit_init(struct r300_context *r300)
127 {
128 create_vertex_program(r300);
129 create_fragment_program(r300);
130 }
131
132 static void r300_emit_tx_setup(struct r300_context *r300,
133 gl_format mesa_format,
134 struct radeon_bo *bo,
135 intptr_t offset,
136 unsigned width,
137 unsigned height,
138 unsigned pitch)
139 {
140 BATCH_LOCALS(&r300->radeon);
141
142 assert(width <= 2048);
143 assert(height <= 2048);
144 assert(r300TranslateTexFormat(mesa_format) >= 0);
145 assert(offset % 32 == 0);
146
147 BEGIN_BATCH(17);
148 OUT_BATCH_REGVAL(R300_TX_FILTER0_0,
149 (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT) |
150 (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT) |
151 (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT) |
152 R300_TX_MIN_FILTER_MIP_NONE |
153 R300_TX_MIN_FILTER_NEAREST |
154 R300_TX_MAG_FILTER_NEAREST |
155 (0 << 28));
156 OUT_BATCH_REGVAL(R300_TX_FILTER1_0, 0);
157 OUT_BATCH_REGVAL(R300_TX_SIZE_0,
158 ((width-1) << R300_TX_WIDTHMASK_SHIFT) |
159 ((height-1) << R300_TX_HEIGHTMASK_SHIFT) |
160 (0 << R300_TX_DEPTHMASK_SHIFT) |
161 (0 << R300_TX_MAX_MIP_LEVEL_SHIFT) |
162 R300_TX_SIZE_TXPITCH_EN);
163
164 OUT_BATCH_REGVAL(R300_TX_FORMAT_0, r300TranslateTexFormat(mesa_format));
165 OUT_BATCH_REGVAL(R300_TX_FORMAT2_0, pitch - 1);
166 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0, 1);
167 OUT_BATCH_RELOC(0, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
168
169 OUT_BATCH_REGSEQ(R300_TX_INVALTAGS, 2);
170 OUT_BATCH(0);
171 OUT_BATCH(1);
172
173 END_BATCH();
174 }
175
176 #define EASY_US_FORMAT(FMT, C0, C1, C2, C3, SIGN) \
177 (FMT | R500_C0_SEL_##C0 | R500_C1_SEL_##C1 | \
178 R500_C2_SEL_##C2 | R500_C3_SEL_##C3 | R500_OUT_SIGN(SIGN))
179
180 static uint32_t mesa_format_to_us_format(gl_format mesa_format)
181 {
182 switch(mesa_format)
183 {
184 case MESA_FORMAT_RGBA8888: // x
185 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0);
186 case MESA_FORMAT_RGB565: // x
187 case MESA_FORMAT_ARGB1555: // x
188 case MESA_FORMAT_RGBA8888_REV: // x
189 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0);
190 case MESA_FORMAT_ARGB8888: // x
191 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, B, G, R, A, 0);
192 case MESA_FORMAT_ARGB8888_REV:
193 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0);
194 case MESA_FORMAT_XRGB8888:
195 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0);
196
197 case MESA_FORMAT_RGB332:
198 return EASY_US_FORMAT(R500_OUT_FMT_C_3_3_2, A, R, G, B, 0);
199
200 case MESA_FORMAT_RGBA_FLOAT32:
201 return EASY_US_FORMAT(R500_OUT_FMT_C4_32_FP, R, G, B, A, 0);
202 case MESA_FORMAT_RGBA_FLOAT16:
203 return EASY_US_FORMAT(R500_OUT_FMT_C4_16_FP, R, G, B, A, 0);
204 case MESA_FORMAT_ALPHA_FLOAT32:
205 return EASY_US_FORMAT(R500_OUT_FMT_C_32_FP, A, A, A, A, 0);
206 case MESA_FORMAT_ALPHA_FLOAT16:
207 return EASY_US_FORMAT(R500_OUT_FMT_C_16_FP, A, A, A, A, 0);
208
209 case MESA_FORMAT_SIGNED_RGBA8888:
210 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0xf);
211 case MESA_FORMAT_SIGNED_RGBA8888_REV:
212 return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0xf);
213 case MESA_FORMAT_SIGNED_RGBA_16:
214 return EASY_US_FORMAT(R500_OUT_FMT_C4_16, R, G, B, A, 0xf);
215
216 default:
217 fprintf(stderr, "Unsupported format %s for US output\n", _mesa_get_format_name(mesa_format));
218 assert(0);
219 return 0;
220 }
221 }
222 #undef EASY_US_FORMAT
223
224 static void r500_emit_fp_setup(struct r300_context *r300,
225 struct r500_fragment_program_code *fp,
226 gl_format dst_format)
227 {
228 r500_emit_fp(r300, (uint32_t *)fp->inst, (fp->inst_end + 1) * 6, 0, 0, 0);
229 BATCH_LOCALS(&r300->radeon);
230
231 BEGIN_BATCH(10);
232 OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
233 OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(fp->inst_end));
234 OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(fp->inst_end));
235 OUT_BATCH(0);
236 OUT_BATCH_REGVAL(R500_US_CONFIG, 0);
237 OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
238 OUT_BATCH_REGVAL(R500_US_PIXSIZE, fp->max_temp_idx);
239 END_BATCH();
240 }
241
242 static void r500_emit_rs_setup(struct r300_context *r300)
243 {
244 BATCH_LOCALS(&r300->radeon);
245
246 BEGIN_BATCH(7);
247 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
248 OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
249 OUT_BATCH(0);
250 OUT_BATCH_REGVAL(R500_RS_INST_0,
251 (0 << R500_RS_INST_TEX_ID_SHIFT) |
252 (0 << R500_RS_INST_TEX_ADDR_SHIFT) |
253 R500_RS_INST_TEX_CN_WRITE |
254 R500_RS_INST_COL_CN_NO_WRITE);
255 OUT_BATCH_REGVAL(R500_RS_IP_0,
256 (0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
257 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
258 (2 << R500_RS_IP_TEX_PTR_R_SHIFT) |
259 (3 << R500_RS_IP_TEX_PTR_Q_SHIFT));
260 END_BATCH();
261 }
262
263 static void r300_emit_fp_setup(struct r300_context *r300,
264 struct r300_fragment_program_code *code,
265 gl_format dst_format)
266 {
267 unsigned i;
268 BATCH_LOCALS(&r300->radeon);
269
270 BEGIN_BATCH((code->alu.length + 1) * 4 + code->tex.length + 1 + 11);
271
272 OUT_BATCH_REGSEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
273 for (i = 0; i < code->alu.length; i++) {
274 OUT_BATCH(code->alu.inst[i].rgb_inst);
275 }
276 OUT_BATCH_REGSEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
277 for (i = 0; i < code->alu.length; i++) {
278 OUT_BATCH(code->alu.inst[i].rgb_addr);
279 }
280 OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
281 for (i = 0; i < code->alu.length; i++) {
282 OUT_BATCH(code->alu.inst[i].alpha_inst);
283 }
284 OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
285 for (i = 0; i < code->alu.length; i++) {
286 OUT_BATCH(code->alu.inst[i].alpha_addr);
287 }
288
289 OUT_BATCH_REGSEQ(R300_US_TEX_INST_0, code->tex.length);
290 OUT_BATCH_TABLE(code->tex.inst, code->tex.length);
291
292 OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
293 OUT_BATCH(R300_PFS_CNTL_FIRST_NODE_HAS_TEX);
294 OUT_BATCH(code->pixsize);
295 OUT_BATCH(code->code_offset);
296 OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
297 OUT_BATCH_TABLE(code->code_addr, 4);
298 OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
299 END_BATCH();
300 }
301
302 static void r300_emit_rs_setup(struct r300_context *r300)
303 {
304 BATCH_LOCALS(&r300->radeon);
305
306 BEGIN_BATCH(7);
307 OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
308 OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
309 OUT_BATCH(0);
310 OUT_BATCH_REGVAL(R300_RS_INST_0,
311 R300_RS_INST_TEX_ID(0) |
312 R300_RS_INST_TEX_ADDR(0) |
313 R300_RS_INST_TEX_CN_WRITE);
314 OUT_BATCH_REGVAL(R300_RS_IP_0,
315 R300_RS_TEX_PTR(0) |
316 R300_RS_SEL_S(R300_RS_SEL_C0) |
317 R300_RS_SEL_T(R300_RS_SEL_C1) |
318 R300_RS_SEL_R(R300_RS_SEL_K0) |
319 R300_RS_SEL_Q(R300_RS_SEL_K1));
320 END_BATCH();
321 }
322
323 static void emit_pvs_setup(struct r300_context *r300,
324 uint32_t *vp_code,
325 unsigned vp_len)
326 {
327 BATCH_LOCALS(&r300->radeon);
328
329 r300_emit_vpu(r300, vp_code, vp_len * 4, R300_PVS_CODE_START);
330
331 BEGIN_BATCH(4);
332 OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
333 OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
334 ((vp_len - 1) << R300_PVS_XYZW_VALID_INST_SHIFT) |
335 ((vp_len - 1)<< R300_PVS_LAST_INST_SHIFT));
336 OUT_BATCH(0);
337 OUT_BATCH((vp_len - 1) << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
338 END_BATCH();
339 }
340
341 static void emit_vap_setup(struct r300_context *r300)
342 {
343 BATCH_LOCALS(&r300->radeon);
344
345 BEGIN_BATCH(12);
346 OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
347 OUT_BATCH(R300_VTX_XY_FMT | R300_VTX_Z_FMT);
348 OUT_BATCH(4);
349
350 OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
351 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_0,
352 ((R300_DATA_TYPE_FLOAT_2 | (0 << R300_DST_VEC_LOC_SHIFT)) << 0) |
353 (((1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_2 | R300_LAST_VEC) << 16));
354 OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
355 ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
356 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
357 (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) |
358 (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) |
359 (0xf << R300_WRITE_ENA_SHIFT) ) << 0) |
360 (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
361 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
362 (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) |
363 (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) |
364 (0xf << R300_WRITE_ENA_SHIFT) ) << 16) ) );
365 OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
366 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT);
367 OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS);
368 END_BATCH();
369 }
370
371 static GLboolean validate_buffers(struct r300_context *r300,
372 struct radeon_bo *src_bo,
373 struct radeon_bo *dst_bo)
374 {
375 int ret;
376 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
377 src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
378
379 radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
380 dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
381
382 ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
383 first_elem(&r300->radeon.dma.reserved)->bo,
384 RADEON_GEM_DOMAIN_GTT, 0);
385 if (ret)
386 return GL_FALSE;
387
388 return GL_TRUE;
389 }
390
391 /**
392 * Calculate texcoords for given image region.
393 * Output values are [minx, maxx, miny, maxy]
394 */
395 static void calc_tex_coords(float img_width, float img_height,
396 float x, float y,
397 float reg_width, float reg_height,
398 unsigned flip_y, float *buf)
399 {
400 buf[0] = x / img_width;
401 buf[1] = buf[0] + reg_width / img_width;
402 buf[2] = y / img_height;
403 buf[3] = buf[2] + reg_height / img_height;
404 if (flip_y)
405 {
406 buf[2] = 1.0 - buf[2];
407 buf[3] = 1.0 - buf[3];
408 }
409 }
410
411 static void emit_draw_packet(struct r300_context *r300,
412 unsigned src_width, unsigned src_height,
413 unsigned src_x_offset, unsigned src_y_offset,
414 unsigned dst_x_offset, unsigned dst_y_offset,
415 unsigned reg_width, unsigned reg_height,
416 unsigned flip_y)
417 {
418 float texcoords[4];
419
420 calc_tex_coords(src_width, src_height,
421 src_x_offset, src_y_offset,
422 reg_width, reg_height,
423 flip_y, texcoords);
424
425 float verts[] = { dst_x_offset, dst_y_offset,
426 texcoords[0], texcoords[2],
427 dst_x_offset, dst_y_offset + reg_height,
428 texcoords[0], texcoords[3],
429 dst_x_offset + reg_width, dst_y_offset + reg_height,
430 texcoords[1], texcoords[3],
431 dst_x_offset + reg_width, dst_y_offset,
432 texcoords[1], texcoords[2] };
433
434 BATCH_LOCALS(&r300->radeon);
435
436 BEGIN_BATCH(19);
437 OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_IMMD_2, 16);
438 OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED |
439 (4 << 16) | R300_VAP_VF_CNTL__PRIM_QUADS);
440 OUT_BATCH_TABLE(verts, 16);
441 END_BATCH();
442 }
443
444 static void other_stuff(struct r300_context *r300)
445 {
446 BATCH_LOCALS(&r300->radeon);
447
448 BEGIN_BATCH(15);
449 OUT_BATCH_REGVAL(R300_GA_POLY_MODE,
450 R300_GA_POLY_MODE_FRONT_PTYPE_TRI | R300_GA_POLY_MODE_BACK_PTYPE_TRI);
451 OUT_BATCH_REGVAL(R300_SU_CULL_MODE, R300_FRONT_FACE_CCW);
452 OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
453 OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
454 OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
455 OUT_BATCH(0x0);
456 OUT_BATCH(0x0);
457 OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
458 OUT_BATCH_REGVAL(R300_ZB_CNTL, 0);
459 END_BATCH();
460 }
461
462 static void emit_cb_setup(struct r300_context *r300,
463 struct radeon_bo *bo,
464 intptr_t offset,
465 gl_format mesa_format,
466 unsigned pitch,
467 unsigned width,
468 unsigned height)
469 {
470 BATCH_LOCALS(&r300->radeon);
471
472 unsigned x1, y1, x2, y2;
473 x1 = 0;
474 y1 = 0;
475 x2 = width - 1;
476 y2 = height - 1;
477
478 if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
479 x1 += R300_SCISSORS_OFFSET;
480 y1 += R300_SCISSORS_OFFSET;
481 x2 += R300_SCISSORS_OFFSET;
482 y2 += R300_SCISSORS_OFFSET;
483 }
484
485 r300_emit_cb_setup(r300, bo, offset, mesa_format,
486 _mesa_get_format_bytes(mesa_format),
487 _mesa_format_row_stride(mesa_format, pitch));
488
489 BEGIN_BATCH_NO_AUTOSTATE(5);
490 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
491 OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
492 OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
493 OUT_BATCH_REGVAL(R300_RB3D_CCTL, 0);
494 END_BATCH();
495 }
496
497 static unsigned is_blit_supported(gl_format dst_format)
498 {
499 switch (dst_format) {
500 case MESA_FORMAT_RGB565:
501 case MESA_FORMAT_ARGB1555:
502 case MESA_FORMAT_RGBA8888:
503 case MESA_FORMAT_RGBA8888_REV:
504 case MESA_FORMAT_ARGB8888:
505 case MESA_FORMAT_ARGB8888_REV:
506 case MESA_FORMAT_XRGB8888:
507 break;
508 default:
509 return 0;
510 }
511
512 if (_mesa_get_format_bits(dst_format, GL_DEPTH_BITS) > 0)
513 return 0;
514
515 return 1;
516 }
517
518 /**
519 * Copy a region of [@a width x @a height] pixels from source buffer
520 * to destination buffer.
521 * @param[in] r300 r300 context
522 * @param[in] src_bo source radeon buffer object
523 * @param[in] src_offset offset of the source image in the @a src_bo
524 * @param[in] src_mesaformat source image format
525 * @param[in] src_pitch aligned source image width
526 * @param[in] src_width source image width
527 * @param[in] src_height source image height
528 * @param[in] src_x_offset x offset in the source image
529 * @param[in] src_y_offset y offset in the source image
530 * @param[in] dst_bo destination radeon buffer object
531 * @param[in] dst_offset offset of the destination image in the @a dst_bo
532 * @param[in] dst_mesaformat destination image format
533 * @param[in] dst_pitch aligned destination image width
534 * @param[in] dst_width destination image width
535 * @param[in] dst_height destination image height
536 * @param[in] dst_x_offset x offset in the destination image
537 * @param[in] dst_y_offset y offset in the destination image
538 * @param[in] width region width
539 * @param[in] height region height
540 * @param[in] flip_y set if y coords of the source image need to be flipped
541 */
542 unsigned r300_blit(GLcontext *ctx,
543 struct radeon_bo *src_bo,
544 intptr_t src_offset,
545 gl_format src_mesaformat,
546 unsigned src_pitch,
547 unsigned src_width,
548 unsigned src_height,
549 unsigned src_x_offset,
550 unsigned src_y_offset,
551 struct radeon_bo *dst_bo,
552 intptr_t dst_offset,
553 gl_format dst_mesaformat,
554 unsigned dst_pitch,
555 unsigned dst_width,
556 unsigned dst_height,
557 unsigned dst_x_offset,
558 unsigned dst_y_offset,
559 unsigned reg_width,
560 unsigned reg_height,
561 unsigned flip_y)
562 {
563 r300ContextPtr r300 = R300_CONTEXT(ctx);
564
565 if (!is_blit_supported(dst_mesaformat))
566 return 0;
567
568 /* Make sure that colorbuffer has even width - hw limitation */
569 if (dst_pitch % 2 > 0)
570 ++dst_pitch;
571
572 /* Rendering to small buffer doesn't work.
573 * Looks like a hw limitation.
574 */
575 if (dst_pitch < 32)
576 return 0;
577
578 /* Need to clamp the region size to make sure
579 * we don't read outside of the source buffer
580 * or write outside of the destination buffer.
581 */
582 if (reg_width + src_x_offset > src_width)
583 reg_width = src_width - src_x_offset;
584 if (reg_height + src_y_offset > src_height)
585 reg_height = src_height - src_y_offset;
586 if (reg_width + dst_x_offset > dst_width)
587 reg_width = dst_width - dst_x_offset;
588 if (reg_height + dst_y_offset > dst_height)
589 reg_height = dst_height - dst_y_offset;
590
591 if (src_bo == dst_bo) {
592 return 0;
593 }
594
595 if (src_offset % 32 || dst_offset % 32) {
596 return GL_FALSE;
597 }
598
599 if (0) {
600 fprintf(stderr, "src: size [%d x %d], pitch %d, "
601 "offset [%d x %d], format %s, bo %p\n",
602 src_width, src_height, src_pitch,
603 src_x_offset, src_y_offset,
604 _mesa_get_format_name(src_mesaformat),
605 src_bo);
606 fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
607 dst_pitch, dst_x_offset, dst_y_offset,
608 _mesa_get_format_name(dst_mesaformat), dst_bo);
609 fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
610 }
611
612 /* Flush is needed to make sure that source buffer has correct data */
613 radeonFlush(r300->radeon.glCtx);
614
615 if (!validate_buffers(r300, src_bo, dst_bo))
616 return 0;
617
618 rcommonEnsureCmdBufSpace(&r300->radeon, 200, __FUNCTION__);
619
620 other_stuff(r300);
621
622 r300_emit_tx_setup(r300, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
623
624 if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
625 r500_emit_fp_setup(r300, &r300->blit.fp_code.code.r500, dst_mesaformat);
626 r500_emit_rs_setup(r300);
627 } else {
628 r300_emit_fp_setup(r300, &r300->blit.fp_code.code.r300, dst_mesaformat);
629 r300_emit_rs_setup(r300);
630 }
631
632 emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2);
633 emit_vap_setup(r300);
634
635 emit_cb_setup(r300, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
636
637 emit_draw_packet(r300, src_width, src_height,
638 src_x_offset, src_y_offset,
639 dst_x_offset, dst_y_offset,
640 reg_width, reg_height,
641 flip_y);
642
643 r300EmitCacheFlush(r300);
644
645 radeonFlush(r300->radeon.glCtx);
646
647 return 1;
648 }