src/mesa/drivers/dri/r300/r300_blit.c

   1 /*
   2  * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r300_context.h"
  30
  31 #include "r300_blit.h"
  32 #include "r300_cmdbuf.h"
  33 #include "r300_emit.h"
  34 #include "r300_tex.h"
  35 #include "compiler/radeon_compiler.h"
  36 #include "compiler/radeon_opcodes.h"
  37
  38 static void vp_ins_outs(struct r300_vertex_program_compiler *c)
  39 {
  40     c->code->inputs[VERT_ATTRIB_POS] = 0;
  41     c->code->inputs[VERT_ATTRIB_TEX0] = 1;
  42     c->code->outputs[VERT_RESULT_HPOS] = 0;
  43     c->code->outputs[VERT_RESULT_TEX0] = 1;
  44 }
  45
  46 static void fp_allocate_hw_inputs(
  47     struct r300_fragment_program_compiler * c,
  48     void (*allocate)(void * data, unsigned input, unsigned hwreg),
  49     void * mydata)
  50 {
  51     allocate(mydata, FRAG_ATTRIB_TEX0, 0);
  52 }
  53
  54 static void create_vertex_program(struct r300_context *r300)
  55 {
  56     struct r300_vertex_program_compiler compiler;
  57     struct rc_instruction *inst;
  58
  59     rc_init(&compiler.Base);
  60
  61     inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
  62     inst->U.I.Opcode = RC_OPCODE_MOV;
  63     inst->U.I.DstReg.File = RC_FILE_OUTPUT;
  64     inst->U.I.DstReg.Index = VERT_RESULT_HPOS;
  65     inst->U.I.DstReg.RelAddr = 0;
  66     inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
  67     inst->U.I.SrcReg[0].Abs = 0;
  68     inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
  69     inst->U.I.SrcReg[0].Index = VERT_ATTRIB_POS;
  70     inst->U.I.SrcReg[0].Negate = 0;
  71     inst->U.I.SrcReg[0].RelAddr = 0;
  72     inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
  73
  74     inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
  75     inst->U.I.Opcode = RC_OPCODE_MOV;
  76     inst->U.I.DstReg.File = RC_FILE_OUTPUT;
  77     inst->U.I.DstReg.Index = VERT_RESULT_TEX0;
  78     inst->U.I.DstReg.RelAddr = 0;
  79     inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
  80     inst->U.I.SrcReg[0].Abs = 0;
  81     inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
  82     inst->U.I.SrcReg[0].Index = VERT_ATTRIB_TEX0;
  83     inst->U.I.SrcReg[0].Negate = 0;
  84     inst->U.I.SrcReg[0].RelAddr = 0;
  85     inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
  86
  87     compiler.Base.Program.InputsRead = (1 << VERT_ATTRIB_POS) | (1 << VERT_ATTRIB_TEX0);
  88     compiler.RequiredOutputs = compiler.Base.Program.OutputsWritten = (1 << VERT_RESULT_HPOS) | (1 << VERT_RESULT_TEX0);
  89     compiler.SetHwInputOutput = vp_ins_outs;
  90     compiler.code = &r300->blit.vp_code;
  91
  92     r3xx_compile_vertex_program(&compiler);
  93 }
  94
  95 static void create_fragment_program(struct r300_context *r300)
  96 {
  97     struct r300_fragment_program_compiler compiler;
  98     struct rc_instruction *inst;
  99
 100     memset(&compiler, 0, sizeof(struct r300_fragment_program_compiler));
 101     rc_init(&compiler.Base);
 102
 103     inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
 104     inst->U.I.Opcode = RC_OPCODE_TEX;
 105     inst->U.I.TexSrcTarget = RC_TEXTURE_2D;
 106     inst->U.I.TexSrcUnit = 0;
 107     inst->U.I.DstReg.File = RC_FILE_OUTPUT;
 108     inst->U.I.DstReg.Index = FRAG_RESULT_COLOR;
 109     inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
 110     inst->U.I.SrcReg[0].Abs = 0;
 111     inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
 112     inst->U.I.SrcReg[0].Index = FRAG_ATTRIB_TEX0;
 113     inst->U.I.SrcReg[0].Negate = 0;
 114     inst->U.I.SrcReg[0].RelAddr = 0;
 115     inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
 116
 117     compiler.Base.Program.InputsRead = (1 << FRAG_ATTRIB_TEX0);
 118     compiler.OutputColor[0] = FRAG_RESULT_COLOR;
 119     compiler.OutputDepth = FRAG_RESULT_DEPTH;
 120     compiler.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515);
 121     compiler.max_temp_regs = (compiler.is_r500) ? 128 : 32;
 122     compiler.code = &r300->blit.fp_code;
 123     compiler.AllocateHwInputs = fp_allocate_hw_inputs;
 124
 125     r3xx_compile_fragment_program(&compiler);
 126 }
 127
 128 void r300_blit_init(struct r300_context *r300)
 129 {
 130     if (r300->options.hw_tcl_enabled)
 131         create_vertex_program(r300);
 132     create_fragment_program(r300);
 133 }
 134
 135 static void r300_emit_tx_setup(struct r300_context *r300,
 136                                gl_format mesa_format,
 137                                struct radeon_bo *bo,
 138                                intptr_t offset,
 139                                unsigned width,
 140                                unsigned height,
 141                                unsigned pitch)
 142 {
 143     BATCH_LOCALS(&r300->radeon);
 144
 145     assert(width <= 2048);
 146     assert(height <= 2048);
 147     assert(r300TranslateTexFormat(mesa_format) >= 0);
 148     assert(offset % 32 == 0);
 149
 150     BEGIN_BATCH(17);
 151     OUT_BATCH_REGVAL(R300_TX_FILTER0_0,
 152                      (R300_TX_CLAMP_TO_EDGE  << R300_TX_WRAP_S_SHIFT) |
 153                      (R300_TX_CLAMP_TO_EDGE  << R300_TX_WRAP_T_SHIFT) |
 154                      (R300_TX_CLAMP_TO_EDGE  << R300_TX_WRAP_R_SHIFT) |
 155                      R300_TX_MIN_FILTER_MIP_NONE |
 156                      R300_TX_MIN_FILTER_NEAREST |
 157                      R300_TX_MAG_FILTER_NEAREST |
 158                      (0 << 28));
 159     OUT_BATCH_REGVAL(R300_TX_FILTER1_0, 0);
 160     OUT_BATCH_REGVAL(R300_TX_SIZE_0,
 161                      ((width-1) << R300_TX_WIDTHMASK_SHIFT) |
 162                      ((height-1) << R300_TX_HEIGHTMASK_SHIFT) |
 163                      (0 << R300_TX_DEPTHMASK_SHIFT) |
 164                      (0 << R300_TX_MAX_MIP_LEVEL_SHIFT) |
 165                      R300_TX_SIZE_TXPITCH_EN);
 166
 167     OUT_BATCH_REGVAL(R300_TX_FORMAT_0, r300TranslateTexFormat(mesa_format));
 168     OUT_BATCH_REGVAL(R300_TX_FORMAT2_0, pitch - 1);
 169     OUT_BATCH_REGSEQ(R300_TX_OFFSET_0, 1);
 170     OUT_BATCH_RELOC(0, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 171
 172     OUT_BATCH_REGSEQ(R300_TX_INVALTAGS, 2);
 173     OUT_BATCH(0);
 174     OUT_BATCH(1);
 175
 176     END_BATCH();
 177 }
 178
 179 #define EASY_US_FORMAT(FMT, C0, C1, C2, C3, SIGN) \
 180     (FMT  | R500_C0_SEL_##C0 | R500_C1_SEL_##C1 | \
 181     R500_C2_SEL_##C2 | R500_C3_SEL_##C3 | R500_OUT_SIGN(SIGN))
 182
 183 static uint32_t mesa_format_to_us_format(gl_format mesa_format)
 184 {
 185     switch(mesa_format)
 186     {
 187         case MESA_FORMAT_RGBA8888: // x
 188             return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0);
 189         case MESA_FORMAT_RGB565: // x
 190         case MESA_FORMAT_ARGB1555: // x
 191         case MESA_FORMAT_RGBA8888_REV: // x
 192             return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0);
 193         case MESA_FORMAT_ARGB8888: // x
 194             return EASY_US_FORMAT(R500_OUT_FMT_C4_8, B, G, R, A, 0);
 195         case MESA_FORMAT_ARGB8888_REV:
 196             return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0);
 197         case MESA_FORMAT_XRGB8888:
 198             return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0);
 199
 200         case MESA_FORMAT_RGB332:
 201             return EASY_US_FORMAT(R500_OUT_FMT_C_3_3_2, A, R, G, B, 0);
 202
 203         case MESA_FORMAT_RGBA_FLOAT32:
 204             return EASY_US_FORMAT(R500_OUT_FMT_C4_32_FP, R, G, B, A, 0);
 205         case MESA_FORMAT_RGBA_FLOAT16:
 206             return EASY_US_FORMAT(R500_OUT_FMT_C4_16_FP, R, G, B, A, 0);
 207         case MESA_FORMAT_ALPHA_FLOAT32:
 208             return EASY_US_FORMAT(R500_OUT_FMT_C_32_FP, A, A, A, A, 0);
 209         case MESA_FORMAT_ALPHA_FLOAT16:
 210             return EASY_US_FORMAT(R500_OUT_FMT_C_16_FP, A, A, A, A, 0);
 211
 212         case MESA_FORMAT_SIGNED_RGBA8888:
 213             return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0xf);
 214         case MESA_FORMAT_SIGNED_RGBA8888_REV:
 215             return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0xf);
 216         case MESA_FORMAT_SIGNED_RGBA_16:
 217             return EASY_US_FORMAT(R500_OUT_FMT_C4_16, R, G, B, A, 0xf);
 218
 219         default:
 220             fprintf(stderr, "Unsupported format %s for US output\n", _mesa_get_format_name(mesa_format));
 221             assert(0);
 222             return 0;
 223     }
 224 }
 225 #undef EASY_US_FORMAT
 226
 227 static void r500_emit_fp_setup(struct r300_context *r300,
 228                                struct r500_fragment_program_code *fp,
 229                                gl_format dst_format)
 230 {
 231     r500_emit_fp(r300, (uint32_t *)fp->inst, (fp->inst_end + 1) * 6, 0, 0, 0);
 232     BATCH_LOCALS(&r300->radeon);
 233
 234     BEGIN_BATCH(10);
 235     OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
 236     OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(fp->inst_end));
 237     OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(fp->inst_end));
 238     OUT_BATCH(0);
 239     OUT_BATCH_REGVAL(R500_US_CONFIG, 0);
 240     OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
 241     OUT_BATCH_REGVAL(R500_US_PIXSIZE, fp->max_temp_idx);
 242     END_BATCH();
 243 }
 244
 245 static void r500_emit_rs_setup(struct r300_context *r300)
 246 {
 247     BATCH_LOCALS(&r300->radeon);
 248
 249     BEGIN_BATCH(7);
 250     OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
 251     OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
 252     OUT_BATCH(0);
 253     OUT_BATCH_REGVAL(R500_RS_INST_0,
 254                      (0 << R500_RS_INST_TEX_ID_SHIFT) |
 255                      (0 << R500_RS_INST_TEX_ADDR_SHIFT) |
 256                      R500_RS_INST_TEX_CN_WRITE |
 257                      R500_RS_INST_COL_CN_NO_WRITE);
 258     OUT_BATCH_REGVAL(R500_RS_IP_0,
 259                      (0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 260                      (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 261                      (2 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 262                      (3 << R500_RS_IP_TEX_PTR_Q_SHIFT));
 263     END_BATCH();
 264 }
 265
 266 static void r300_emit_fp_setup(struct r300_context *r300,
 267                                struct r300_fragment_program_code *code,
 268                                gl_format dst_format)
 269 {
 270     unsigned i;
 271     BATCH_LOCALS(&r300->radeon);
 272
 273     BEGIN_BATCH((code->alu.length + 1) * 4 + code->tex.length + 1 + 11);
 274
 275     OUT_BATCH_REGSEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
 276     for (i = 0; i < code->alu.length; i++) {
 277         OUT_BATCH(code->alu.inst[i].rgb_inst);
 278     }
 279     OUT_BATCH_REGSEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
 280     for (i = 0; i < code->alu.length; i++) {
 281         OUT_BATCH(code->alu.inst[i].rgb_addr);
 282     }
 283     OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
 284     for (i = 0; i < code->alu.length; i++) {
 285         OUT_BATCH(code->alu.inst[i].alpha_inst);
 286     }
 287     OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
 288     for (i = 0; i < code->alu.length; i++) {
 289         OUT_BATCH(code->alu.inst[i].alpha_addr);
 290     }
 291
 292     OUT_BATCH_REGSEQ(R300_US_TEX_INST_0, code->tex.length);
 293     OUT_BATCH_TABLE(code->tex.inst, code->tex.length);
 294
 295     OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
 296     OUT_BATCH(R300_PFS_CNTL_FIRST_NODE_HAS_TEX);
 297     OUT_BATCH(code->pixsize);
 298     OUT_BATCH(code->code_offset);
 299     OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
 300     OUT_BATCH_TABLE(code->code_addr, 4);
 301     OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
 302     END_BATCH();
 303 }
 304
 305 static void r300_emit_rs_setup(struct r300_context *r300)
 306 {
 307     BATCH_LOCALS(&r300->radeon);
 308
 309     BEGIN_BATCH(7);
 310     OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
 311     OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
 312     OUT_BATCH(0);
 313     OUT_BATCH_REGVAL(R300_RS_INST_0,
 314                      R300_RS_INST_TEX_ID(0) |
 315                      R300_RS_INST_TEX_ADDR(0) |
 316                      R300_RS_INST_TEX_CN_WRITE);
 317     OUT_BATCH_REGVAL(R300_RS_IP_0,
 318                      R300_RS_TEX_PTR(0) |
 319                      R300_RS_SEL_S(R300_RS_SEL_C0) |
 320                      R300_RS_SEL_T(R300_RS_SEL_C1) |
 321                      R300_RS_SEL_R(R300_RS_SEL_K0) |
 322                      R300_RS_SEL_Q(R300_RS_SEL_K1));
 323     END_BATCH();
 324 }
 325
 326 static void emit_pvs_setup(struct r300_context *r300,
 327                            uint32_t *vp_code,
 328                            unsigned vp_len)
 329 {
 330     BATCH_LOCALS(&r300->radeon);
 331
 332     r300_emit_vpu(r300, vp_code, vp_len * 4, R300_PVS_CODE_START);
 333
 334     BEGIN_BATCH(4);
 335     OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
 336     OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
 337               ((vp_len - 1)  << R300_PVS_XYZW_VALID_INST_SHIFT) |
 338               ((vp_len - 1)<< R300_PVS_LAST_INST_SHIFT));
 339     OUT_BATCH(0);
 340     OUT_BATCH((vp_len - 1) << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
 341     END_BATCH();
 342 }
 343
 344 static void emit_vap_setup(struct r300_context *r300)
 345 {
 346     int tex_offset;
 347     BATCH_LOCALS(&r300->radeon);
 348
 349     if (r300->options.hw_tcl_enabled)
 350         tex_offset = 1;
 351     else
 352         tex_offset = 6;
 353
 354     BEGIN_BATCH(12);
 355     OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
 356     OUT_BATCH(R300_VTX_XY_FMT | R300_VTX_Z_FMT);
 357     OUT_BATCH(4);
 358
 359     OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
 360     OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_0,
 361                      ((R300_DATA_TYPE_FLOAT_2 | (0 << R300_DST_VEC_LOC_SHIFT)) << 0) |
 362                      (((tex_offset << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_2 | R300_LAST_VEC) << 16));
 363     OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
 364                     ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
 365                        (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
 366                        (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) |
 367                        (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) |
 368                        (0xf << R300_WRITE_ENA_SHIFT) ) << 0) |
 369                      (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
 370                        (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
 371                        (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) |
 372                        (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) |
 373                        (0xf << R300_WRITE_ENA_SHIFT) ) << 16) ) );
 374     OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 375     OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT);
 376     OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS);
 377     END_BATCH();
 378 }
 379
 380 static GLboolean validate_buffers(struct r300_context *r300,
 381                                   struct radeon_bo *src_bo,
 382                                   struct radeon_bo *dst_bo)
 383 {
 384     int ret;
 385
 386     radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
 387
 388     ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
 389                                         src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 390     if (ret)
 391         return GL_FALSE;
 392
 393     ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
 394                                         dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
 395     if (ret)
 396         return GL_FALSE;
 397
 398     return GL_TRUE;
 399 }
 400
 401 /**
 402  * Calculate texcoords for given image region.
 403  * Output values are [minx, maxx, miny, maxy]
 404  */
 405 static void calc_tex_coords(float img_width, float img_height,
 406                             float x, float y,
 407                             float reg_width, float reg_height,
 408                             unsigned flip_y, float *buf)
 409 {
 410     buf[0] = x / img_width;
 411     buf[1] = buf[0] + reg_width / img_width;
 412     buf[2] = y / img_height;
 413     buf[3] = buf[2] + reg_height / img_height;
 414     if (flip_y)
 415     {
 416         buf[2] = 1.0 - buf[2];
 417         buf[3] = 1.0 - buf[3];
 418     }
 419 }
 420
 421 static void emit_draw_packet(struct r300_context *r300,
 422                              unsigned src_width, unsigned src_height,
 423                              unsigned src_x_offset, unsigned src_y_offset,
 424                              unsigned dst_x_offset, unsigned dst_y_offset,
 425                              unsigned reg_width, unsigned reg_height,
 426                              unsigned flip_y)
 427 {
 428     float texcoords[4];
 429
 430     calc_tex_coords(src_width, src_height,
 431                     src_x_offset, src_y_offset,
 432                     reg_width, reg_height,
 433                     flip_y, texcoords);
 434
 435     float verts[] = { dst_x_offset, dst_y_offset,
 436                       texcoords[0], texcoords[2],
 437                       dst_x_offset, dst_y_offset + reg_height,
 438                       texcoords[0], texcoords[3],
 439                       dst_x_offset + reg_width, dst_y_offset + reg_height,
 440                       texcoords[1], texcoords[3],
 441                       dst_x_offset + reg_width, dst_y_offset,
 442                       texcoords[1], texcoords[2] };
 443
 444     BATCH_LOCALS(&r300->radeon);
 445
 446     BEGIN_BATCH(19);
 447     OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_IMMD_2, 16);
 448     OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED |
 449               (4 << 16) | R300_VAP_VF_CNTL__PRIM_QUADS);
 450     OUT_BATCH_TABLE(verts, 16);
 451     END_BATCH();
 452 }
 453
 454 static void other_stuff(struct r300_context *r300)
 455 {
 456     BATCH_LOCALS(&r300->radeon);
 457
 458     BEGIN_BATCH(13);
 459     OUT_BATCH_REGVAL(R300_GA_POLY_MODE,
 460                      R300_GA_POLY_MODE_FRONT_PTYPE_TRI | R300_GA_POLY_MODE_BACK_PTYPE_TRI);
 461     OUT_BATCH_REGVAL(R300_SU_CULL_MODE, R300_FRONT_FACE_CCW);
 462     OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
 463     OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
 464     OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
 465     OUT_BATCH(0x0);
 466     OUT_BATCH(0x0);
 467     OUT_BATCH_REGVAL(R300_ZB_CNTL, 0);
 468     END_BATCH();
 469     if (r300->options.hw_tcl_enabled) {
 470         BEGIN_BATCH(2);
 471         OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
 472         END_BATCH();
 473     }
 474 }
 475
 476 static void emit_cb_setup(struct r300_context *r300,
 477                           struct radeon_bo *bo,
 478                           intptr_t offset,
 479                           gl_format mesa_format,
 480                           unsigned pitch,
 481                           unsigned width,
 482                           unsigned height)
 483 {
 484     BATCH_LOCALS(&r300->radeon);
 485
 486     unsigned x1, y1, x2, y2;
 487     x1 = 0;
 488     y1 = 0;
 489     x2 = width - 1;
 490     y2 = height - 1;
 491
 492     if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
 493         x1 += R300_SCISSORS_OFFSET;
 494         y1 += R300_SCISSORS_OFFSET;
 495         x2 += R300_SCISSORS_OFFSET;
 496         y2 += R300_SCISSORS_OFFSET;
 497     }
 498
 499     r300_emit_cb_setup(r300, bo, offset, mesa_format,
 500                        _mesa_get_format_bytes(mesa_format),
 501                        _mesa_format_row_stride(mesa_format, pitch));
 502
 503     BEGIN_BATCH_NO_AUTOSTATE(5);
 504     OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 505     OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
 506     OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
 507     OUT_BATCH_REGVAL(R300_RB3D_CCTL, 0);
 508     END_BATCH();
 509 }
 510
 511 unsigned r300_check_blit(gl_format dst_format)
 512 {
 513     switch (dst_format) {
 514         case MESA_FORMAT_RGB565:
 515         case MESA_FORMAT_ARGB1555:
 516         case MESA_FORMAT_RGBA8888:
 517         case MESA_FORMAT_RGBA8888_REV:
 518         case MESA_FORMAT_ARGB8888:
 519         case MESA_FORMAT_ARGB8888_REV:
 520         case MESA_FORMAT_XRGB8888:
 521             break;
 522         default:
 523             return 0;
 524     }
 525
 526     if (_mesa_get_format_bits(dst_format, GL_DEPTH_BITS) > 0)
 527         return 0;
 528
 529     return 1;
 530 }
 531
 532 /**
 533  * Copy a region of [@a width x @a height] pixels from source buffer
 534  * to destination buffer.
 535  * @param[in] r300 r300 context
 536  * @param[in] src_bo source radeon buffer object
 537  * @param[in] src_offset offset of the source image in the @a src_bo
 538  * @param[in] src_mesaformat source image format
 539  * @param[in] src_pitch aligned source image width
 540  * @param[in] src_width source image width
 541  * @param[in] src_height source image height
 542  * @param[in] src_x_offset x offset in the source image
 543  * @param[in] src_y_offset y offset in the source image
 544  * @param[in] dst_bo destination radeon buffer object
 545  * @param[in] dst_offset offset of the destination image in the @a dst_bo
 546  * @param[in] dst_mesaformat destination image format
 547  * @param[in] dst_pitch aligned destination image width
 548  * @param[in] dst_width destination image width
 549  * @param[in] dst_height destination image height
 550  * @param[in] dst_x_offset x offset in the destination image
 551  * @param[in] dst_y_offset y offset in the destination image
 552  * @param[in] width region width
 553  * @param[in] height region height
 554  * @param[in] flip_y set if y coords of the source image need to be flipped
 555  */
 556 unsigned r300_blit(GLcontext *ctx,
 557                    struct radeon_bo *src_bo,
 558                    intptr_t src_offset,
 559                    gl_format src_mesaformat,
 560                    unsigned src_pitch,
 561                    unsigned src_width,
 562                    unsigned src_height,
 563                    unsigned src_x_offset,
 564                    unsigned src_y_offset,
 565                    struct radeon_bo *dst_bo,
 566                    intptr_t dst_offset,
 567                    gl_format dst_mesaformat,
 568                    unsigned dst_pitch,
 569                    unsigned dst_width,
 570                    unsigned dst_height,
 571                    unsigned dst_x_offset,
 572                    unsigned dst_y_offset,
 573                    unsigned reg_width,
 574                    unsigned reg_height,
 575                    unsigned flip_y)
 576 {
 577     r300ContextPtr r300 = R300_CONTEXT(ctx);
 578
 579     if (!r300_check_blit(dst_mesaformat))
 580         return 0;
 581
 582     /* Make sure that colorbuffer has even width - hw limitation */
 583     if (dst_pitch % 2 > 0)
 584         ++dst_pitch;
 585
 586     /* Need to clamp the region size to make sure
 587      * we don't read outside of the source buffer
 588      * or write outside of the destination buffer.
 589      */
 590     if (reg_width + src_x_offset > src_width)
 591         reg_width = src_width - src_x_offset;
 592     if (reg_height + src_y_offset > src_height)
 593         reg_height = src_height - src_y_offset;
 594     if (reg_width + dst_x_offset > dst_width)
 595         reg_width = dst_width - dst_x_offset;
 596     if (reg_height + dst_y_offset > dst_height)
 597         reg_height = dst_height - dst_y_offset;
 598
 599     if (src_bo == dst_bo) {
 600         return 0;
 601     }
 602
 603     if (src_offset % 32 || dst_offset % 32) {
 604         return GL_FALSE;
 605     }
 606
 607     if (0) {
 608         fprintf(stderr, "src: size [%d x %d], pitch %d, "
 609                 "offset [%d x %d], format %s, bo %p\n",
 610                 src_width, src_height, src_pitch,
 611                 src_x_offset, src_y_offset,
 612                 _mesa_get_format_name(src_mesaformat),
 613                 src_bo);
 614         fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
 615                 dst_pitch, dst_x_offset, dst_y_offset,
 616                 _mesa_get_format_name(dst_mesaformat), dst_bo);
 617         fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
 618     }
 619
 620     /* Flush is needed to make sure that source buffer has correct data */
 621     radeonFlush(r300->radeon.glCtx);
 622
 623     if (!validate_buffers(r300, src_bo, dst_bo))
 624         return 0;
 625
 626     rcommonEnsureCmdBufSpace(&r300->radeon, 200, __FUNCTION__);
 627
 628     other_stuff(r300);
 629
 630     r300_emit_tx_setup(r300, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
 631
 632     if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 633         r500_emit_fp_setup(r300, &r300->blit.fp_code.code.r500, dst_mesaformat);
 634         r500_emit_rs_setup(r300);
 635     } else {
 636         r300_emit_fp_setup(r300, &r300->blit.fp_code.code.r300, dst_mesaformat);
 637         r300_emit_rs_setup(r300);
 638     }
 639
 640     if (r300->options.hw_tcl_enabled)
 641         emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2);
 642
 643     emit_vap_setup(r300);
 644
 645     emit_cb_setup(r300, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
 646
 647     emit_draw_packet(r300, src_width, src_height,
 648                      src_x_offset, src_y_offset,
 649                      dst_x_offset, dst_y_offset,
 650                      reg_width, reg_height,
 651                      flip_y);
 652
 653     r300EmitCacheFlush(r300);
 654
 655     radeonFlush(r300->radeon.glCtx);
 656
 657     return 1;
 658 }