src/mesa/drivers/dri/r300/r300_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42
  43 #include "drm.h"
  44 #include "radeon_drm.h"
  45
  46 #include "r300_context.h"
  47 #include "r300_reg.h"
  48 #include "r300_cmdbuf.h"
  49 #include "r300_emit.h"
  50 #include "radeon_bocs_wrapper.h"
  51 #include "radeon_mipmap_tree.h"
  52 #include "radeon_queryobj.h"
  53
  54 /** # of dwords reserved for additional instructions that may need to be written
  55  * during flushing.
  56  */
  57 #define SPACE_FOR_FLUSHING      4
  58
  59 static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
  60 {
  61     if (r300->radeon.radeonScreen->kernel_mm) {
  62         return ((((*pkt) >> 16) & 0x3FFF) + 1);
  63     } else {
  64         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
  65         return t->packet0.count;
  66     }
  67 }
  68
  69 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
  70 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
  71
  72 static int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
  73 {
  74         r300ContextPtr r300 = R300_CONTEXT(ctx);
  75         int cnt;
  76         int extra = 1;
  77         cnt = vpu_count(atom->cmd);
  78
  79         if (r300->radeon.radeonScreen->kernel_mm) {
  80                 extra = 3;
  81         }
  82
  83         return cnt ? (cnt * 4) + extra : 0;
  84 }
  85
  86 static int check_vpp(GLcontext *ctx, struct radeon_state_atom *atom)
  87 {
  88     r300ContextPtr r300 = R300_CONTEXT(ctx);
  89     int cnt;
  90     int extra = 1;
  91
  92     if (r300->radeon.radeonScreen->kernel_mm) {
  93         cnt = r300->selected_vp->code.constants.Count * 4;
  94         extra = 3;
  95     } else {
  96         cnt = vpu_count(atom->cmd);
  97         extra = 1;
  98     }
  99
 100     return cnt ? (cnt * 4) + extra : 0;
 101 }
 102
 103 void r300_emit_vpu(struct r300_context *r300,
 104                    uint32_t *data,
 105                    unsigned len,
 106                    uint32_t addr)
 107 {
 108     BATCH_LOCALS(&r300->radeon);
 109
 110     BEGIN_BATCH_NO_AUTOSTATE(3 + len);
 111     OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
 112     OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, len-1) | RADEON_ONE_REG_WR);
 113     OUT_BATCH_TABLE(data, len);
 114     END_BATCH();
 115 }
 116
 117 static void emit_vpu_state(GLcontext *ctx, struct radeon_state_atom * atom)
 118 {
 119     r300ContextPtr r300 = R300_CONTEXT(ctx);
 120     drm_r300_cmd_header_t cmd;
 121     uint32_t addr;
 122
 123     cmd.u = atom->cmd[0];
 124     addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
 125
 126     r300_emit_vpu(r300, &atom->cmd[1], vpu_count(atom->cmd) * 4, addr);
 127 }
 128
 129 static void emit_vpp_state(GLcontext *ctx, struct radeon_state_atom * atom)
 130 {
 131     r300ContextPtr r300 = R300_CONTEXT(ctx);
 132     drm_r300_cmd_header_t cmd;
 133     uint32_t addr;
 134
 135     cmd.u = atom->cmd[0];
 136     addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
 137
 138     r300_emit_vpu(r300, &atom->cmd[1], r300->selected_vp->code.constants.Count * 4, addr);
 139 }
 140
 141 void r500_emit_fp(struct r300_context *r300,
 142                   uint32_t *data,
 143                   unsigned len,
 144                   uint32_t addr,
 145                   unsigned type,
 146                   unsigned clamp)
 147 {
 148     BATCH_LOCALS(&r300->radeon);
 149
 150     addr |= (type << 16);
 151     addr |= (clamp << 17);
 152
 153     BEGIN_BATCH_NO_AUTOSTATE(len + 3);
 154     OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
 155     OUT_BATCH(addr);
 156     OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, len-1) | RADEON_ONE_REG_WR);
 157     OUT_BATCH_TABLE(data, len);
 158     END_BATCH();
 159 }
 160
 161 static void emit_r500fp_atom(GLcontext *ctx, struct radeon_state_atom * atom)
 162 {
 163     r300ContextPtr r300 = R300_CONTEXT(ctx);
 164     drm_r300_cmd_header_t cmd;
 165     uint32_t addr, count;
 166     int type, clamp;
 167
 168     cmd.u = atom->cmd[0];
 169     addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
 170     type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 171     clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 172
 173     if (type) {
 174         count = r500fp_count(atom->cmd) * 4;
 175     } else {
 176         count = r500fp_count(atom->cmd) * 6;
 177     }
 178
 179     r500_emit_fp(r300, &atom->cmd[1], count, addr, type, clamp);
 180 }
 181
 182 static int check_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 183 {
 184         r300ContextPtr r300 = R300_CONTEXT(ctx);
 185         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 186         int dw = 0, i;
 187         if (atom->cmd[0] == CP_PACKET2) {
 188                 return dw;
 189         }
 190         for(i = 0; i < numtmus; ++i) {
 191                 radeonTexObj *t = r300->hw.textures[i];
 192                 if (!t && !r300->radeon.radeonScreen->kernel_mm) {
 193                         dw += 0;
 194                 } else if (t && t->image_override && !t->bo) {
 195                         if (!r300->radeon.radeonScreen->kernel_mm)
 196                                 dw += 2;
 197                 } else
 198                         dw += 4;
 199         }
 200         return dw;
 201 }
 202
 203 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 204 {
 205         r300ContextPtr r300 = R300_CONTEXT(ctx);
 206         BATCH_LOCALS(&r300->radeon);
 207         int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
 208         int i;
 209
 210         for(i = 0; i < numtmus; ++i) {
 211                 radeonTexObj *t = r300->hw.textures[i];
 212                 if (t && !t->image_override) {
 213                         BEGIN_BATCH_NO_AUTOSTATE(4);
 214                         OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 215                         OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
 216                                         RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 217                         END_BATCH();
 218                 } else if (!t) {
 219                         /* Texture unit hasn't a texture bound.
 220                          * We assign the current color buffer as a fakery to make
 221                          * KIL work on KMS (without it, the CS checker will complain).
 222                          */
 223                         if (r300->radeon.radeonScreen->kernel_mm) {
 224                                 struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
 225                                 if (rrb && rrb->bo) {
 226                                         BEGIN_BATCH_NO_AUTOSTATE(4);
 227                                         OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 228                                         OUT_BATCH_RELOC(0, rrb->bo, 0,
 229                                                         RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 230                                         END_BATCH();
 231                                 }
 232                         }
 233                 } else { /* override cases */
 234                         if (t->bo) {
 235                                 BEGIN_BATCH_NO_AUTOSTATE(4);
 236                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 237                                 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 238                                                 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 239                                 END_BATCH();
 240                         } else if (!r300->radeon.radeonScreen->kernel_mm) {
 241                                 BEGIN_BATCH_NO_AUTOSTATE(2);
 242                                 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
 243                                 OUT_BATCH(t->override_offset);
 244                                 END_BATCH();
 245                         } else {
 246                                 /* Texture unit hasn't a texture bound nothings to do */
 247                         }
 248                 }
 249         }
 250 }
 251
 252 void r300_emit_scissor(GLcontext *ctx)
 253 {
 254         r300ContextPtr r300 = R300_CONTEXT(ctx);
 255         BATCH_LOCALS(&r300->radeon);
 256     unsigned x1, y1, x2, y2;
 257         struct radeon_renderbuffer *rrb;
 258
 259     if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 260         return;
 261     }
 262         rrb = radeon_get_colorbuffer(&r300->radeon);
 263         if (!rrb || !rrb->bo) {
 264                 fprintf(stderr, "no rrb\n");
 265                 return;
 266         }
 267     if (r300->radeon.state.scissor.enabled) {
 268         x1 = r300->radeon.state.scissor.rect.x1;
 269         y1 = r300->radeon.state.scissor.rect.y1;
 270         x2 = r300->radeon.state.scissor.rect.x2;
 271         y2 = r300->radeon.state.scissor.rect.y2;
 272     } else {
 273         x1 = 0;
 274         y1 = 0;
 275         x2 = rrb->base.Width - 1;
 276         y2 = rrb->base.Height - 1;
 277     }
 278     if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
 279         x1 += R300_SCISSORS_OFFSET;
 280         y1 += R300_SCISSORS_OFFSET;
 281         x2 += R300_SCISSORS_OFFSET;
 282         y2 += R300_SCISSORS_OFFSET;
 283     }
 284     BEGIN_BATCH_NO_AUTOSTATE(3);
 285     OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 286     OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
 287     OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
 288     END_BATCH();
 289 }
 290 static int check_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 291 {
 292         r300ContextPtr r300 = R300_CONTEXT(ctx);
 293         uint32_t dw = 6 + 3 + 16;
 294         if (r300->radeon.radeonScreen->kernel_mm)
 295                 dw += 2;
 296         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 297                 dw -= 3 + 16;
 298         }
 299         return dw;
 300 }
 301
 302 static void emit_scissor(struct r300_context *r300,
 303                          unsigned width,
 304                          unsigned height)
 305 {
 306     int i;
 307     BATCH_LOCALS(&r300->radeon);
 308     if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 309         BEGIN_BATCH_NO_AUTOSTATE(3);
 310         OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 311         OUT_BATCH(0);
 312         OUT_BATCH(((width - 1) << R300_SCISSORS_X_SHIFT) |
 313                 ((height - 1) << R300_SCISSORS_Y_SHIFT));
 314         END_BATCH();
 315         BEGIN_BATCH_NO_AUTOSTATE(16);
 316         for (i = 0; i < 4; i++) {
 317             OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 318             OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
 319             OUT_BATCH(((width - 1) << R300_CLIPRECT_X_SHIFT) | ((height - 1) << R300_CLIPRECT_Y_SHIFT));
 320         }
 321         OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 322         OUT_BATCH(0xAAAA);
 323         OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 324         OUT_BATCH(0xffffff);
 325         END_BATCH();
 326     } else {
 327         BEGIN_BATCH_NO_AUTOSTATE(3);
 328         OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
 329         OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
 330                 (R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
 331         OUT_BATCH(((width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
 332                 ((height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
 333         END_BATCH();
 334         BEGIN_BATCH_NO_AUTOSTATE(16);
 335         for (i = 0; i < 4; i++) {
 336             OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
 337             OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
 338             OUT_BATCH(((R300_SCISSORS_OFFSET + width - 1) << R300_CLIPRECT_X_SHIFT) |
 339                         ((R300_SCISSORS_OFFSET + height - 1) << R300_CLIPRECT_Y_SHIFT));
 340         }
 341         OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
 342         OUT_BATCH(0xAAAA);
 343         OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
 344         OUT_BATCH(0xffffff);
 345         END_BATCH();
 346     }
 347 }
 348
 349 void r300_emit_cb_setup(struct r300_context *r300,
 350                         struct radeon_bo *bo,
 351                         uint32_t offset,
 352                         GLuint format,
 353                         unsigned cpp,
 354                         unsigned pitch)
 355 {
 356     BATCH_LOCALS(&r300->radeon);
 357     uint32_t cbpitch = pitch / cpp;
 358     uint32_t dw = 6;
 359
 360     assert(offset % 32 == 0);
 361
 362     switch (format) {
 363         case MESA_FORMAT_RGB565:
 364             assert(_mesa_little_endian());
 365             cbpitch |= R300_COLOR_FORMAT_RGB565;
 366             break;
 367         case MESA_FORMAT_RGB565_REV:
 368             assert(!_mesa_little_endian());
 369             cbpitch |= R300_COLOR_FORMAT_RGB565;
 370             break;
 371         case MESA_FORMAT_ARGB4444:
 372             assert(_mesa_little_endian());
 373             cbpitch |= R300_COLOR_FORMAT_ARGB4444;
 374             break;
 375         case MESA_FORMAT_ARGB4444_REV:
 376             assert(!_mesa_little_endian());
 377             cbpitch |= R300_COLOR_FORMAT_ARGB4444;
 378             break;
 379         case MESA_FORMAT_ARGB1555:
 380             assert(_mesa_little_endian());
 381             cbpitch |= R300_COLOR_FORMAT_ARGB1555;
 382             break;
 383         case MESA_FORMAT_ARGB1555_REV:
 384             assert(!_mesa_little_endian());
 385             cbpitch |= R300_COLOR_FORMAT_ARGB1555;
 386             break;
 387         default:
 388             if (cpp == 4) {
 389                 cbpitch |= R300_COLOR_FORMAT_ARGB8888;
 390             } else {
 391                 _mesa_problem(r300->radeon.glCtx, "unexpected format in emit_cb_offset()");;
 392             }
 393             break;
 394     }
 395
 396     if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 397         cbpitch |= R300_COLOR_TILE_ENABLE;
 398
 399     if (r300->radeon.radeonScreen->kernel_mm)
 400         dw += 2;
 401
 402     BEGIN_BATCH_NO_AUTOSTATE(dw);
 403     OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
 404     OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 405     OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
 406     if (!r300->radeon.radeonScreen->kernel_mm)
 407         OUT_BATCH(cbpitch);
 408     else
 409         OUT_BATCH_RELOC(cbpitch, bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 410     END_BATCH();
 411 }
 412
 413 static void emit_cb_offset_atom(GLcontext *ctx, struct radeon_state_atom * atom)
 414 {
 415     r300ContextPtr r300 = R300_CONTEXT(ctx);
 416     struct radeon_renderbuffer *rrb;
 417     uint32_t offset = r300->radeon.state.color.draw_offset;
 418
 419     rrb = radeon_get_colorbuffer(&r300->radeon);
 420     if (!rrb || !rrb->bo) {
 421         fprintf(stderr, "no rrb\n");
 422         return;
 423     }
 424
 425     if (RADEON_DEBUG & RADEON_STATE)
 426         fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
 427
 428     r300_emit_cb_setup(r300, rrb->bo, offset, rrb->base.Format, rrb->cpp, rrb->pitch);
 429
 430     if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 431         emit_scissor(r300, rrb->base.Width, rrb->base.Height);
 432     }
 433 }
 434
 435 static int check_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 436 {
 437         r300ContextPtr r300 = R300_CONTEXT(ctx);
 438         uint32_t dw;
 439         dw = 6;
 440         if (r300->radeon.radeonScreen->kernel_mm)
 441                 dw += 2;
 442         return dw;
 443 }
 444
 445 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 446 {
 447         r300ContextPtr r300 = R300_CONTEXT(ctx);
 448         BATCH_LOCALS(&r300->radeon);
 449         struct radeon_renderbuffer *rrb;
 450         uint32_t zbpitch;
 451         uint32_t dw = atom->check(ctx, atom);
 452
 453         rrb = radeon_get_depthbuffer(&r300->radeon);
 454         if (!rrb)
 455                 return;
 456
 457         zbpitch = (rrb->pitch / rrb->cpp);
 458         if (!r300->radeon.radeonScreen->kernel_mm) {
 459             if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 460                 zbpitch |= R300_DEPTHMACROTILE_ENABLE;
 461            }
 462             if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 463                 zbpitch |= R300_DEPTHMICROTILE_TILED;
 464             }
 465         }
 466
 467         BEGIN_BATCH_NO_AUTOSTATE(dw);
 468         OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
 469         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 470         OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
 471         if (!r300->radeon.radeonScreen->kernel_mm)
 472             OUT_BATCH(zbpitch);
 473         else
 474             OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 475         END_BATCH();
 476 }
 477
 478 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
 479 {
 480         r300ContextPtr r300 = R300_CONTEXT(ctx);
 481         BATCH_LOCALS(&r300->radeon);
 482         struct radeon_renderbuffer *rrb;
 483         uint32_t format = 0;
 484
 485         rrb = radeon_get_depthbuffer(&r300->radeon);
 486         if (!rrb)
 487           format = 0;
 488         else {
 489           if (rrb->cpp == 2)
 490             format = R300_DEPTHFORMAT_16BIT_INT_Z;
 491           else if (rrb->cpp == 4)
 492             format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
 493         }
 494
 495         BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
 496         OUT_BATCH(atom->cmd[0]);
 497         atom->cmd[1] &= ~0xf;
 498         atom->cmd[1] |= format;
 499         OUT_BATCH(atom->cmd[1]);
 500         OUT_BATCH(atom->cmd[2]);
 501         OUT_BATCH(atom->cmd[3]);
 502         OUT_BATCH(atom->cmd[4]);
 503         END_BATCH();
 504 }
 505
 506 static int check_never(GLcontext *ctx, struct radeon_state_atom *atom)
 507 {
 508    return 0;
 509 }
 510
 511 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 512 {
 513         return atom->cmd_size;
 514 }
 515
 516 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 517 {
 518         r300ContextPtr r300 = R300_CONTEXT(ctx);
 519         int cnt;
 520         if (atom->cmd[0] == CP_PACKET2) {
 521                 return 0;
 522         }
 523         cnt = packet0_count(r300, atom->cmd);
 524         return cnt ? cnt + 1 : 0;
 525 }
 526
 527 static int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
 528 {
 529         int cnt;
 530         r300ContextPtr r300 = R300_CONTEXT(ctx);
 531         int extra = 1;
 532         cnt = r500fp_count(atom->cmd);
 533         if (r300->radeon.radeonScreen->kernel_mm)
 534                 extra = 3;
 535
 536         return cnt ? (cnt * 6) + extra : 0;
 537 }
 538
 539 static int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
 540 {
 541         int cnt;
 542         r300ContextPtr r300 = R300_CONTEXT(ctx);
 543         int extra = 1;
 544         cnt = r500fp_count(atom->cmd);
 545         if (r300->radeon.radeonScreen->kernel_mm)
 546                 extra = 3;
 547
 548         cnt = r500fp_count(atom->cmd);
 549         return cnt ? (cnt * 4) + extra : 0;
 550 }
 551
 552 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 553    do {                                                                 \
 554       r300->hw.ATOM.cmd_size = (SZ);                                    \
 555       r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 556       r300->hw.ATOM.name = #ATOM;                                       \
 557       r300->hw.ATOM.idx = (IDX);                                        \
 558       r300->hw.ATOM.check = check_##CHK;                                \
 559       r300->hw.ATOM.dirty = GL_FALSE;                                   \
 560       r300->radeon.hw.max_state_size += (SZ);                                   \
 561       insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM);                \
 562    } while (0)
 563 /**
 564  * Allocate memory for the command buffer and initialize the state atom
 565  * list. Note that the initial hardware state is set by r300InitState().
 566  */
 567 void r300InitCmdBuf(r300ContextPtr r300)
 568 {
 569         int mtu;
 570         int has_tcl;
 571         int is_r500 = 0;
 572
 573         has_tcl = r300->options.hw_tcl_enabled;
 574
 575         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 576                 is_r500 = 1;
 577
 578         r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 579
 580         mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
 581         if (RADEON_DEBUG & RADEON_TEXTURE) {
 582                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 583         }
 584
 585         /* Setup the atom linked list */
 586         make_empty_list(&r300->radeon.hw.atomlist);
 587         r300->radeon.hw.atomlist.name = "atom-list";
 588
 589         /* Initialize state atoms */
 590         ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
 591         r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
 592         ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
 593         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
 594         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
 595         r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
 596         if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
 597             ALLOC_STATE(vap_index_offset, always, 2, 0);
 598             r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
 599             r300->hw.vap_index_offset.cmd[1] = 0;
 600         }
 601         ALLOC_STATE(vte, always, 3, 0);
 602         r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
 603         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 604         r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
 605         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 606         r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
 607         ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
 608         r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
 609             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
 610         ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
 611         r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
 612             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 613         ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
 614         r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
 615         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 616         r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 617
 618         if (has_tcl) {
 619                 ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 620                 r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
 621                 ALLOC_STATE(vap_clip, always, 5, 0);
 622                 r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
 623                 ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 624                 r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 625         }
 626
 627         ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
 628         r300->hw.vof.cmd[R300_VOF_CMD_0] =
 629             cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
 630
 631         if (has_tcl) {
 632                 ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
 633                 r300->hw.pvs.cmd[R300_PVS_CMD_0] =
 634                     cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
 635         }
 636
 637         ALLOC_STATE(gb_enable, always, 2, 0);
 638         r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
 639         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 640                 ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
 641         } else {
 642                 ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
 643         }
 644         r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
 645         ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
 646         r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
 647         ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
 648         r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
 649         ALLOC_STATE(ga_point_s0, always, 5, 0);
 650         r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
 651         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 652         r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
 653         ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
 654         r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
 655         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 656         r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
 657         ALLOC_STATE(lcntl, always, 2, 0);
 658         r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
 659         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 660         r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
 661         if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
 662                 ALLOC_STATE(shade, always, 2, 0);
 663         } else {
 664                 ALLOC_STATE(shade, never, 2, 0);
 665         }
 666         r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
 667         ALLOC_STATE(shade2, always, 4, 0);
 668         r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
 669         ALLOC_STATE(polygon_mode, always, 4, 0);
 670         r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
 671         ALLOC_STATE(fogp, always, 3, 0);
 672         r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
 673         ALLOC_STATE(zbias_cntl, always, 2, 0);
 674         r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
 675         ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
 676         r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
 677             cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
 678         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 679         r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
 680         ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
 681         r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
 682         ALLOC_STATE(su_depth_scale, always, 3, 0);
 683         r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
 684         ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
 685         r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
 686         if (is_r500) {
 687                 ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
 688                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
 689                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 690                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
 691         } else {
 692                 ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
 693                 r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
 694                 ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
 695                 r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
 696         }
 697         ALLOC_STATE(sc_hyperz, always, 3, 0);
 698         r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
 699         ALLOC_STATE(sc_screendoor, always, 2, 0);
 700         r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
 701         ALLOC_STATE(us_out_fmt, always, 6, 0);
 702         r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
 703
 704         if (is_r500) {
 705                 ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
 706                 r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
 707                 r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
 708                 r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
 709                 r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
 710                 r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
 711
 712                 ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
 713                 r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
 714                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
 715                 if (r300->radeon.radeonScreen->kernel_mm)
 716                         r300->hw.r500fp.emit = emit_r500fp_atom;
 717
 718                 ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
 719                 r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
 720                         cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
 721                 if (r300->radeon.radeonScreen->kernel_mm)
 722                         r300->hw.r500fp_const.emit = emit_r500fp_atom;
 723         } else {
 724                 ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
 725                 r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
 726                 r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
 727
 728                 ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
 729                 r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
 730
 731                 ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
 732                 r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
 733                 ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
 734                 r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
 735                 ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
 736                 r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
 737                 ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
 738                 r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
 739                 ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
 740                 r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
 741         }
 742         ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
 743         r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
 744         ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
 745         r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
 746         ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
 747         r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
 748         ALLOC_STATE(fg_depth_src, always, 2, 0);
 749         r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
 750         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 751         r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
 752         ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
 753         r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
 754         ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
 755         r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 756         if (is_r500) {
 757                 ALLOC_STATE(blend_color, always, 3, 0);
 758                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
 759         } else {
 760                 ALLOC_STATE(blend_color, always, 2, 0);
 761                 r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
 762         }
 763         ALLOC_STATE(rop, always, 2, 0);
 764         r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
 765         ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
 766         r300->hw.cb.emit = &emit_cb_offset_atom;
 767         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 768         r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
 769         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 770         r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
 771         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) {
 772                 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
 773         } else {
 774                 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
 775         }
 776         r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
 777         ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
 778         r300->hw.zs.cmd[R300_ZS_CMD_0] =
 779             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
 780         if (is_r500) {
 781                 if (r300->radeon.radeonScreen->kernel_mm)
 782                         ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0);
 783                 else
 784                         ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0);
 785                 r300->hw.zsb.cmd[R300_ZSB_CMD_0] =
 786                         cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1);
 787         }
 788
 789         ALLOC_STATE(zstencil_format, always, 5, 0);
 790         r300->hw.zstencil_format.cmd[0] =
 791             cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
 792         r300->hw.zstencil_format.emit = emit_zstencil_format;
 793
 794         ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
 795         r300->hw.zb.emit = emit_zb_offset;
 796         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 797         r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
 798         ALLOC_STATE(zb_zmask, always, 3, 0);
 799         r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
 800         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 801         r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
 802         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 803         r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
 804
 805         /* VPU only on TCL */
 806         if (has_tcl) {
 807                 int i;
 808                 ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
 809                 r300->hw.vpi.cmd[0] =
 810                         cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
 811                 if (r300->radeon.radeonScreen->kernel_mm)
 812                         r300->hw.vpi.emit = emit_vpu_state;
 813
 814                 if (is_r500) {
 815                         ALLOC_STATE(vpp, vpp, R300_VPP_CMDSIZE, 0);
 816                         r300->hw.vpp.cmd[0] =
 817                                 cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
 818                         if (r300->radeon.radeonScreen->kernel_mm)
 819                                 r300->hw.vpp.emit = emit_vpp_state;
 820
 821                         ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 822                         r300->hw.vps.cmd[0] =
 823                                 cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
 824                         if (r300->radeon.radeonScreen->kernel_mm)
 825                                 r300->hw.vps.emit = emit_vpu_state;
 826
 827                         for (i = 0; i < 6; i++) {
 828                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 829                                 r300->hw.vpucp[i].cmd[0] =
 830                                         cmdvpu(r300->radeon.radeonScreen,
 831                                                         R500_PVS_UCP_START + i, 1);
 832                                 if (r300->radeon.radeonScreen->kernel_mm)
 833                                         r300->hw.vpucp[i].emit = emit_vpu_state;
 834                         }
 835                 } else {
 836                         ALLOC_STATE(vpp, vpp, R300_VPP_CMDSIZE, 0);
 837                         r300->hw.vpp.cmd[0] =
 838                                 cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
 839                         if (r300->radeon.radeonScreen->kernel_mm)
 840                                 r300->hw.vpp.emit = emit_vpp_state;
 841
 842                         ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
 843                         r300->hw.vps.cmd[0] =
 844                                 cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
 845                         if (r300->radeon.radeonScreen->kernel_mm)
 846                                 r300->hw.vps.emit = emit_vpu_state;
 847
 848                         for (i = 0; i < 6; i++) {
 849                                 ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
 850                                 r300->hw.vpucp[i].cmd[0] =
 851                                         cmdvpu(r300->radeon.radeonScreen,
 852                                                         R300_PVS_UCP_START + i, 1);
 853                                 if (r300->radeon.radeonScreen->kernel_mm)
 854                                         r300->hw.vpucp[i].emit = emit_vpu_state;
 855                         }
 856                 }
 857         }
 858
 859         /* Textures */
 860         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 861         r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
 862             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
 863
 864         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 865         r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
 866             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
 867
 868         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 869         r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
 870
 871         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 872         r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
 873             cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
 874
 875         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 876         r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
 877
 878         ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
 879         r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
 880             cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
 881         r300->hw.tex.offset.emit = &emit_tex_offsets;
 882
 883         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 884         r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
 885             cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
 886
 887         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 888         r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
 889             cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
 890
 891         radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE);
 892         if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 893                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1);
 894                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL;
 895         } else {
 896                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1);
 897                 r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL;
 898         }
 899         r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1);
 900         r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0;
 901
 902         r300->radeon.hw.is_dirty = GL_TRUE;
 903         r300->radeon.hw.all_dirty = GL_TRUE;
 904
 905         rcommonInitCmdBuf(&r300->radeon);
 906 }