2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Keith Whitwell <keith@tungstengraphics.com>
35 * \author Nicolai Haehnle <prefect_@gmx.net>
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "main/imports.h"
43 #include "main/extensions.h"
44 #include "main/bufferobj.h"
45 #include "main/texobj.h"
47 #include "swrast/swrast.h"
48 #include "swrast_setup/swrast_setup.h"
52 #include "tnl/t_pipeline.h"
54 #include "drivers/common/driverfuncs.h"
55 #include "drivers/common/meta.h"
57 #include "r300_context.h"
58 #include "radeon_span.h"
59 #include "r300_blit.h"
60 #include "r300_cmdbuf.h"
61 #include "r300_state.h"
63 #include "r300_emit.h"
64 #include "r300_render.h"
65 #include "r300_swtcl.h"
66 #include "radeon_bocs_wrapper.h"
67 #include "radeon_buffer_objects.h"
68 #include "radeon_queryobj.h"
71 #include "xmlpool.h" /* for symbolic values of enum-type options */
73 #define need_GL_VERSION_2_0
74 #define need_GL_ARB_occlusion_query
75 #define need_GL_ARB_point_parameters
76 #define need_GL_ARB_vertex_program
77 #define need_GL_EXT_blend_equation_separate
78 #define need_GL_EXT_blend_func_separate
79 #define need_GL_EXT_blend_minmax
80 #define need_GL_EXT_framebuffer_blit
81 #define need_GL_EXT_framebuffer_object
82 #define need_GL_EXT_fog_coord
83 #define need_GL_EXT_gpu_program_parameters
84 #define need_GL_EXT_provoking_vertex
85 #define need_GL_EXT_secondary_color
86 #define need_GL_EXT_stencil_two_side
87 #define need_GL_ATI_separate_stencil
88 #define need_GL_NV_vertex_program
90 #include "main/remap_helper.h"
92 static const struct dri_extension card_extensions
[] = {
94 {"GL_ARB_depth_texture", NULL
},
95 {"GL_ARB_fragment_program", NULL
},
96 {"GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions
},
97 {"GL_ARB_multitexture", NULL
},
98 {"GL_ARB_point_parameters", GL_ARB_point_parameters_functions
},
99 {"GL_ARB_shadow", NULL
},
100 {"GL_ARB_shadow_ambient", NULL
},
101 {"GL_ARB_texture_border_clamp", NULL
},
102 {"GL_ARB_texture_cube_map", NULL
},
103 {"GL_ARB_texture_env_add", NULL
},
104 {"GL_ARB_texture_env_combine", NULL
},
105 {"GL_ARB_texture_env_crossbar", NULL
},
106 {"GL_ARB_texture_env_dot3", NULL
},
107 {"GL_ARB_texture_mirrored_repeat", NULL
},
108 {"GL_ARB_vertex_program", GL_ARB_vertex_program_functions
},
109 {"GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions
},
110 {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions
},
111 {"GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions
},
112 {"GL_EXT_blend_subtract", NULL
},
113 {"GL_EXT_fog_coord", GL_EXT_fog_coord_functions
},
114 {"GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions
},
115 {"GL_EXT_provoking_vertex", GL_EXT_provoking_vertex_functions
},
116 {"GL_EXT_secondary_color", GL_EXT_secondary_color_functions
},
117 {"GL_EXT_shadow_funcs", NULL
},
118 {"GL_EXT_stencil_two_side", GL_EXT_stencil_two_side_functions
},
119 {"GL_EXT_stencil_wrap", NULL
},
120 {"GL_EXT_texture_edge_clamp", NULL
},
121 {"GL_EXT_texture_env_combine", NULL
},
122 {"GL_EXT_texture_env_dot3", NULL
},
123 {"GL_EXT_texture_filter_anisotropic", NULL
},
124 {"GL_EXT_texture_lod_bias", NULL
},
125 {"GL_EXT_texture_mirror_clamp", NULL
},
126 {"GL_EXT_texture_rectangle", NULL
},
127 {"GL_EXT_texture_sRGB", NULL
},
128 {"GL_EXT_vertex_array_bgra", NULL
},
129 {"GL_ATI_separate_stencil", GL_ATI_separate_stencil_functions
},
130 {"GL_ATI_texture_env_combine3", NULL
},
131 {"GL_ATI_texture_mirror_once", NULL
},
132 {"GL_MESA_pack_invert", NULL
},
133 {"GL_MESA_ycbcr_texture", NULL
},
134 {"GL_MESAX_texture_float", NULL
},
135 {"GL_NV_blend_square", NULL
},
136 {"GL_NV_vertex_program", GL_NV_vertex_program_functions
},
137 {"GL_SGIS_generate_mipmap", NULL
},
143 static const struct dri_extension mm_extensions
[] = {
144 { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions
},
145 { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions
},
150 * The GL 2.0 functions are needed to make display lists work with
151 * functions added by GL_ATI_separate_stencil.
153 static const struct dri_extension gl_20_extension
[] = {
154 {"GL_VERSION_2_0", GL_VERSION_2_0_functions
},
157 static const struct tnl_pipeline_stage
*r300_pipeline
[] = {
158 /* Catch any t&l fallbacks
160 &_tnl_vertex_transform_stage
,
161 &_tnl_normal_transform_stage
,
162 &_tnl_lighting_stage
,
163 &_tnl_fog_coordinate_stage
,
165 &_tnl_texture_transform_stage
,
166 &_tnl_point_attenuation_stage
,
167 &_tnl_vertex_program_stage
,
172 static void r300_get_lock(radeonContextPtr rmesa
)
174 drm_radeon_sarea_t
*sarea
= rmesa
->sarea
;
176 if (sarea
->ctx_owner
!= rmesa
->dri
.hwContext
) {
177 sarea
->ctx_owner
= rmesa
->dri
.hwContext
;
178 if (!rmesa
->radeonScreen
->kernel_mm
)
179 radeon_bo_legacy_texture_age(rmesa
->radeonScreen
->bom
);
183 static void r300_vtbl_emit_cs_header(struct radeon_cs
*cs
, radeonContextPtr rmesa
)
185 /* please flush pipe do all pending work */
186 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
187 R300_SC_SCREENDOOR
, 1));
188 radeon_cs_write_dword(cs
, 0x0);
189 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
190 R300_SC_SCREENDOOR
, 1));
191 radeon_cs_write_dword(cs
, 0x00FFFFFF);
192 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
194 radeon_cs_write_dword(cs
, 0x0);
195 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
197 radeon_cs_write_dword(cs
, 0x0);
198 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
200 radeon_cs_write_dword(cs
, 0x0);
201 radeon_cs_write_dword(cs
, cmdwait(rmesa
->radeonScreen
, R300_WAIT_3D
));
202 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
203 R300_RB3D_DSTCACHE_CTLSTAT
, 1));
204 radeon_cs_write_dword(cs
, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
205 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
206 R300_ZB_ZCACHE_CTLSTAT
, 1));
207 radeon_cs_write_dword(cs
, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
);
208 radeon_cs_write_dword(cs
, cmdwait(rmesa
->radeonScreen
,
209 R300_WAIT_3D
| R300_WAIT_3D_CLEAN
));
212 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon
)
214 BATCH_LOCALS(radeon
);
216 cp_wait(radeon
, R300_WAIT_3D
| R300_WAIT_3D_CLEAN
);
217 BEGIN_BATCH_NO_AUTOSTATE(2);
218 OUT_BATCH_REGVAL(R300_TX_INVALTAGS
, R300_TX_FLUSH
);
223 static void r300_fallback(GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
225 r300ContextPtr r300
= R300_CONTEXT(ctx
);
227 r300
->radeon
.Fallback
|= bit
;
229 r300
->radeon
.Fallback
&= ~bit
;
231 r300SwitchFallback(ctx
, R300_FALLBACK_RADEON_COMMON
, mode
);
234 static void r300_emit_query_finish(radeonContextPtr radeon
)
236 r300ContextPtr r300
= (r300ContextPtr
)radeon
;
237 struct radeon_query_object
*query
= radeon
->query
.current
;
238 BATCH_LOCALS(radeon
);
240 BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300
->radeon
.radeonScreen
->num_gb_pipes
+ 2);
241 switch (r300
->radeon
.radeonScreen
->num_gb_pipes
) {
243 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_3
);
244 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
245 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
247 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_2
);
248 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
249 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
251 if (r300
->radeon
.radeonScreen
->chip_family
<= CHIP_FAMILY_RV380
) {
252 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_3
);
254 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_1
);
256 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
257 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
260 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_0
);
261 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
262 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
265 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
267 query
->curr_offset
+= r300
->radeon
.radeonScreen
->num_gb_pipes
* sizeof(uint32_t);
268 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
269 query
->emitted_begin
= GL_FALSE
;
272 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon
)
274 BATCH_LOCALS(radeon
);
275 struct radeon_query_object
*query
= radeon
->query
.current
;
277 BEGIN_BATCH_NO_AUTOSTATE(8);
278 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
279 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
280 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
281 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
284 query
->curr_offset
+= sizeof(uint32_t);
285 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
286 query
->emitted_begin
= GL_FALSE
;
289 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon
)
291 BATCH_LOCALS(radeon
);
292 struct radeon_query_object
*query
= radeon
->query
.current
;
294 BEGIN_BATCH_NO_AUTOSTATE(14);
295 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
296 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
297 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
298 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
299 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
300 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
301 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
304 query
->curr_offset
+= 2 * sizeof(uint32_t);
305 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
306 query
->emitted_begin
= GL_FALSE
;
309 static void r300_init_vtbl(radeonContextPtr radeon
)
311 radeon
->vtbl
.get_lock
= r300_get_lock
;
312 radeon
->vtbl
.update_viewport_offset
= r300UpdateViewportOffset
;
313 radeon
->vtbl
.emit_cs_header
= r300_vtbl_emit_cs_header
;
314 radeon
->vtbl
.swtcl_flush
= r300_swtcl_flush
;
315 radeon
->vtbl
.pre_emit_atoms
= r300_vtbl_pre_emit_atoms
;
316 radeon
->vtbl
.fallback
= r300_fallback
;
317 if (radeon
->radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) {
318 if (radeon
->radeonScreen
->num_z_pipes
== 2)
319 radeon
->vtbl
.emit_query_finish
= rv530_emit_query_finish_double_z
;
321 radeon
->vtbl
.emit_query_finish
= rv530_emit_query_finish_single_z
;
323 radeon
->vtbl
.emit_query_finish
= r300_emit_query_finish
;
325 radeon
->vtbl
.check_blit
= r300_check_blit
;
326 radeon
->vtbl
.blit
= r300_blit
;
329 static void r300InitConstValues(GLcontext
*ctx
, radeonScreenPtr screen
)
331 r300ContextPtr r300
= R300_CONTEXT(ctx
);
333 ctx
->Const
.MaxTextureImageUnits
=
334 driQueryOptioni(&r300
->radeon
.optionCache
, "texture_image_units");
335 ctx
->Const
.MaxTextureCoordUnits
=
336 driQueryOptioni(&r300
->radeon
.optionCache
, "texture_coord_units");
337 ctx
->Const
.MaxTextureUnits
= MIN2(ctx
->Const
.MaxTextureImageUnits
,
338 ctx
->Const
.MaxTextureCoordUnits
);
339 ctx
->Const
.MaxCombinedTextureImageUnits
=
340 ctx
->Const
.MaxVertexTextureImageUnits
+
341 ctx
->Const
.MaxTextureImageUnits
;
344 ctx
->Const
.MaxTextureMaxAnisotropy
= 16.0;
345 ctx
->Const
.MaxTextureLodBias
= 16.0;
347 if (screen
->chip_family
>= CHIP_FAMILY_RV515
) {
348 ctx
->Const
.MaxTextureLevels
= 13;
349 ctx
->Const
.MaxCubeTextureLevels
= 13;
350 ctx
->Const
.MaxTextureRectSize
= 4096;
351 ctx
->Const
.MaxRenderbufferSize
= 4096;
354 ctx
->Const
.MaxTextureLevels
= 12;
355 ctx
->Const
.MaxCubeTextureLevels
= 12;
356 ctx
->Const
.MaxTextureRectSize
= 2048;
357 ctx
->Const
.MaxRenderbufferSize
= 2048;
360 ctx
->Const
.MinPointSize
= 1.0;
361 ctx
->Const
.MinPointSizeAA
= 1.0;
362 ctx
->Const
.MaxPointSize
= R300_POINTSIZE_MAX
;
363 ctx
->Const
.MaxPointSizeAA
= R300_POINTSIZE_MAX
;
365 ctx
->Const
.MinLineWidth
= 1.0;
366 ctx
->Const
.MinLineWidthAA
= 1.0;
367 ctx
->Const
.MaxLineWidth
= R300_LINESIZE_MAX
;
368 ctx
->Const
.MaxLineWidthAA
= R300_LINESIZE_MAX
;
370 ctx
->Const
.MaxDrawBuffers
= 1;
371 ctx
->Const
.MaxColorAttachments
= 1;
373 /* currently bogus data */
374 if (r300
->options
.hw_tcl_enabled
) {
375 ctx
->Const
.VertexProgram
.MaxNativeInstructions
= VSF_MAX_FRAGMENT_LENGTH
/ 4;
376 ctx
->Const
.VertexProgram
.MaxNativeAluInstructions
= VSF_MAX_FRAGMENT_LENGTH
/ 4;
377 ctx
->Const
.VertexProgram
.MaxNativeAttribs
= 16; /* r420 */
378 ctx
->Const
.VertexProgram
.MaxNativeTemps
= 32;
379 ctx
->Const
.VertexProgram
.MaxNativeParameters
= 256; /* r420 */
380 ctx
->Const
.VertexProgram
.MaxNativeAddressRegs
= 1;
383 if (screen
->chip_family
>= CHIP_FAMILY_RV515
) {
384 ctx
->Const
.FragmentProgram
.MaxNativeTemps
= R500_PFS_NUM_TEMP_REGS
;
385 ctx
->Const
.FragmentProgram
.MaxNativeAttribs
= 11; /* copy i915... */
387 /* The hardware limits are higher than this,
388 * but the non-KMS DRM interface artificially limits us
389 * to this many instructions.
391 * We could of course work around it in the KMS path,
392 * but it would be a mess, so it seems wiser
393 * to leave it as is. Going forward, the Gallium driver
394 * will not be subject to these limitations.
396 ctx
->Const
.FragmentProgram
.MaxNativeParameters
= 255;
397 ctx
->Const
.FragmentProgram
.MaxNativeAluInstructions
= 255;
398 ctx
->Const
.FragmentProgram
.MaxNativeTexInstructions
= 255;
399 ctx
->Const
.FragmentProgram
.MaxNativeInstructions
= 255;
400 ctx
->Const
.FragmentProgram
.MaxNativeTexIndirections
= 255;
401 ctx
->Const
.FragmentProgram
.MaxNativeAddressRegs
= 0;
403 ctx
->Const
.FragmentProgram
.MaxNativeTemps
= R300_PFS_NUM_TEMP_REGS
;
404 ctx
->Const
.FragmentProgram
.MaxNativeAttribs
= 11; /* copy i915... */
405 ctx
->Const
.FragmentProgram
.MaxNativeParameters
= R300_PFS_NUM_CONST_REGS
;
406 ctx
->Const
.FragmentProgram
.MaxNativeAluInstructions
= R300_PFS_MAX_ALU_INST
;
407 ctx
->Const
.FragmentProgram
.MaxNativeTexInstructions
= R300_PFS_MAX_TEX_INST
;
408 ctx
->Const
.FragmentProgram
.MaxNativeInstructions
= R300_PFS_MAX_ALU_INST
+ R300_PFS_MAX_TEX_INST
;
409 ctx
->Const
.FragmentProgram
.MaxNativeTexIndirections
= R300_PFS_MAX_TEX_INDIRECT
;
410 ctx
->Const
.FragmentProgram
.MaxNativeAddressRegs
= 0;
415 static void r300ParseOptions(r300ContextPtr r300
, radeonScreenPtr screen
)
417 struct r300_options options
= { 0 };
419 driParseConfigFiles(&r300
->radeon
.optionCache
, &screen
->optionCache
,
420 screen
->driScreen
->myNum
, "r300");
422 r300
->radeon
.initialMaxAnisotropy
= driQueryOptionf(&r300
->radeon
.optionCache
, "def_max_anisotropy");
424 options
.stencil_two_side_disabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "disable_stencil_two_side");
425 options
.s3tc_force_enabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "force_s3tc_enable");
426 options
.s3tc_force_disabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "disable_s3tc");
428 if (!(screen
->chip_flags
& RADEON_CHIPSET_TCL
) || driQueryOptioni(&r300
->radeon
.optionCache
, "tcl_mode") == DRI_CONF_TCL_SW
)
429 options
.hw_tcl_enabled
= 0;
431 options
.hw_tcl_enabled
= 1;
433 options
.conformance_mode
= !driQueryOptionb(&r300
->radeon
.optionCache
, "disable_lowimpact_fallback");
435 r300
->options
= options
;
438 static void r300InitGLExtensions(GLcontext
*ctx
)
440 r300ContextPtr r300
= R300_CONTEXT(ctx
);
442 driInitExtensions(ctx
, card_extensions
, GL_TRUE
);
443 if (r300
->radeon
.radeonScreen
->kernel_mm
)
444 driInitExtensions(ctx
, mm_extensions
, GL_FALSE
);
446 if (r300
->options
.stencil_two_side_disabled
)
447 _mesa_disable_extension(ctx
, "GL_EXT_stencil_two_side");
449 if (r300
->options
.s3tc_force_disabled
) {
450 _mesa_disable_extension(ctx
, "GL_EXT_texture_compression_s3tc");
451 } else if (ctx
->Mesa_DXTn
|| r300
->options
.s3tc_force_enabled
) {
452 _mesa_enable_extension(ctx
, "GL_EXT_texture_compression_s3tc");
453 _mesa_enable_extension(ctx
, "GL_S3_s3tc");
456 if (!r300
->radeon
.radeonScreen
->drmSupportsOcclusionQueries
) {
457 _mesa_disable_extension(ctx
, "GL_ARB_occlusion_query");
459 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV350
)
460 _mesa_enable_extension(ctx
, "GL_ARB_half_float_vertex");
462 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
463 _mesa_enable_extension(ctx
, "GL_EXT_packed_depth_stencil");
466 static void r300InitIoctlFuncs(struct dd_function_table
*functions
)
468 functions
->Clear
= _mesa_meta_Clear
;
469 functions
->Finish
= radeonFinish
;
470 functions
->Flush
= radeonFlush
;
473 /* Create the device specific rendering context.
475 GLboolean
r300CreateContext(const __GLcontextModes
* glVisual
,
476 __DRIcontext
* driContextPriv
,
477 void *sharedContextPrivate
)
479 __DRIscreen
*sPriv
= driContextPriv
->driScreenPriv
;
480 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
481 struct dd_function_table functions
;
486 assert(driContextPriv
);
489 r300
= (r300ContextPtr
) CALLOC(sizeof(*r300
));
493 r300ParseOptions(r300
, screen
);
495 r300
->radeon
.radeonScreen
= screen
;
496 r300_init_vtbl(&r300
->radeon
);
498 _mesa_init_driver_functions(&functions
);
499 r300InitIoctlFuncs(&functions
);
500 r300InitStateFuncs(&functions
);
501 r300InitTextureFuncs(&r300
->radeon
, &functions
);
502 r300InitShaderFuncs(&functions
);
503 radeonInitQueryObjFunctions(&functions
);
504 radeonInitBufferObjectFuncs(&functions
);
506 if (!radeonInitContext(&r300
->radeon
, &functions
,
507 glVisual
, driContextPriv
,
508 sharedContextPrivate
)) {
513 ctx
= r300
->radeon
.glCtx
;
516 if (r300
->options
.hw_tcl_enabled
)
517 ctx
->VertexProgram
._MaintainTnlProgram
= GL_TRUE
;
519 ctx
->FragmentProgram
._MaintainTexEnvProgram
= GL_TRUE
;
521 r300InitConstValues(ctx
, screen
);
523 _mesa_set_mvp_with_dp4( ctx
, GL_TRUE
);
525 /* Initialize the software rasterizer and helper modules.
527 _swrast_CreateContext(ctx
);
528 _vbo_CreateContext(ctx
);
529 _tnl_CreateContext(ctx
);
530 _swsetup_CreateContext(ctx
);
531 _swsetup_Wakeup(ctx
);
533 /* Install the customized pipeline:
535 _tnl_destroy_pipeline(ctx
);
536 _tnl_install_pipeline(ctx
, r300_pipeline
);
537 TNL_CONTEXT(ctx
)->Driver
.RunPipeline
= _tnl_run_pipeline
;
539 /* Configure swrast and TNL to match hardware characteristics:
541 _swrast_allow_pixel_fog(ctx
, GL_FALSE
);
542 _swrast_allow_vertex_fog(ctx
, GL_TRUE
);
543 _tnl_allow_pixel_fog(ctx
, GL_FALSE
);
544 _tnl_allow_vertex_fog(ctx
, GL_TRUE
);
546 if (r300
->options
.hw_tcl_enabled
) {
552 r300_blit_init(r300
);
553 radeon_fbo_init(&r300
->radeon
);
554 radeonInitSpanFuncs( ctx
);
555 r300InitCmdBuf(r300
);
557 r300InitShaderFunctions(r300
);
559 r300InitGLExtensions(ctx
);