src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/extensions.h"
  44 #include "main/bufferobj.h"
  45 #include "main/texobj.h"
  46
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "vbo/vbo.h"
  50
  51 #include "tnl/tnl.h"
  52 #include "tnl/t_pipeline.h"
  53
  54 #include "drivers/common/driverfuncs.h"
  55 #include "drivers/common/meta.h"
  56
  57 #include "r300_context.h"
  58 #include "radeon_span.h"
  59 #include "r300_blit.h"
  60 #include "r300_cmdbuf.h"
  61 #include "r300_state.h"
  62 #include "r300_tex.h"
  63 #include "r300_emit.h"
  64 #include "r300_render.h"
  65 #include "r300_swtcl.h"
  66 #include "radeon_bocs_wrapper.h"
  67 #include "radeon_buffer_objects.h"
  68 #include "radeon_queryobj.h"
  69
  70 #include "utils.h"
  71 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  72
  73 #define need_GL_VERSION_2_0
  74 #define need_GL_ARB_occlusion_query
  75 #define need_GL_ARB_point_parameters
  76 #define need_GL_ARB_vertex_program
  77 #define need_GL_EXT_blend_equation_separate
  78 #define need_GL_EXT_blend_func_separate
  79 #define need_GL_EXT_blend_minmax
  80 #define need_GL_EXT_framebuffer_blit
  81 #define need_GL_EXT_framebuffer_object
  82 #define need_GL_EXT_fog_coord
  83 #define need_GL_EXT_gpu_program_parameters
  84 #define need_GL_EXT_provoking_vertex
  85 #define need_GL_EXT_secondary_color
  86 #define need_GL_EXT_stencil_two_side
  87 #define need_GL_ATI_separate_stencil
  88 #define need_GL_NV_vertex_program
  89 #define need_GL_OES_EGL_image
  90
  91 #include "main/remap_helper.h"
  92
  93 static const struct dri_extension card_extensions[] = {
  94   /* *INDENT-OFF* */
  95   {"GL_ARB_depth_texture",              NULL},
  96   {"GL_ARB_fragment_program",           NULL},
  97   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  98   {"GL_ARB_multitexture",               NULL},
  99   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
 100   {"GL_ARB_shadow",                     NULL},
 101   {"GL_ARB_shadow_ambient",             NULL},
 102   {"GL_ARB_texture_border_clamp",       NULL},
 103   {"GL_ARB_texture_cube_map",           NULL},
 104   {"GL_ARB_texture_env_add",            NULL},
 105   {"GL_ARB_texture_env_combine",        NULL},
 106   {"GL_ARB_texture_env_crossbar",       NULL},
 107   {"GL_ARB_texture_env_dot3",           NULL},
 108   {"GL_ARB_texture_mirrored_repeat",    NULL},
 109   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 110   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 111   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 112   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 113   {"GL_EXT_blend_subtract",             NULL},
 114   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 115   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 116   {"GL_EXT_provoking_vertex",           GL_EXT_provoking_vertex_functions },
 117   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 118   {"GL_EXT_shadow_funcs",               NULL},
 119   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 120   {"GL_EXT_stencil_wrap",               NULL},
 121   {"GL_EXT_texture_edge_clamp",         NULL},
 122   {"GL_EXT_texture_env_combine",        NULL},
 123   {"GL_EXT_texture_env_dot3",           NULL},
 124   {"GL_EXT_texture_filter_anisotropic", NULL},
 125   {"GL_EXT_texture_lod_bias",           NULL},
 126   {"GL_EXT_texture_mirror_clamp",       NULL},
 127   {"GL_EXT_texture_rectangle",          NULL},
 128   {"GL_EXT_texture_sRGB",               NULL},
 129   {"GL_EXT_vertex_array_bgra",          NULL},
 130   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 131   {"GL_ATI_texture_env_combine3",       NULL},
 132   {"GL_ATI_texture_mirror_once",        NULL},
 133   {"GL_MESA_pack_invert",               NULL},
 134   {"GL_MESA_ycbcr_texture",             NULL},
 135   {"GL_MESAX_texture_float",            NULL},
 136   {"GL_NV_blend_square",                NULL},
 137   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 138 #if FEATURE_OES_EGL_image
 139   {"GL_OES_EGL_image",                  GL_OES_EGL_image_functions },
 140 #endif
 141   {NULL,                                NULL}
 142   /* *INDENT-ON* */
 143 };
 144
 145
 146 static const struct dri_extension mm_extensions[] = {
 147   { "GL_EXT_framebuffer_blit",  GL_EXT_framebuffer_blit_functions },
 148   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 149   { NULL, NULL }
 150 };
 151
 152 /**
 153  * The GL 2.0 functions are needed to make display lists work with
 154  * functions added by GL_ATI_separate_stencil.
 155  */
 156 static const struct dri_extension gl_20_extension[] = {
 157   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 158 };
 159
 160 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 161         /* Catch any t&l fallbacks
 162          */
 163         &_tnl_vertex_transform_stage,
 164         &_tnl_normal_transform_stage,
 165         &_tnl_lighting_stage,
 166         &_tnl_fog_coordinate_stage,
 167         &_tnl_texgen_stage,
 168         &_tnl_texture_transform_stage,
 169         &_tnl_point_attenuation_stage,
 170         &_tnl_vertex_program_stage,
 171         &_tnl_render_stage,
 172         0,
 173 };
 174
 175 static void r300_get_lock(radeonContextPtr rmesa)
 176 {
 177         drm_radeon_sarea_t *sarea = rmesa->sarea;
 178
 179         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 180                 sarea->ctx_owner = rmesa->dri.hwContext;
 181                 if (!rmesa->radeonScreen->kernel_mm)
 182                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 183         }
 184 }
 185
 186 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 187 {
 188     /* please flush pipe do all pending work */
 189     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 190                                   R300_SC_SCREENDOOR, 1));
 191     radeon_cs_write_dword(cs, 0x0);
 192     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 193                                   R300_SC_SCREENDOOR, 1));
 194     radeon_cs_write_dword(cs, 0x00FFFFFF);
 195     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 196                                   R300_SC_HYPERZ, 1));
 197     radeon_cs_write_dword(cs, 0x0);
 198     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 199                                   R300_US_CONFIG, 1));
 200     radeon_cs_write_dword(cs, 0x0);
 201     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 202                                   R300_ZB_CNTL, 1));
 203     radeon_cs_write_dword(cs, 0x0);
 204     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 205     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 206                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 207     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 208     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 209                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 210     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 211     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 212                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 213 }
 214
 215 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 216 {
 217         BATCH_LOCALS(radeon);
 218
 219         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 220         BEGIN_BATCH_NO_AUTOSTATE(2);
 221         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 222         END_BATCH();
 223         end_3d(radeon);
 224 }
 225
 226 static void r300_fallback(struct gl_context *ctx, GLuint bit, GLboolean mode)
 227 {
 228         r300ContextPtr r300 = R300_CONTEXT(ctx);
 229         if (mode)
 230                 r300->radeon.Fallback |= bit;
 231         else
 232                 r300->radeon.Fallback &= ~bit;
 233
 234         r300SwitchFallback(ctx, R300_FALLBACK_RADEON_COMMON, mode);
 235 }
 236
 237 static void r300_emit_query_finish(radeonContextPtr radeon)
 238 {
 239         r300ContextPtr r300 = (r300ContextPtr)radeon;
 240         struct radeon_query_object *query = radeon->query.current;
 241         BATCH_LOCALS(radeon);
 242
 243         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
 244         switch (r300->radeon.radeonScreen->num_gb_pipes) {
 245         case 4:
 246                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 247                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 248                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 249         case 3:
 250                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 251                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 252                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 253         case 2:
 254                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 255                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 256                 } else {
 257                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 258                 }
 259                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 260                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 261         case 1:
 262         default:
 263                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 264                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 265                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 266                 break;
 267         }
 268         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 269         END_BATCH();
 270         query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
 271         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 272         query->emitted_begin = GL_FALSE;
 273 }
 274
 275 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 276 {
 277         BATCH_LOCALS(radeon);
 278         struct radeon_query_object *query = radeon->query.current;
 279
 280         BEGIN_BATCH_NO_AUTOSTATE(8);
 281         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 282         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 283         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 284         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 285         END_BATCH();
 286
 287         query->curr_offset += sizeof(uint32_t);
 288         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 289         query->emitted_begin = GL_FALSE;
 290 }
 291
 292 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 293 {
 294         BATCH_LOCALS(radeon);
 295         struct radeon_query_object *query = radeon->query.current;
 296
 297         BEGIN_BATCH_NO_AUTOSTATE(14);
 298         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 299         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 300         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 301         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 302         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 303         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 304         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 305         END_BATCH();
 306
 307         query->curr_offset += 2 * sizeof(uint32_t);
 308         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 309         query->emitted_begin = GL_FALSE;
 310 }
 311
 312 static void r300_init_vtbl(radeonContextPtr radeon)
 313 {
 314         radeon->vtbl.get_lock = r300_get_lock;
 315         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 316         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 317         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 318         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 319         radeon->vtbl.fallback = r300_fallback;
 320         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 321                 if (radeon->radeonScreen->num_z_pipes == 2)
 322                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
 323                 else
 324                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 325         } else
 326                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 327
 328         radeon->vtbl.check_blit = r300_check_blit;
 329         radeon->vtbl.blit = r300_blit;
 330
 331         if (radeon->radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 332                 radeon->vtbl.is_format_renderable = r500IsFormatRenderable;
 333         } else {
 334                 radeon->vtbl.is_format_renderable = r300IsFormatRenderable;
 335         }
 336 }
 337
 338 static void r300InitConstValues(struct gl_context *ctx, radeonScreenPtr screen)
 339 {
 340         r300ContextPtr r300 = R300_CONTEXT(ctx);
 341
 342         ctx->Const.MaxTextureImageUnits =
 343             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 344         ctx->Const.MaxTextureCoordUnits =
 345             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 346         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 347                  ctx->Const.MaxTextureCoordUnits);
 348         ctx->Const.MaxCombinedTextureImageUnits =
 349                 ctx->Const.MaxVertexTextureImageUnits +
 350                 ctx->Const.MaxTextureImageUnits;
 351
 352
 353         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 354         ctx->Const.MaxTextureLodBias = 16.0;
 355
 356         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 357                 ctx->Const.MaxTextureLevels = 13;
 358                 ctx->Const.MaxCubeTextureLevels = 13;
 359                 ctx->Const.MaxTextureRectSize = 4096;
 360                 ctx->Const.MaxRenderbufferSize = 4096;
 361         }
 362         else {
 363                 ctx->Const.MaxTextureLevels = 12;
 364                 ctx->Const.MaxCubeTextureLevels = 12;
 365                 ctx->Const.MaxTextureRectSize = 2048;
 366                 ctx->Const.MaxRenderbufferSize = 2048;
 367         }
 368
 369         ctx->Const.MinPointSize = 1.0;
 370         ctx->Const.MinPointSizeAA = 1.0;
 371         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 372         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 373
 374         ctx->Const.MinLineWidth = 1.0;
 375         ctx->Const.MinLineWidthAA = 1.0;
 376         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 377         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 378
 379         ctx->Const.MaxDrawBuffers = 1;
 380         ctx->Const.MaxColorAttachments = 1;
 381
 382         if (r300->options.hw_tcl_enabled) {
 383                 ctx->Const.VertexProgram.MaxNativeInstructions = 255;
 384                 ctx->Const.VertexProgram.MaxNativeAluInstructions = 255;
 385                 ctx->Const.VertexProgram.MaxNativeAttribs = 16;
 386                 ctx->Const.VertexProgram.MaxNativeTemps = 32;
 387                 ctx->Const.VertexProgram.MaxNativeParameters = 256;
 388                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 389         }
 390
 391         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 392                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 393                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 394
 395                 /* The hardware limits are higher than this,
 396                  * but the non-KMS DRM interface artificially limits us
 397                  * to this many instructions.
 398                  *
 399                  * We could of course work around it in the KMS path,
 400                  * but it would be a mess, so it seems wiser
 401                  * to leave it as is. Going forward, the Gallium driver
 402                  * will not be subject to these limitations.
 403                  */
 404                 ctx->Const.FragmentProgram.MaxNativeParameters = 255;
 405                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255;
 406                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255;
 407                 ctx->Const.FragmentProgram.MaxNativeInstructions = 255;
 408                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255;
 409                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 410         } else {
 411                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 412                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 413                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 414                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 415                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 416                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 417                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 418                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 419         }
 420
 421 }
 422
 423 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 424 {
 425         struct r300_options options = { 0 };
 426
 427         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 428                             screen->driScreen->myNum, "r300");
 429
 430         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 431
 432         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 433         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 434         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 435
 436         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 437                 options.hw_tcl_enabled = 0;
 438         else
 439                 options.hw_tcl_enabled = 1;
 440
 441         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 442
 443         r300->options = options;
 444 }
 445
 446 static void r300InitGLExtensions(struct gl_context *ctx)
 447 {
 448         r300ContextPtr r300 = R300_CONTEXT(ctx);
 449
 450         driInitExtensions(ctx, card_extensions, GL_TRUE);
 451         if (r300->radeon.radeonScreen->kernel_mm)
 452                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 453
 454         if (r300->options.stencil_two_side_disabled)
 455                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 456
 457         if (r300->options.s3tc_force_disabled) {
 458                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 459         } else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) {
 460                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 461                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 462         }
 463
 464         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 465                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 466         }
 467         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_R420)
 468                 _mesa_enable_extension(ctx, "GL_ARB_half_float_vertex");
 469
 470         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 471                 _mesa_enable_extension(ctx, "GL_EXT_packed_depth_stencil");
 472 }
 473
 474 static void r300InitIoctlFuncs(struct dd_function_table *functions)
 475 {
 476         functions->Clear = _mesa_meta_Clear;
 477         functions->Finish = radeonFinish;
 478         functions->Flush = radeonFlush;
 479 }
 480
 481 /* Create the device specific rendering context.
 482  */
 483 GLboolean r300CreateContext(gl_api api,
 484                             const struct gl_config * glVisual,
 485                             __DRIcontext * driContextPriv,
 486                             void *sharedContextPrivate)
 487 {
 488         __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 489         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 490         struct dd_function_table functions;
 491         r300ContextPtr r300;
 492         struct gl_context *ctx;
 493
 494         assert(glVisual);
 495         assert(driContextPriv);
 496         assert(screen);
 497
 498         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 499         if (!r300)
 500                 return GL_FALSE;
 501
 502         r300ParseOptions(r300, screen);
 503
 504         r300->radeon.radeonScreen = screen;
 505         r300_init_vtbl(&r300->radeon);
 506
 507         _mesa_init_driver_functions(&functions);
 508         r300InitIoctlFuncs(&functions);
 509         r300InitStateFuncs(&r300->radeon, &functions);
 510         r300InitTextureFuncs(&r300->radeon, &functions);
 511         r300InitShaderFuncs(&functions);
 512         radeonInitQueryObjFunctions(&functions);
 513         radeonInitBufferObjectFuncs(&functions);
 514
 515         if (!radeonInitContext(&r300->radeon, &functions,
 516                                glVisual, driContextPriv,
 517                                sharedContextPrivate)) {
 518                 FREE(r300);
 519                 return GL_FALSE;
 520         }
 521
 522         ctx = r300->radeon.glCtx;
 523
 524         r300->fallback = 0;
 525         if (r300->options.hw_tcl_enabled)
 526                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 527
 528         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 529
 530         r300InitConstValues(ctx, screen);
 531
 532         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 533
 534         /* Initialize the software rasterizer and helper modules.
 535          */
 536         _swrast_CreateContext(ctx);
 537         _vbo_CreateContext(ctx);
 538         _tnl_CreateContext(ctx);
 539         _swsetup_CreateContext(ctx);
 540         _swsetup_Wakeup(ctx);
 541
 542         /* Install the customized pipeline:
 543          */
 544         _tnl_destroy_pipeline(ctx);
 545         _tnl_install_pipeline(ctx, r300_pipeline);
 546         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 547
 548         /* Configure swrast and TNL to match hardware characteristics:
 549          */
 550         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 551         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 552         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 553         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 554
 555         if (r300->options.hw_tcl_enabled) {
 556                 r300InitDraw(ctx);
 557         } else {
 558                 r300InitSwtcl(ctx);
 559         }
 560
 561         r300_blit_init(r300);
 562         radeon_fbo_init(&r300->radeon);
 563         radeonInitSpanFuncs( ctx );
 564         r300InitCmdBuf(r300);
 565         r300InitState(r300);
 566         r300InitShaderFunctions(r300);
 567
 568         r300InitGLExtensions(ctx);
 569
 570         return GL_TRUE;
 571 }
 572