2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Keith Whitwell <keith@tungstengraphics.com>
35 * \author Nicolai Haehnle <prefect_@gmx.net>
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "main/imports.h"
43 #include "main/matrix.h"
44 #include "main/extensions.h"
45 #include "main/state.h"
46 #include "main/bufferobj.h"
47 #include "main/texobj.h"
49 #include "swrast/swrast.h"
50 #include "swrast_setup/swrast_setup.h"
54 #include "tnl/t_pipeline.h"
55 #include "tnl/t_vp_build.h"
57 #include "drivers/common/driverfuncs.h"
58 #include "drivers/common/meta.h"
60 #include "r300_context.h"
61 #include "radeon_context.h"
62 #include "radeon_span.h"
63 #include "r300_blit.h"
64 #include "r300_cmdbuf.h"
65 #include "r300_state.h"
67 #include "r300_emit.h"
68 #include "r300_swtcl.h"
69 #include "radeon_bocs_wrapper.h"
70 #include "radeon_buffer_objects.h"
71 #include "radeon_queryobj.h"
75 #include "xmlpool.h" /* for symbolic values of enum-type options */
77 #define need_GL_VERSION_2_0
78 #define need_GL_ARB_occlusion_query
79 #define need_GL_ARB_point_parameters
80 #define need_GL_ARB_vertex_program
81 #define need_GL_EXT_blend_equation_separate
82 #define need_GL_EXT_blend_func_separate
83 #define need_GL_EXT_blend_minmax
84 #define need_GL_EXT_framebuffer_blit
85 #define need_GL_EXT_framebuffer_object
86 #define need_GL_EXT_fog_coord
87 #define need_GL_EXT_gpu_program_parameters
88 #define need_GL_EXT_provoking_vertex
89 #define need_GL_EXT_secondary_color
90 #define need_GL_EXT_stencil_two_side
91 #define need_GL_ATI_separate_stencil
92 #define need_GL_NV_vertex_program
94 #include "main/remap_helper.h"
96 static const struct dri_extension card_extensions
[] = {
98 {"GL_ARB_depth_texture", NULL
},
99 {"GL_ARB_fragment_program", NULL
},
100 {"GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions
},
101 {"GL_ARB_multitexture", NULL
},
102 {"GL_ARB_point_parameters", GL_ARB_point_parameters_functions
},
103 {"GL_ARB_shadow", NULL
},
104 {"GL_ARB_shadow_ambient", NULL
},
105 {"GL_ARB_texture_border_clamp", NULL
},
106 {"GL_ARB_texture_cube_map", NULL
},
107 {"GL_ARB_texture_env_add", NULL
},
108 {"GL_ARB_texture_env_combine", NULL
},
109 {"GL_ARB_texture_env_crossbar", NULL
},
110 {"GL_ARB_texture_env_dot3", NULL
},
111 {"GL_ARB_texture_mirrored_repeat", NULL
},
112 {"GL_ARB_vertex_program", GL_ARB_vertex_program_functions
},
113 {"GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions
},
114 {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions
},
115 {"GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions
},
116 {"GL_EXT_blend_subtract", NULL
},
117 {"GL_EXT_packed_depth_stencil", NULL
},
118 {"GL_EXT_fog_coord", GL_EXT_fog_coord_functions
},
119 {"GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions
},
120 {"GL_EXT_provoking_vertex", GL_EXT_provoking_vertex_functions
},
121 {"GL_EXT_secondary_color", GL_EXT_secondary_color_functions
},
122 {"GL_EXT_shadow_funcs", NULL
},
123 {"GL_EXT_stencil_two_side", GL_EXT_stencil_two_side_functions
},
124 {"GL_EXT_stencil_wrap", NULL
},
125 {"GL_EXT_texture_edge_clamp", NULL
},
126 {"GL_EXT_texture_env_combine", NULL
},
127 {"GL_EXT_texture_env_dot3", NULL
},
128 {"GL_EXT_texture_filter_anisotropic", NULL
},
129 {"GL_EXT_texture_lod_bias", NULL
},
130 {"GL_EXT_texture_mirror_clamp", NULL
},
131 {"GL_EXT_texture_rectangle", NULL
},
132 {"GL_EXT_texture_sRGB", NULL
},
133 {"GL_EXT_vertex_array_bgra", NULL
},
134 {"GL_ATI_separate_stencil", GL_ATI_separate_stencil_functions
},
135 {"GL_ATI_texture_env_combine3", NULL
},
136 {"GL_ATI_texture_mirror_once", NULL
},
137 {"GL_MESA_pack_invert", NULL
},
138 {"GL_MESA_ycbcr_texture", NULL
},
139 {"GL_MESAX_texture_float", NULL
},
140 {"GL_NV_blend_square", NULL
},
141 {"GL_NV_vertex_program", GL_NV_vertex_program_functions
},
142 {"GL_SGIS_generate_mipmap", NULL
},
148 static const struct dri_extension mm_extensions
[] = {
149 { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions
},
150 { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions
},
155 * The GL 2.0 functions are needed to make display lists work with
156 * functions added by GL_ATI_separate_stencil.
158 static const struct dri_extension gl_20_extension
[] = {
159 {"GL_VERSION_2_0", GL_VERSION_2_0_functions
},
162 static const struct tnl_pipeline_stage
*r300_pipeline
[] = {
163 /* Catch any t&l fallbacks
165 &_tnl_vertex_transform_stage
,
166 &_tnl_normal_transform_stage
,
167 &_tnl_lighting_stage
,
168 &_tnl_fog_coordinate_stage
,
170 &_tnl_texture_transform_stage
,
171 &_tnl_point_attenuation_stage
,
172 &_tnl_vertex_program_stage
,
177 static void r300_get_lock(radeonContextPtr rmesa
)
179 drm_radeon_sarea_t
*sarea
= rmesa
->sarea
;
181 if (sarea
->ctx_owner
!= rmesa
->dri
.hwContext
) {
182 sarea
->ctx_owner
= rmesa
->dri
.hwContext
;
183 if (!rmesa
->radeonScreen
->kernel_mm
)
184 radeon_bo_legacy_texture_age(rmesa
->radeonScreen
->bom
);
188 static void r300_vtbl_emit_cs_header(struct radeon_cs
*cs
, radeonContextPtr rmesa
)
190 /* please flush pipe do all pending work */
191 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
192 R300_SC_SCREENDOOR
, 1));
193 radeon_cs_write_dword(cs
, 0x0);
194 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
195 R300_SC_SCREENDOOR
, 1));
196 radeon_cs_write_dword(cs
, 0x00FFFFFF);
197 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
199 radeon_cs_write_dword(cs
, 0x0);
200 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
202 radeon_cs_write_dword(cs
, 0x0);
203 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
205 radeon_cs_write_dword(cs
, 0x0);
206 radeon_cs_write_dword(cs
, cmdwait(rmesa
->radeonScreen
, R300_WAIT_3D
));
207 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
208 R300_RB3D_DSTCACHE_CTLSTAT
, 1));
209 radeon_cs_write_dword(cs
, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
210 radeon_cs_write_dword(cs
, cmdpacket0(rmesa
->radeonScreen
,
211 R300_ZB_ZCACHE_CTLSTAT
, 1));
212 radeon_cs_write_dword(cs
, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
);
213 radeon_cs_write_dword(cs
, cmdwait(rmesa
->radeonScreen
,
214 R300_WAIT_3D
| R300_WAIT_3D_CLEAN
));
217 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon
)
219 BATCH_LOCALS(radeon
);
221 cp_wait(radeon
, R300_WAIT_3D
| R300_WAIT_3D_CLEAN
);
222 BEGIN_BATCH_NO_AUTOSTATE(2);
223 OUT_BATCH_REGVAL(R300_TX_INVALTAGS
, R300_TX_FLUSH
);
228 static void r300_fallback(GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
230 r300ContextPtr r300
= R300_CONTEXT(ctx
);
232 r300
->radeon
.Fallback
|= bit
;
234 r300
->radeon
.Fallback
&= ~bit
;
237 static void r300_emit_query_finish(radeonContextPtr radeon
)
239 r300ContextPtr r300
= (r300ContextPtr
)radeon
;
240 struct radeon_query_object
*query
= radeon
->query
.current
;
241 BATCH_LOCALS(radeon
);
243 BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300
->radeon
.radeonScreen
->num_gb_pipes
+ 2);
244 switch (r300
->radeon
.radeonScreen
->num_gb_pipes
) {
246 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_3
);
247 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
248 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
250 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_2
);
251 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
252 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
254 if (r300
->radeon
.radeonScreen
->chip_family
<= CHIP_FAMILY_RV380
) {
255 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_3
);
257 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_1
);
259 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
260 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
263 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_0
);
264 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
265 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
268 OUT_BATCH_REGVAL(R300_SU_REG_DEST
, R300_RASTER_PIPE_SELECT_ALL
);
270 query
->curr_offset
+= r300
->radeon
.radeonScreen
->num_gb_pipes
* sizeof(uint32_t);
271 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
272 query
->emitted_begin
= GL_FALSE
;
275 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon
)
277 BATCH_LOCALS(radeon
);
278 struct radeon_query_object
*query
= radeon
->query
.current
;
280 BEGIN_BATCH_NO_AUTOSTATE(8);
281 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
282 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
283 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
284 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
287 query
->curr_offset
+= sizeof(uint32_t);
288 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
289 query
->emitted_begin
= GL_FALSE
;
292 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon
)
294 BATCH_LOCALS(radeon
);
295 struct radeon_query_object
*query
= radeon
->query
.current
;
297 BEGIN_BATCH_NO_AUTOSTATE(14);
298 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_0
);
299 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
300 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
301 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_1
);
302 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR
, 1);
303 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
+ sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT
, 0);
304 OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST
, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL
);
307 query
->curr_offset
+= 2 * sizeof(uint32_t);
308 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
309 query
->emitted_begin
= GL_FALSE
;
312 static void r300_init_vtbl(radeonContextPtr radeon
)
314 radeon
->vtbl
.get_lock
= r300_get_lock
;
315 radeon
->vtbl
.update_viewport_offset
= r300UpdateViewportOffset
;
316 radeon
->vtbl
.emit_cs_header
= r300_vtbl_emit_cs_header
;
317 radeon
->vtbl
.swtcl_flush
= r300_swtcl_flush
;
318 radeon
->vtbl
.pre_emit_atoms
= r300_vtbl_pre_emit_atoms
;
319 radeon
->vtbl
.fallback
= r300_fallback
;
320 if (radeon
->radeonScreen
->chip_family
== CHIP_FAMILY_RV530
) {
321 if (radeon
->radeonScreen
->num_z_pipes
== 2)
322 radeon
->vtbl
.emit_query_finish
= rv530_emit_query_finish_double_z
;
324 radeon
->vtbl
.emit_query_finish
= rv530_emit_query_finish_single_z
;
326 radeon
->vtbl
.emit_query_finish
= r300_emit_query_finish
;
328 radeon
->vtbl
.blit
= r300_blit
;
331 static void r300InitConstValues(GLcontext
*ctx
, radeonScreenPtr screen
)
333 r300ContextPtr r300
= R300_CONTEXT(ctx
);
335 ctx
->Const
.MaxTextureImageUnits
=
336 driQueryOptioni(&r300
->radeon
.optionCache
, "texture_image_units");
337 ctx
->Const
.MaxTextureCoordUnits
=
338 driQueryOptioni(&r300
->radeon
.optionCache
, "texture_coord_units");
339 ctx
->Const
.MaxTextureUnits
= MIN2(ctx
->Const
.MaxTextureImageUnits
,
340 ctx
->Const
.MaxTextureCoordUnits
);
342 ctx
->Const
.MaxTextureMaxAnisotropy
= 16.0;
343 ctx
->Const
.MaxTextureLodBias
= 16.0;
345 if (screen
->chip_family
>= CHIP_FAMILY_RV515
) {
346 ctx
->Const
.MaxTextureLevels
= 13;
347 ctx
->Const
.MaxCubeTextureLevels
= 13;
348 ctx
->Const
.MaxTextureRectSize
= 4096;
351 ctx
->Const
.MaxTextureLevels
= 12;
352 ctx
->Const
.MaxCubeTextureLevels
= 12;
353 ctx
->Const
.MaxTextureRectSize
= 2048;
356 ctx
->Const
.MinPointSize
= 1.0;
357 ctx
->Const
.MinPointSizeAA
= 1.0;
358 ctx
->Const
.MaxPointSize
= R300_POINTSIZE_MAX
;
359 ctx
->Const
.MaxPointSizeAA
= R300_POINTSIZE_MAX
;
361 ctx
->Const
.MinLineWidth
= 1.0;
362 ctx
->Const
.MinLineWidthAA
= 1.0;
363 ctx
->Const
.MaxLineWidth
= R300_LINESIZE_MAX
;
364 ctx
->Const
.MaxLineWidthAA
= R300_LINESIZE_MAX
;
366 ctx
->Const
.MaxDrawBuffers
= 1;
368 /* currently bogus data */
369 if (r300
->options
.hw_tcl_enabled
) {
370 ctx
->Const
.VertexProgram
.MaxNativeInstructions
= VSF_MAX_FRAGMENT_LENGTH
/ 4;
371 ctx
->Const
.VertexProgram
.MaxNativeAluInstructions
= VSF_MAX_FRAGMENT_LENGTH
/ 4;
372 ctx
->Const
.VertexProgram
.MaxNativeAttribs
= 16; /* r420 */
373 ctx
->Const
.VertexProgram
.MaxNativeTemps
= 32;
374 ctx
->Const
.VertexProgram
.MaxNativeParameters
= 256; /* r420 */
375 ctx
->Const
.VertexProgram
.MaxNativeAddressRegs
= 1;
378 if (screen
->chip_family
>= CHIP_FAMILY_RV515
) {
379 ctx
->Const
.FragmentProgram
.MaxNativeTemps
= R500_PFS_NUM_TEMP_REGS
;
380 ctx
->Const
.FragmentProgram
.MaxNativeAttribs
= 11; /* copy i915... */
382 /* The hardware limits are higher than this,
383 * but the non-KMS DRM interface artificially limits us
384 * to this many instructions.
386 * We could of course work around it in the KMS path,
387 * but it would be a mess, so it seems wiser
388 * to leave it as is. Going forward, the Gallium driver
389 * will not be subject to these limitations.
391 ctx
->Const
.FragmentProgram
.MaxNativeParameters
= 255;
392 ctx
->Const
.FragmentProgram
.MaxNativeAluInstructions
= 255;
393 ctx
->Const
.FragmentProgram
.MaxNativeTexInstructions
= 255;
394 ctx
->Const
.FragmentProgram
.MaxNativeInstructions
= 255;
395 ctx
->Const
.FragmentProgram
.MaxNativeTexIndirections
= 255;
396 ctx
->Const
.FragmentProgram
.MaxNativeAddressRegs
= 0;
398 ctx
->Const
.FragmentProgram
.MaxNativeTemps
= R300_PFS_NUM_TEMP_REGS
;
399 ctx
->Const
.FragmentProgram
.MaxNativeAttribs
= 11; /* copy i915... */
400 ctx
->Const
.FragmentProgram
.MaxNativeParameters
= R300_PFS_NUM_CONST_REGS
;
401 ctx
->Const
.FragmentProgram
.MaxNativeAluInstructions
= R300_PFS_MAX_ALU_INST
;
402 ctx
->Const
.FragmentProgram
.MaxNativeTexInstructions
= R300_PFS_MAX_TEX_INST
;
403 ctx
->Const
.FragmentProgram
.MaxNativeInstructions
= R300_PFS_MAX_ALU_INST
+ R300_PFS_MAX_TEX_INST
;
404 ctx
->Const
.FragmentProgram
.MaxNativeTexIndirections
= R300_PFS_MAX_TEX_INDIRECT
;
405 ctx
->Const
.FragmentProgram
.MaxNativeAddressRegs
= 0;
410 static void r300ParseOptions(r300ContextPtr r300
, radeonScreenPtr screen
)
412 struct r300_options options
= { 0 };
414 driParseConfigFiles(&r300
->radeon
.optionCache
, &screen
->optionCache
,
415 screen
->driScreen
->myNum
, "r300");
417 r300
->radeon
.initialMaxAnisotropy
= driQueryOptionf(&r300
->radeon
.optionCache
, "def_max_anisotropy");
419 options
.stencil_two_side_disabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "disable_stencil_two_side");
420 options
.s3tc_force_enabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "force_s3tc_enable");
421 options
.s3tc_force_disabled
= driQueryOptionb(&r300
->radeon
.optionCache
, "disable_s3tc");
423 if (!(screen
->chip_flags
& RADEON_CHIPSET_TCL
) || driQueryOptioni(&r300
->radeon
.optionCache
, "tcl_mode") == DRI_CONF_TCL_SW
)
424 options
.hw_tcl_enabled
= 0;
426 options
.hw_tcl_enabled
= 1;
428 options
.conformance_mode
= !driQueryOptionb(&r300
->radeon
.optionCache
, "disable_lowimpact_fallback");
430 r300
->options
= options
;
433 static void r300InitGLExtensions(GLcontext
*ctx
)
435 r300ContextPtr r300
= R300_CONTEXT(ctx
);
437 driInitExtensions(ctx
, card_extensions
, GL_TRUE
);
438 if (r300
->radeon
.radeonScreen
->kernel_mm
)
439 driInitExtensions(ctx
, mm_extensions
, GL_FALSE
);
441 if (r300
->options
.stencil_two_side_disabled
)
442 _mesa_disable_extension(ctx
, "GL_EXT_stencil_two_side");
444 if (r300
->options
.s3tc_force_disabled
) {
445 _mesa_disable_extension(ctx
, "GL_EXT_texture_compression_s3tc");
446 } else if (ctx
->Mesa_DXTn
|| r300
->options
.s3tc_force_enabled
) {
447 _mesa_enable_extension(ctx
, "GL_EXT_texture_compression_s3tc");
448 _mesa_enable_extension(ctx
, "GL_S3_s3tc");
451 if (!r300
->radeon
.radeonScreen
->drmSupportsOcclusionQueries
) {
452 _mesa_disable_extension(ctx
, "GL_ARB_occlusion_query");
456 static void r300InitIoctlFuncs(struct dd_function_table
*functions
)
458 functions
->Clear
= _mesa_meta_Clear
;
459 functions
->Finish
= radeonFinish
;
460 functions
->Flush
= radeonFlush
;
463 /* Create the device specific rendering context.
465 GLboolean
r300CreateContext(const __GLcontextModes
* glVisual
,
466 __DRIcontext
* driContextPriv
,
467 void *sharedContextPrivate
)
469 __DRIscreen
*sPriv
= driContextPriv
->driScreenPriv
;
470 radeonScreenPtr screen
= (radeonScreenPtr
) (sPriv
->private);
471 struct dd_function_table functions
;
476 assert(driContextPriv
);
479 r300
= (r300ContextPtr
) CALLOC(sizeof(*r300
));
483 r300ParseOptions(r300
, screen
);
485 r300
->radeon
.radeonScreen
= screen
;
486 r300_init_vtbl(&r300
->radeon
);
488 _mesa_init_driver_functions(&functions
);
489 r300InitIoctlFuncs(&functions
);
490 r300InitStateFuncs(&functions
);
491 r300InitTextureFuncs(&r300
->radeon
, &functions
);
492 r300InitShaderFuncs(&functions
);
493 radeonInitQueryObjFunctions(&functions
);
494 radeonInitBufferObjectFuncs(&functions
);
496 if (!radeonInitContext(&r300
->radeon
, &functions
,
497 glVisual
, driContextPriv
,
498 sharedContextPrivate
)) {
503 ctx
= r300
->radeon
.glCtx
;
506 if (r300
->options
.hw_tcl_enabled
)
507 ctx
->VertexProgram
._MaintainTnlProgram
= GL_TRUE
;
509 ctx
->FragmentProgram
._MaintainTexEnvProgram
= GL_TRUE
;
511 r300InitConstValues(ctx
, screen
);
513 _mesa_set_mvp_with_dp4( ctx
, GL_TRUE
);
515 /* Initialize the software rasterizer and helper modules.
517 _swrast_CreateContext(ctx
);
518 _vbo_CreateContext(ctx
);
519 _tnl_CreateContext(ctx
);
520 _swsetup_CreateContext(ctx
);
521 _swsetup_Wakeup(ctx
);
523 /* Install the customized pipeline:
525 _tnl_destroy_pipeline(ctx
);
526 _tnl_install_pipeline(ctx
, r300_pipeline
);
527 TNL_CONTEXT(ctx
)->Driver
.RunPipeline
= _tnl_run_pipeline
;
529 /* Configure swrast and TNL to match hardware characteristics:
531 _swrast_allow_pixel_fog(ctx
, GL_FALSE
);
532 _swrast_allow_vertex_fog(ctx
, GL_TRUE
);
533 _tnl_allow_pixel_fog(ctx
, GL_FALSE
);
534 _tnl_allow_vertex_fog(ctx
, GL_TRUE
);
536 if (r300
->options
.hw_tcl_enabled
) {
542 r300_blit_init(r300
);
543 radeon_fbo_init(&r300
->radeon
);
544 radeonInitSpanFuncs( ctx
);
545 r300InitCmdBuf(r300
);
547 r300InitShaderFunctions(r300
);
549 r300InitGLExtensions(ctx
);