src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include "main/glheader.h"
  39 #include "main/api_arrayelt.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "main/imports.h"
  43 #include "main/extensions.h"
  44 #include "main/bufferobj.h"
  45 #include "main/texobj.h"
  46
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "vbo/vbo.h"
  50
  51 #include "tnl/tnl.h"
  52 #include "tnl/t_pipeline.h"
  53
  54 #include "drivers/common/driverfuncs.h"
  55 #include "drivers/common/meta.h"
  56
  57 #include "r300_context.h"
  58 #include "radeon_span.h"
  59 #include "r300_blit.h"
  60 #include "r300_cmdbuf.h"
  61 #include "r300_state.h"
  62 #include "r300_tex.h"
  63 #include "r300_emit.h"
  64 #include "r300_swtcl.h"
  65 #include "radeon_bocs_wrapper.h"
  66 #include "radeon_buffer_objects.h"
  67 #include "radeon_queryobj.h"
  68
  69 #include "utils.h"
  70 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  71
  72 #define need_GL_VERSION_2_0
  73 #define need_GL_ARB_occlusion_query
  74 #define need_GL_ARB_point_parameters
  75 #define need_GL_ARB_vertex_program
  76 #define need_GL_EXT_blend_equation_separate
  77 #define need_GL_EXT_blend_func_separate
  78 #define need_GL_EXT_blend_minmax
  79 #define need_GL_EXT_framebuffer_blit
  80 #define need_GL_EXT_framebuffer_object
  81 #define need_GL_EXT_fog_coord
  82 #define need_GL_EXT_gpu_program_parameters
  83 #define need_GL_EXT_provoking_vertex
  84 #define need_GL_EXT_secondary_color
  85 #define need_GL_EXT_stencil_two_side
  86 #define need_GL_ATI_separate_stencil
  87 #define need_GL_NV_vertex_program
  88
  89 #include "main/remap_helper.h"
  90
  91 static const struct dri_extension card_extensions[] = {
  92   /* *INDENT-OFF* */
  93   {"GL_ARB_depth_texture",              NULL},
  94   {"GL_ARB_fragment_program",           NULL},
  95   {"GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  96   {"GL_ARB_multitexture",               NULL},
  97   {"GL_ARB_point_parameters",           GL_ARB_point_parameters_functions},
  98   {"GL_ARB_shadow",                     NULL},
  99   {"GL_ARB_shadow_ambient",             NULL},
 100   {"GL_ARB_texture_border_clamp",       NULL},
 101   {"GL_ARB_texture_cube_map",           NULL},
 102   {"GL_ARB_texture_env_add",            NULL},
 103   {"GL_ARB_texture_env_combine",        NULL},
 104   {"GL_ARB_texture_env_crossbar",       NULL},
 105   {"GL_ARB_texture_env_dot3",           NULL},
 106   {"GL_ARB_texture_mirrored_repeat",    NULL},
 107   {"GL_ARB_vertex_program",             GL_ARB_vertex_program_functions},
 108   {"GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions},
 109   {"GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions},
 110   {"GL_EXT_blend_minmax",               GL_EXT_blend_minmax_functions},
 111   {"GL_EXT_blend_subtract",             NULL},
 112   {"GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
 113   {"GL_EXT_gpu_program_parameters",     GL_EXT_gpu_program_parameters_functions},
 114   {"GL_EXT_provoking_vertex",           GL_EXT_provoking_vertex_functions },
 115   {"GL_EXT_secondary_color",            GL_EXT_secondary_color_functions},
 116   {"GL_EXT_shadow_funcs",               NULL},
 117   {"GL_EXT_stencil_two_side",           GL_EXT_stencil_two_side_functions},
 118   {"GL_EXT_stencil_wrap",               NULL},
 119   {"GL_EXT_texture_edge_clamp",         NULL},
 120   {"GL_EXT_texture_env_combine",        NULL},
 121   {"GL_EXT_texture_env_dot3",           NULL},
 122   {"GL_EXT_texture_filter_anisotropic", NULL},
 123   {"GL_EXT_texture_lod_bias",           NULL},
 124   {"GL_EXT_texture_mirror_clamp",       NULL},
 125   {"GL_EXT_texture_rectangle",          NULL},
 126   {"GL_EXT_texture_sRGB",               NULL},
 127   {"GL_EXT_vertex_array_bgra",          NULL},
 128   {"GL_ATI_separate_stencil",           GL_ATI_separate_stencil_functions},
 129   {"GL_ATI_texture_env_combine3",       NULL},
 130   {"GL_ATI_texture_mirror_once",        NULL},
 131   {"GL_MESA_pack_invert",               NULL},
 132   {"GL_MESA_ycbcr_texture",             NULL},
 133   {"GL_MESAX_texture_float",            NULL},
 134   {"GL_NV_blend_square",                NULL},
 135   {"GL_NV_vertex_program",              GL_NV_vertex_program_functions},
 136   {"GL_SGIS_generate_mipmap",           NULL},
 137   {NULL,                                NULL}
 138   /* *INDENT-ON* */
 139 };
 140
 141
 142 static const struct dri_extension mm_extensions[] = {
 143   { "GL_EXT_framebuffer_blit",  GL_EXT_framebuffer_blit_functions },
 144   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 145   { NULL, NULL }
 146 };
 147
 148 /**
 149  * The GL 2.0 functions are needed to make display lists work with
 150  * functions added by GL_ATI_separate_stencil.
 151  */
 152 static const struct dri_extension gl_20_extension[] = {
 153   {"GL_VERSION_2_0",                    GL_VERSION_2_0_functions },
 154 };
 155
 156 static const struct tnl_pipeline_stage *r300_pipeline[] = {
 157         /* Catch any t&l fallbacks
 158          */
 159         &_tnl_vertex_transform_stage,
 160         &_tnl_normal_transform_stage,
 161         &_tnl_lighting_stage,
 162         &_tnl_fog_coordinate_stage,
 163         &_tnl_texgen_stage,
 164         &_tnl_texture_transform_stage,
 165         &_tnl_point_attenuation_stage,
 166         &_tnl_vertex_program_stage,
 167         &_tnl_render_stage,
 168         0,
 169 };
 170
 171 static void r300_get_lock(radeonContextPtr rmesa)
 172 {
 173         drm_radeon_sarea_t *sarea = rmesa->sarea;
 174
 175         if (sarea->ctx_owner != rmesa->dri.hwContext) {
 176                 sarea->ctx_owner = rmesa->dri.hwContext;
 177                 if (!rmesa->radeonScreen->kernel_mm)
 178                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
 179         }
 180 }
 181
 182 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 183 {
 184     /* please flush pipe do all pending work */
 185     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 186                                   R300_SC_SCREENDOOR, 1));
 187     radeon_cs_write_dword(cs, 0x0);
 188     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 189                                   R300_SC_SCREENDOOR, 1));
 190     radeon_cs_write_dword(cs, 0x00FFFFFF);
 191     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 192                                   R300_SC_HYPERZ, 1));
 193     radeon_cs_write_dword(cs, 0x0);
 194     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 195                                   R300_US_CONFIG, 1));
 196     radeon_cs_write_dword(cs, 0x0);
 197     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 198                                   R300_ZB_CNTL, 1));
 199     radeon_cs_write_dword(cs, 0x0);
 200     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 201     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 202                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 203     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 204     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 205                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 206     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 207     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 208                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 209 }
 210
 211 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 212 {
 213         BATCH_LOCALS(radeon);
 214
 215         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 216         BEGIN_BATCH_NO_AUTOSTATE(2);
 217         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 218         END_BATCH();
 219         end_3d(radeon);
 220 }
 221
 222 static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
 223 {
 224         r300ContextPtr r300 = R300_CONTEXT(ctx);
 225         if (mode)
 226                 r300->radeon.Fallback |= bit;
 227         else
 228                 r300->radeon.Fallback &= ~bit;
 229 }
 230
 231 static void r300_emit_query_finish(radeonContextPtr radeon)
 232 {
 233         r300ContextPtr r300 = (r300ContextPtr)radeon;
 234         struct radeon_query_object *query = radeon->query.current;
 235         BATCH_LOCALS(radeon);
 236
 237         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
 238         switch (r300->radeon.radeonScreen->num_gb_pipes) {
 239         case 4:
 240                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 241                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 242                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 243         case 3:
 244                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 245                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 246                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 247         case 2:
 248                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 249                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 250                 } else {
 251                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 252                 }
 253                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 254                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 255         case 1:
 256         default:
 257                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 258                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 259                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 260                 break;
 261         }
 262         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 263         END_BATCH();
 264         query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
 265         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 266         query->emitted_begin = GL_FALSE;
 267 }
 268
 269 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 270 {
 271         BATCH_LOCALS(radeon);
 272         struct radeon_query_object *query = radeon->query.current;
 273
 274         BEGIN_BATCH_NO_AUTOSTATE(8);
 275         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 276         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 277         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 278         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 279         END_BATCH();
 280
 281         query->curr_offset += sizeof(uint32_t);
 282         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 283         query->emitted_begin = GL_FALSE;
 284 }
 285
 286 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 287 {
 288         BATCH_LOCALS(radeon);
 289         struct radeon_query_object *query = radeon->query.current;
 290
 291         BEGIN_BATCH_NO_AUTOSTATE(14);
 292         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 293         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 294         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 295         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 296         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 297         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 298         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 299         END_BATCH();
 300
 301         query->curr_offset += 2 * sizeof(uint32_t);
 302         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 303         query->emitted_begin = GL_FALSE;
 304 }
 305
 306 static void r300_init_vtbl(radeonContextPtr radeon)
 307 {
 308         radeon->vtbl.get_lock = r300_get_lock;
 309         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 310         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 311         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 312         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 313         radeon->vtbl.fallback = r300_fallback;
 314         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 315                 if (radeon->radeonScreen->num_z_pipes == 2)
 316                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
 317                 else
 318                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 319         } else
 320                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 321
 322         radeon->vtbl.check_blit = r300_check_blit;
 323         radeon->vtbl.blit = r300_blit;
 324
 325         if (radeon->radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 326                 radeon->vtbl.is_format_renderable = r500IsFormatRenderable;
 327         } else {
 328                 radeon->vtbl.is_format_renderable = r300IsFormatRenderable;
 329         }
 330 }
 331
 332 static void r300InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
 333 {
 334         r300ContextPtr r300 = R300_CONTEXT(ctx);
 335
 336         ctx->Const.MaxTextureImageUnits =
 337             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 338         ctx->Const.MaxTextureCoordUnits =
 339             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 340         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 341                  ctx->Const.MaxTextureCoordUnits);
 342         ctx->Const.MaxCombinedTextureImageUnits =
 343                 ctx->Const.MaxVertexTextureImageUnits +
 344                 ctx->Const.MaxTextureImageUnits;
 345
 346
 347         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 348         ctx->Const.MaxTextureLodBias = 16.0;
 349
 350         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 351                 ctx->Const.MaxTextureLevels = 13;
 352                 ctx->Const.MaxCubeTextureLevels = 13;
 353                 ctx->Const.MaxTextureRectSize = 4096;
 354                 ctx->Const.MaxRenderbufferSize = 4096;
 355         }
 356         else {
 357                 ctx->Const.MaxTextureLevels = 12;
 358                 ctx->Const.MaxCubeTextureLevels = 12;
 359                 ctx->Const.MaxTextureRectSize = 2048;
 360                 ctx->Const.MaxRenderbufferSize = 2048;
 361         }
 362
 363         ctx->Const.MinPointSize = 1.0;
 364         ctx->Const.MinPointSizeAA = 1.0;
 365         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 366         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 367
 368         ctx->Const.MinLineWidth = 1.0;
 369         ctx->Const.MinLineWidthAA = 1.0;
 370         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 371         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 372
 373         ctx->Const.MaxDrawBuffers = 1;
 374         ctx->Const.MaxColorAttachments = 1;
 375
 376         /* currently bogus data */
 377         if (r300->options.hw_tcl_enabled) {
 378                 ctx->Const.VertexProgram.MaxNativeInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 379                 ctx->Const.VertexProgram.MaxNativeAluInstructions = VSF_MAX_FRAGMENT_LENGTH / 4;
 380                 ctx->Const.VertexProgram.MaxNativeAttribs = 16; /* r420 */
 381                 ctx->Const.VertexProgram.MaxNativeTemps = 32;
 382                 ctx->Const.VertexProgram.MaxNativeParameters = 256;     /* r420 */
 383                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 384         }
 385
 386         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 387                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 388                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 389
 390                 /* The hardware limits are higher than this,
 391                  * but the non-KMS DRM interface artificially limits us
 392                  * to this many instructions.
 393                  *
 394                  * We could of course work around it in the KMS path,
 395                  * but it would be a mess, so it seems wiser
 396                  * to leave it as is. Going forward, the Gallium driver
 397                  * will not be subject to these limitations.
 398                  */
 399                 ctx->Const.FragmentProgram.MaxNativeParameters = 255;
 400                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255;
 401                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255;
 402                 ctx->Const.FragmentProgram.MaxNativeInstructions = 255;
 403                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255;
 404                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 405         } else {
 406                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 407                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 408                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 409                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 410                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 411                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 412                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 413                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 414         }
 415
 416 }
 417
 418 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 419 {
 420         struct r300_options options = { 0 };
 421
 422         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 423                             screen->driScreen->myNum, "r300");
 424
 425         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 426
 427         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 428         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 429         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 430
 431         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 432                 options.hw_tcl_enabled = 0;
 433         else
 434                 options.hw_tcl_enabled = 1;
 435
 436         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 437
 438         r300->options = options;
 439 }
 440
 441 static void r300InitGLExtensions(GLcontext *ctx)
 442 {
 443         r300ContextPtr r300 = R300_CONTEXT(ctx);
 444
 445         driInitExtensions(ctx, card_extensions, GL_TRUE);
 446         if (r300->radeon.radeonScreen->kernel_mm)
 447                 driInitExtensions(ctx, mm_extensions, GL_FALSE);
 448
 449         if (r300->options.stencil_two_side_disabled)
 450                 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
 451
 452         if (r300->options.s3tc_force_disabled) {
 453                 _mesa_disable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 454         } else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) {
 455                 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
 456                 _mesa_enable_extension(ctx, "GL_S3_s3tc");
 457         }
 458
 459         if (!r300->radeon.radeonScreen->drmSupportsOcclusionQueries) {
 460                 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 461         }
 462         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350)
 463                 _mesa_enable_extension(ctx, "GL_ARB_half_float_vertex");
 464
 465         if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
 466                 _mesa_enable_extension(ctx, "GL_EXT_packed_depth_stencil");
 467 }
 468
 469 static void r300InitIoctlFuncs(struct dd_function_table *functions)
 470 {
 471         functions->Clear = _mesa_meta_Clear;
 472         functions->Finish = radeonFinish;
 473         functions->Flush = radeonFlush;
 474 }
 475
 476 /* Create the device specific rendering context.
 477  */
 478 GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 479                             __DRIcontext * driContextPriv,
 480                             void *sharedContextPrivate)
 481 {
 482         __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 483         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 484         struct dd_function_table functions;
 485         r300ContextPtr r300;
 486         GLcontext *ctx;
 487
 488         assert(glVisual);
 489         assert(driContextPriv);
 490         assert(screen);
 491
 492         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 493         if (!r300)
 494                 return GL_FALSE;
 495
 496         r300ParseOptions(r300, screen);
 497
 498         r300->radeon.radeonScreen = screen;
 499         r300_init_vtbl(&r300->radeon);
 500
 501         _mesa_init_driver_functions(&functions);
 502         r300InitIoctlFuncs(&functions);
 503         r300InitStateFuncs(&functions);
 504         r300InitTextureFuncs(&r300->radeon, &functions);
 505         r300InitShaderFuncs(&functions);
 506         radeonInitQueryObjFunctions(&functions);
 507         radeonInitBufferObjectFuncs(&functions);
 508
 509         if (!radeonInitContext(&r300->radeon, &functions,
 510                                glVisual, driContextPriv,
 511                                sharedContextPrivate)) {
 512                 FREE(r300);
 513                 return GL_FALSE;
 514         }
 515
 516         ctx = r300->radeon.glCtx;
 517
 518         r300->fallback = 0;
 519         if (r300->options.hw_tcl_enabled)
 520                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 521
 522         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 523
 524         r300InitConstValues(ctx, screen);
 525
 526         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 527
 528         /* Initialize the software rasterizer and helper modules.
 529          */
 530         _swrast_CreateContext(ctx);
 531         _vbo_CreateContext(ctx);
 532         _tnl_CreateContext(ctx);
 533         _swsetup_CreateContext(ctx);
 534         _swsetup_Wakeup(ctx);
 535
 536         /* Install the customized pipeline:
 537          */
 538         _tnl_destroy_pipeline(ctx);
 539         _tnl_install_pipeline(ctx, r300_pipeline);
 540         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 541
 542         /* Configure swrast and TNL to match hardware characteristics:
 543          */
 544         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 545         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 546         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 547         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 548
 549         if (r300->options.hw_tcl_enabled) {
 550                 r300InitDraw(ctx);
 551         } else {
 552                 r300InitSwtcl(ctx);
 553         }
 554
 555         r300_blit_init(r300);
 556         radeon_fbo_init(&r300->radeon);
 557         radeonInitSpanFuncs( ctx );
 558         r300InitCmdBuf(r300);
 559         r300InitState(r300);
 560         r300InitShaderFunctions(r300);
 561
 562         r300InitGLExtensions(ctx);
 563
 564         return GL_TRUE;
 565 }
 566