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Merge remote branch 'origin/master' into nv50-compiler
[mesa.git] / src / mesa / drivers / dri / r600 / evergreen_chip.c
1 /*
2 * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/imports.h"
28 #include "main/glheader.h"
29 #include "main/simple_list.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "evergreen_chip.h"
35 #include "evergreen_off.h"
36 #include "evergreen_diff.h"
37 #include "evergreen_fragprog.h"
38 #include "evergreen_vertprog.h"
39
40 #include "radeon_mipmap_tree.h"
41
42 void evergreenCreateChip(context_t *context)
43 {
44 EVERGREEN_CHIP_CONTEXT * evergreen =
45 (EVERGREEN_CHIP_CONTEXT*) CALLOC(sizeof(EVERGREEN_CHIP_CONTEXT));
46
47 context->pChip = (void*)evergreen;
48 }
49
50 #define EVERGREEN_ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
51 do { \
52 context->evergreen_atoms.ATOM.cmd_size = (SZ); \
53 context->evergreen_atoms.ATOM.cmd = NULL; \
54 context->evergreen_atoms.ATOM.name = #ATOM; \
55 context->evergreen_atoms.ATOM.idx = 0; \
56 context->evergreen_atoms.ATOM.check = check_##CHK; \
57 context->evergreen_atoms.ATOM.dirty = GL_FALSE; \
58 context->evergreen_atoms.ATOM.emit = (EMIT); \
59 context->radeon.hw.max_state_size += (SZ); \
60 insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \
61 } while (0)
62
63 /*
64 static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ)
65 {
66 radeon->query.queryobj.cmd_size = (SZ);
67 radeon->query.queryobj.cmd = NULL;
68 radeon->query.queryobj.name = "queryobj";
69 radeon->query.queryobj.idx = 0;
70 radeon->query.queryobj.check = check_queryobj;
71 radeon->query.queryobj.dirty = GL_FALSE;
72 radeon->query.queryobj.emit = r700SendQueryBegin;
73 radeon->hw.max_state_size += (SZ);
74 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
75 }
76 */
77
78 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
79 {
80 return atom->cmd_size;
81 }
82
83 static void evergreenSendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
84 {
85 context_t *context = EVERGREEN_CONTEXT(ctx);
86 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
87
88 struct evergreen_vertex_program *vp = context->selected_vp;
89
90 struct radeon_bo *bo = NULL;
91 unsigned int i;
92 unsigned int nBorderSet = 0;
93 BATCH_LOCALS(&context->radeon);
94
95 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
96
97 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
98 if (ctx->Texture.Unit[i]._ReallyEnabled) {
99 radeonTexObj *t = evergreen->textures[i];
100
101 if (t) {
102 /* Tex resource */
103 if (!t->image_override) {
104 bo = t->mt->bo;
105 } else {
106 bo = t->bo;
107 }
108 if (bo)
109 {
110 radeon_bo_unmap(bo);
111
112 r700SyncSurf(context, bo,
113 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
114 0, TC_ACTION_ENA_bit);
115
116 BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
117 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
118
119 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
120 { /* vs texture */
121 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
122 }
123 else
124 {
125 R600_OUT_BATCH(i * EG_FETCH_RESOURCE_STRIDE);
126 }
127
128 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE0);
129 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE1);
130 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE2);
131 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE3);
132 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE4);
133 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE5);
134 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE6);
135 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE7);
136
137 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE2,
138 bo,
139 evergreen->textures[i]->SQ_TEX_RESOURCE2,
140 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
141 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE3,
142 bo,
143 evergreen->textures[i]->SQ_TEX_RESOURCE3,
144 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
145 END_BATCH();
146 COMMIT_BATCH();
147 }
148 /* Tex sampler */
149 BEGIN_BATCH_NO_AUTOSTATE(5);
150 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
151
152 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
153 { /* vs texture */
154 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * 3);
155 }
156 else
157 {
158 R600_OUT_BATCH(i * 3);
159 }
160 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER0);
161 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER1);
162 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER2);
163
164 END_BATCH();
165 COMMIT_BATCH();
166
167 /* Tex border color */
168 if(0 == nBorderSet)
169 {
170 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
171 R600_OUT_BATCH_REGSEQ(EG_TD_PS_BORDER_COLOR_RED, 4);
172 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
173 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
174 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
175 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
176 END_BATCH();
177 COMMIT_BATCH();
178
179 nBorderSet = 1;
180 }
181 }
182 }
183 }
184 }
185
186 static int check_evergreen_tx(GLcontext *ctx, struct radeon_state_atom *atom)
187 {
188 context_t *context = EVERGREEN_CONTEXT(ctx);
189 unsigned int i, count = 0;
190 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
191
192 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
193 if (ctx->Texture.Unit[i]._ReallyEnabled) {
194 radeonTexObj *t = evergreen->textures[i];
195 if (t)
196 count++;
197 }
198 }
199 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
200 return count * 37 + 6;
201 }
202
203 static void evergreenSendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
204 {
205 context_t *context = EVERGREEN_CONTEXT(ctx);
206 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
207 BATCH_LOCALS(&context->radeon);
208 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
209
210 BEGIN_BATCH_NO_AUTOSTATE(19);
211 //6
212 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL, evergreen->evergreen_config.SPI_CONFIG_CNTL.u32All);
213 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL_1, evergreen->evergreen_config.SPI_CONFIG_CNTL_1.u32All);
214 //6
215 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
216 R600_OUT_BATCH(evergreen->evergreen_config.SQ_CONFIG.u32All);
217 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
218 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
219 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All);
220 //7
221 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
222 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All);
223 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All);
224 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
225 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
226 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All);
227
228 END_BATCH();
229
230 COMMIT_BATCH();
231 }
232
233 extern int evergreen_getTypeSize(GLenum type);
234 static void evergreenSetupVTXConstants(GLcontext * ctx,
235 void * pAos,
236 StreamDesc * pStreamDesc)
237 {
238 context_t *context = EVERGREEN_CONTEXT(ctx);
239 struct radeon_aos * paos = (struct radeon_aos *)pAos;
240 unsigned int nVBsize;
241 BATCH_LOCALS(&context->radeon);
242
243 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
244 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
245 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
246 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
247 unsigned int uSQ_VTX_CONSTANT_WORD7_0 = 0;
248
249 if (!paos->bo)
250 return;
251
252 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
253
254 if(0 == pStreamDesc->stride)
255 {
256 nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type);
257 }
258 else
259 {
260 nVBsize = (paos->count - 1) * pStreamDesc->stride
261 + pStreamDesc->size * getTypeSize(pStreamDesc->type);
262 }
263
264 //uSQ_VTX_CONSTANT_WORD0_0
265 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
266
267 //uSQ_VTX_CONSTANT_WORD1_0
268 uSQ_VTX_CONSTANT_WORD1_0 = nVBsize;
269
270 //uSQ_VTX_CONSTANT_WORD2_0
271 SETfield(uSQ_VTX_CONSTANT_WORD2_0,
272 pStreamDesc->stride,
273 SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
274 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
275 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
276 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
277 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); // TODO : trace back api for initial data type, not only GL_FLOAT
278 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); // TODO
279 if(GL_TRUE == pStreamDesc->normalize)
280 {
281 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
282 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
283 }
284 else
285 {
286 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
287 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
288 }
289 if(1 == pStreamDesc->_signed)
290 {
291 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
292 }
293
294 //uSQ_VTX_CONSTANT_WORD3_0
295 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_X,
296 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
297 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
298 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Y,
299 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
300 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
301 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Z,
302 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
303 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
304 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_W,
305 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
306 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
307
308 //uSQ_VTX_CONSTANT_WORD7_0
309 SETfield(uSQ_VTX_CONSTANT_WORD7_0, SQ_TEX_VTX_VALID_BUFFER,
310 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
311
312 BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
313
314 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
315 R600_OUT_BATCH((pStreamDesc->element + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
316 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
317 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
318 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
319 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
320 R600_OUT_BATCH(0);
321 R600_OUT_BATCH(0);
322 R600_OUT_BATCH(0);
323 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD7_0);
324 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
325 paos->bo,
326 uSQ_VTX_CONSTANT_WORD0_0,
327 RADEON_GEM_DOMAIN_GTT, 0, 0);
328 END_BATCH();
329
330 COMMIT_BATCH();
331 }
332
333 static int check_evergreen_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
334 {
335 context_t *context = EVERGREEN_CONTEXT(ctx);
336 int count = context->radeon.tcl.aos_count * 12;
337
338 if (count)
339 count += 6;
340
341 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
342 return count;
343 }
344
345 static void evergreenSendVTX(GLcontext *ctx, struct radeon_state_atom *atom)
346 {
347 context_t *context = EVERGREEN_CONTEXT(ctx);
348 struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *)(context->selected_vp);
349 unsigned int i, j = 0;
350 BATCH_LOCALS(&context->radeon);
351 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
352
353 if (context->radeon.tcl.aos_count == 0)
354 return;
355
356 BEGIN_BATCH_NO_AUTOSTATE(6);
357 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
358 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
359 R600_OUT_BATCH(0);
360
361 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
362 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
363 R600_OUT_BATCH(0);
364 END_BATCH();
365 COMMIT_BATCH();
366
367 for(i=0; i<VERT_ATTRIB_MAX; i++) {
368 if(vp->mesa_program->Base.InputsRead & (1 << i))
369 {
370 evergreenSetupVTXConstants(ctx,
371 (void*)(&context->radeon.tcl.aos[j]),
372 &(context->stream_desc[j]));
373 j++;
374 }
375 }
376 }
377 static void evergreenSendPA(GLcontext *ctx, struct radeon_state_atom *atom)
378 {
379 context_t *context = EVERGREEN_CONTEXT(ctx);
380 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
381 BATCH_LOCALS(&context->radeon);
382 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
383 int id = 0;
384
385 BEGIN_BATCH_NO_AUTOSTATE(3);
386 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
387 END_BATCH();
388
389 BEGIN_BATCH_NO_AUTOSTATE(22);
390 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
391 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All);
392 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_BR.u32All);
393
394 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 12);
395 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_OFFSET.u32All);
396 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All);
397 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_BR.u32All);
398 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_RULE.u32All);
399 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_TL.u32All);
400 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_BR.u32All);
401 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_TL.u32All);
402 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_BR.u32All);
403 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_TL.u32All);
404 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_BR.u32All);
405 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_TL.u32All);
406 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_BR.u32All);
407
408 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
409 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All);
410 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_BR.u32All);
411 END_BATCH();
412
413 BEGIN_BATCH_NO_AUTOSTATE(3);
414 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SC_EDGERULE, evergreen->PA_SC_EDGERULE.u32All);
415 END_BATCH();
416
417
418 BEGIN_BATCH_NO_AUTOSTATE(18);
419 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 4);
420 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
421 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
422 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
423 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
424
425 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
426 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
427 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
428
429 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_VPORT_XSCALE, 6);
430 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XSCALE.u32All);
431 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
432 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YSCALE.u32All);
433 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
434 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
435 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
436 END_BATCH();
437
438
439 for (id = 0; id < EVERGREEN_MAX_UCP; id++) {
440 if (evergreen->ucp[id].enabled) {
441 BEGIN_BATCH_NO_AUTOSTATE(6);
442 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_UCP_0_X + (4 * id), 4);
443 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_X.u32All);
444 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Y.u32All);
445 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Z.u32All);
446 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_W.u32All);
447 END_BATCH();
448 }
449 }
450
451 BEGIN_BATCH_NO_AUTOSTATE(42);
452 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_CLIP_CNTL, 5);
453 R600_OUT_BATCH(evergreen->PA_CL_CLIP_CNTL.u32All);
454 R600_OUT_BATCH(evergreen->PA_SU_SC_MODE_CNTL.u32All);
455 R600_OUT_BATCH(evergreen->PA_CL_VTE_CNTL.u32All);
456 R600_OUT_BATCH(evergreen->PA_CL_VS_OUT_CNTL.u32All);
457 R600_OUT_BATCH(evergreen->PA_CL_NANINF_CNTL.u32All);
458
459 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 3);
460 R600_OUT_BATCH(evergreen->PA_SU_POINT_SIZE.u32All);
461 R600_OUT_BATCH(evergreen->PA_SU_POINT_MINMAX.u32All);
462 R600_OUT_BATCH(evergreen->PA_SU_LINE_CNTL.u32All);
463
464 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
465 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_0.u32All);
466 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_1.u32All);
467
468 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
469 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
470 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_CLAMP.u32All);
471 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
472 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
473 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
474 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
475
476 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
477 R600_OUT_BATCH(evergreen->PA_SC_LINE_CNTL.u32All);
478 R600_OUT_BATCH(evergreen->PA_SC_AA_CONFIG.u32All);
479 R600_OUT_BATCH(evergreen->PA_SU_VTX_CNTL.u32All);
480 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_CLIP_ADJ.u32All);
481 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_DISC_ADJ.u32All);
482 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
483 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_DISC_ADJ.u32All);
484 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_0.u32All);
485 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_1.u32All);
486 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_2.u32All);
487 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_3.u32All);
488 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_4.u32All);
489 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_5.u32All);
490 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_6.u32All);
491 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_7.u32All);
492 R600_OUT_BATCH(evergreen->PA_SC_AA_MASK.u32All);
493
494 END_BATCH();
495
496 COMMIT_BATCH();
497 }
498 static void evergreenSendTP(GLcontext *ctx, struct radeon_state_atom *atom)
499 {
500 /*
501 context_t *context = EVERGREEN_CONTEXT(ctx);
502 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
503 BATCH_LOCALS(&context->radeon);
504 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
505
506 COMMIT_BATCH();
507 */
508 }
509
510 static void evergreenSendPSresource(GLcontext *ctx)
511 {
512 context_t *context = EVERGREEN_CONTEXT(ctx);
513 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
514 struct radeon_bo * pbo;
515
516 struct radeon_bo * pbo_const;
517
518 BATCH_LOCALS(&context->radeon);
519 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
520
521 pbo = (struct radeon_bo *)evergreenGetActiveFpShaderBo(GL_CONTEXT(context));
522
523 if (!pbo)
524 return;
525
526 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
527
528 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
529 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
530 R600_OUT_BATCH(evergreen->ps.SQ_PGM_START_PS.u32All);
531 R600_OUT_BATCH_RELOC(evergreen->ps.SQ_PGM_START_PS.u32All,
532 pbo,
533 evergreen->ps.SQ_PGM_START_PS.u32All,
534 RADEON_GEM_DOMAIN_GTT, 0, 0);
535 END_BATCH();
536
537 BEGIN_BATCH_NO_AUTOSTATE(3);
538 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LOOP_CONST_0, 0x01000FFF);
539 END_BATCH();
540
541 pbo_const = (struct radeon_bo *)(context->fp_Constbo);
542
543 if(NULL != pbo_const)
544 {
545 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
546
547 BEGIN_BATCH_NO_AUTOSTATE(3);
548
549 if(evergreen->ps.num_consts < 4)
550 {
551 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, 1);
552 }
553 else
554 {
555 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, (evergreen->ps.num_consts * 4)/16 );
556 }
557
558 END_BATCH();
559
560 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
561 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_PS_0, 1);
562 R600_OUT_BATCH(context->fp_bo_offset >> 8);
563 R600_OUT_BATCH_RELOC(0,
564 pbo_const,
565 0,
566 RADEON_GEM_DOMAIN_GTT, 0, 0);
567 END_BATCH();
568 }
569
570 COMMIT_BATCH();
571 }
572
573 static void evergreenSendVSresource(GLcontext *ctx, struct radeon_state_atom *atom)
574 {
575 context_t *context = EVERGREEN_CONTEXT(ctx);
576 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
577 struct radeon_bo * pbo;
578
579 struct radeon_bo * pbo_const;
580
581 BATCH_LOCALS(&context->radeon);
582 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
583
584 pbo = (struct radeon_bo *)evergreenGetActiveVpShaderBo(GL_CONTEXT(context));
585
586 if (!pbo)
587 return;
588
589 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
590
591 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
592 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
593 R600_OUT_BATCH(evergreen->vs.SQ_PGM_START_VS.u32All);
594 R600_OUT_BATCH_RELOC(evergreen->vs.SQ_PGM_START_VS.u32All,
595 pbo,
596 evergreen->vs.SQ_PGM_START_VS.u32All,
597 RADEON_GEM_DOMAIN_GTT, 0, 0);
598 END_BATCH();
599
600 BEGIN_BATCH_NO_AUTOSTATE(3);
601 EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + 32*1), 0x0100000F); //consts == 1
602 //EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
603 END_BATCH();
604
605 pbo_const = (struct radeon_bo *)(context->vp_Constbo);
606
607 if(NULL != pbo_const)
608 {
609 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
610
611 BEGIN_BATCH_NO_AUTOSTATE(3);
612
613 if(evergreen->vs.num_consts < 4)
614 {
615 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, 1);
616 }
617 else
618 {
619 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, (evergreen->vs.num_consts * 4)/16 );
620 }
621
622 END_BATCH();
623
624 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
625 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_VS_0, 1);
626 R600_OUT_BATCH(context->vp_bo_offset >> 8);
627 R600_OUT_BATCH_RELOC(0,
628 pbo_const,
629 0,
630 RADEON_GEM_DOMAIN_GTT, 0, 0);
631 END_BATCH();
632 }
633
634 COMMIT_BATCH();
635 }
636
637 static void evergreenSendSQ(GLcontext *ctx, struct radeon_state_atom *atom)
638 {
639 context_t *context = EVERGREEN_CONTEXT(ctx);
640 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
641 BATCH_LOCALS(&context->radeon);
642 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
643
644 evergreenSendPSresource(ctx); //16 entries now
645
646 BEGIN_BATCH_NO_AUTOSTATE(77);
647
648 //34
649 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_VTX_SEMANTIC_0, 32);
650 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_0.u32All); //// // = 0x28380, // SAME
651 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_1.u32All); //// // = 0x28384, // SAME
652 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_2.u32All); //// // = 0x28388, // SAME
653 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_3.u32All); //// // = 0x2838C, // SAME
654 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_4.u32All); //// // = 0x28390, // SAME
655 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_5.u32All); //// // = 0x28394, // SAME
656 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_6.u32All); //// // = 0x28398, // SAME
657 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_7.u32All); //// // = 0x2839C, // SAME
658 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_8.u32All); //// // = 0x283A0, // SAME
659 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_9.u32All); //// // = 0x283A4, // SAME
660 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_10.u32All); //// // = 0x283A8, // SAME
661 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_11.u32All); //// // = 0x283AC, // SAME
662 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_12.u32All); //// // = 0x283B0, // SAME
663 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_13.u32All); //// // = 0x283B4, // SAME
664 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_14.u32All); //// // = 0x283B8, // SAME
665 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_15.u32All); //// // = 0x283BC, // SAME
666 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_16.u32All); //// // = 0x283C0, // SAME
667 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_17.u32All); //// // = 0x283C4, // SAME
668 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_18.u32All); //// // = 0x283C8, // SAME
669 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_19.u32All); //// // = 0x283CC, // SAME
670 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_20.u32All); //// // = 0x283D0, // SAME
671 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_21.u32All); //// // = 0x283D4, // SAME
672 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_22.u32All); //// // = 0x283D8, // SAME
673 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_23.u32All); //// // = 0x283DC, // SAME
674 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_24.u32All); //// // = 0x283E0, // SAME
675 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_25.u32All); //// // = 0x283E4, // SAME
676 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_26.u32All); //// // = 0x283E8, // SAME
677 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_27.u32All); //// // = 0x283EC, // SAME
678 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_28.u32All); //// // = 0x283F0, // SAME
679 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_29.u32All); //// // = 0x283F4, // SAME
680 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_30.u32All); //// // = 0x283F8, // SAME
681 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_31.u32All); //// // = 0x283FC, // SAME
682
683
684 //3
685 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_DYN_GPR_RESOURCE_LIMIT_1, 1);
686 R600_OUT_BATCH(evergreen->SQ_DYN_GPR_RESOURCE_LIMIT_1.u32All);//// // = 0x28838, //
687
688 //5
689 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
690 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_PS.u32All); //// // = 0x28844, // DIFF 0x28850
691 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_PS.u32All); //// // = 0x28848, //
692 R600_OUT_BATCH(evergreen->SQ_PGM_EXPORTS_PS.u32All); //// // = 0x2884C, // SAME 0x28854
693
694 //4
695 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
696 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_VS.u32All);//// // = 0x28860, // DIFF 0x28868
697 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_VS.u32All); //// // = 0x28864, //
698
699 //5
700 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_GS, 2);
701 /*
702 R600_OUT_BATCH(evergreen->SQ_PGM_START_GS.u32All); //// // = 0x28874, // SAME 0x2886C
703 */
704 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_GS.u32All); //// // = 0x28878, // DIFF 0x2887C
705 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_GS.u32All); //// // = 0x2887C, //
706
707 //5
708 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_ES, 2);
709 /*
710 R600_OUT_BATCH(evergreen->SQ_PGM_START_ES.u32All); //// // = 0x2888C, // SAME 0x28880
711 */
712 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_ES.u32All); //// // = 0x28890, // DIFF
713 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_ES.u32All); //// // = 0x28894, //
714
715 //4
716 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_FS, 1);
717 /*
718 R600_OUT_BATCH(evergreen->SQ_PGM_START_FS.u32All); //// // = 0x288A4, // SAME 0x28894
719 */
720 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_FS.u32All); //// // = 0x288A8, // DIFF 0x288A4
721
722 //3
723 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_HS, 1);
724 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_HS.u32All);//// // = 0x288C0, //
725
726 //3
727 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_LS, 1);
728 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_LS.u32All); //// // = 0x288D8, //
729
730 //3
731 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_LDS_ALLOC_PS, 1);
732 R600_OUT_BATCH(evergreen->SQ_LDS_ALLOC_PS.u32All); //// // = 0x288EC, //
733
734 //8
735 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
736 R600_OUT_BATCH(evergreen->SQ_ESGS_RING_ITEMSIZE.u32All); //// // = 0x28900, // SAME 0x288A8
737 R600_OUT_BATCH(evergreen->SQ_GSVS_RING_ITEMSIZE.u32All); //// // = 0x28904, // SAME 0x288AC
738 R600_OUT_BATCH(evergreen->SQ_ESTMP_RING_ITEMSIZE.u32All); //// // = 0x28908, // SAME 0x288B0
739 R600_OUT_BATCH(evergreen->SQ_GSTMP_RING_ITEMSIZE.u32All); //// // = 0x2890C, // SAME 0x288B4
740 R600_OUT_BATCH(evergreen->SQ_VSTMP_RING_ITEMSIZE.u32All); //// // = 0x28910, // SAME 0x288B8
741 R600_OUT_BATCH(evergreen->SQ_PSTMP_RING_ITEMSIZE.u32All); //// // = 0x28914, // SAME 0x288BC
742
743 //3
744 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 1);
745 R600_OUT_BATCH(evergreen->SQ_GS_VERT_ITEMSIZE.u32All); //// // = 0x2891C, // SAME 0x288C8
746
747 END_BATCH();
748
749 COMMIT_BATCH();
750
751 }
752 static void evergreenSendSPI(GLcontext *ctx, struct radeon_state_atom *atom)
753 {
754 context_t *context = EVERGREEN_CONTEXT(ctx);
755 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
756 BATCH_LOCALS(&context->radeon);
757 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
758
759 BEGIN_BATCH_NO_AUTOSTATE(59);
760
761 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_VS_OUT_ID_0, 10);
762 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_0.u32All);
763 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_1.u32All);
764 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_2.u32All);
765 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_3.u32All);
766 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_4.u32All);
767 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_5.u32All);
768 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_6.u32All);
769 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_7.u32All);
770 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_8.u32All);
771 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_9.u32All);
772
773 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_INPUT_CNTL_0, 45);
774 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[0].u32All);
775 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[1].u32All);
776 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[2].u32All);
777 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[3].u32All);
778 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[4].u32All);
779 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[5].u32All);
780 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[6].u32All);
781 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[7].u32All);
782 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[8].u32All);
783 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[9].u32All);
784 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[10].u32All);
785 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[11].u32All);
786 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[12].u32All);
787 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[13].u32All);
788 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[14].u32All);
789 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[15].u32All);
790 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[16].u32All);
791 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[17].u32All);
792 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[18].u32All);
793 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[19].u32All);
794 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[20].u32All);
795 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[21].u32All);
796 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[22].u32All);
797 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[23].u32All);
798 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[24].u32All);
799 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[25].u32All);
800 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[26].u32All);
801 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[27].u32All);
802 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[28].u32All);
803 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[29].u32All);
804 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[30].u32All);
805 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[31].u32All);
806 R600_OUT_BATCH(evergreen->SPI_VS_OUT_CONFIG.u32All);
807 R600_OUT_BATCH(evergreen->SPI_THREAD_GROUPING.u32All);
808 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_0.u32All);
809 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_1.u32All);
810 R600_OUT_BATCH(evergreen->SPI_INTERP_CONTROL_0.u32All);
811 R600_OUT_BATCH(evergreen->SPI_INPUT_Z.u32All);
812 R600_OUT_BATCH(evergreen->SPI_FOG_CNTL.u32All);
813 R600_OUT_BATCH(evergreen->SPI_BARYC_CNTL.u32All);
814 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_2.u32All);
815 R600_OUT_BATCH(evergreen->SPI_COMPUTE_INPUT_CNTL.u32All);
816 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_X.u32All);
817 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Y.u32All);
818 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Z.u32All);
819
820 END_BATCH();
821
822 COMMIT_BATCH();
823 }
824 static void evergreenSendSX(GLcontext *ctx, struct radeon_state_atom *atom)
825 {
826 context_t *context = EVERGREEN_CONTEXT(ctx);
827 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
828 BATCH_LOCALS(&context->radeon);
829 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
830
831 BEGIN_BATCH_NO_AUTOSTATE(9);
832
833 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, evergreen->SX_MISC.u32All);
834 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_TEST_CONTROL, evergreen->SX_ALPHA_TEST_CONTROL.u32All);
835 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_REF, evergreen->SX_ALPHA_REF.u32All);
836
837 END_BATCH();
838
839 COMMIT_BATCH();
840 }
841
842 static void evergreenSetDepthTarget(context_t *context)
843 {
844 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
845 struct radeon_renderbuffer *rrb;
846 unsigned int nPitchInPixel;
847
848 rrb = radeon_get_depthbuffer(&context->radeon);
849 if (!rrb)
850 {
851 return;
852 }
853
854 EVERGREEN_STATECHANGE(context, db);
855
856 evergreen->DB_DEPTH_SIZE.u32All = 0;
857
858 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
859 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift,
860 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask);
861 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (context->radeon.radeonScreen->driScreen->fbHeight/8)-1,
862 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift,
863 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask);
864 evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1;
865
866 if(4 == rrb->cpp)
867 {
868 SETfield(evergreen->DB_Z_INFO.u32All, DEPTH_8_24,
869 EG_DB_Z_INFO__FORMAT_shift,
870 EG_DB_Z_INFO__FORMAT_mask);
871 }
872 else
873 {
874 SETfield(evergreen->DB_Z_INFO.u32All, DEPTH_16,
875 EG_DB_Z_INFO__FORMAT_shift,
876 EG_DB_Z_INFO__FORMAT_mask);
877 }
878 SETfield(evergreen->DB_Z_INFO.u32All, ARRAY_1D_TILED_THIN1,
879 EG_DB_Z_INFO__ARRAY_MODE_shift,
880 EG_DB_Z_INFO__ARRAY_MODE_mask);
881 }
882
883 static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom)
884 {
885 context_t *context = EVERGREEN_CONTEXT(ctx);
886 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
887 struct radeon_renderbuffer *rrb;
888 BATCH_LOCALS(&context->radeon);
889 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
890
891 evergreenSetDepthTarget(context);
892
893 //8
894 BEGIN_BATCH_NO_AUTOSTATE(7);
895 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
896 R600_OUT_BATCH(evergreen->DB_RENDER_CONTROL.u32All);
897 R600_OUT_BATCH(evergreen->DB_COUNT_CONTROL.u32All);
898 R600_OUT_BATCH(evergreen->DB_DEPTH_VIEW.u32All);
899 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE.u32All);
900 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE2.u32All);
901 /*
902 R600_OUT_BATCH(evergreen->DB_HTILE_DATA_BASE.u32All);
903 */
904 END_BATCH();
905
906 //4
907 BEGIN_BATCH_NO_AUTOSTATE(4);
908 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
909 R600_OUT_BATCH(evergreen->DB_STENCIL_CLEAR.u32All);
910 R600_OUT_BATCH(evergreen->DB_DEPTH_CLEAR.u32All);
911 END_BATCH();
912
913 //4
914 BEGIN_BATCH_NO_AUTOSTATE(4);
915 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_DEPTH_SIZE, 2);
916 R600_OUT_BATCH(evergreen->DB_DEPTH_SIZE.u32All);
917 R600_OUT_BATCH(evergreen->DB_DEPTH_SLICE.u32All);
918 END_BATCH();
919
920 //3
921 BEGIN_BATCH_NO_AUTOSTATE(3);
922 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, evergreen->DB_DEPTH_CONTROL.u32All);
923 END_BATCH();
924
925 //3
926 BEGIN_BATCH_NO_AUTOSTATE(3);
927 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_SHADER_CONTROL, evergreen->DB_SHADER_CONTROL.u32All);
928 END_BATCH();
929
930 //5
931 BEGIN_BATCH_NO_AUTOSTATE(5);
932 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_SRESULTS_COMPARE_STATE0, 3);
933 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE0.u32All);
934 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE1.u32All);
935 R600_OUT_BATCH(evergreen->DB_PRELOAD_CONTROL.u32All);
936 END_BATCH();
937
938 //3
939 BEGIN_BATCH_NO_AUTOSTATE(3);
940 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, evergreen->DB_ALPHA_TO_MASK.u32All);
941 END_BATCH();
942
943 rrb = radeon_get_depthbuffer(&context->radeon);
944 if( (rrb != NULL) && (rrb->bo != NULL) )
945 {
946 //5
947 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
948 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_INFO, evergreen->DB_Z_INFO.u32All);
949 R600_OUT_BATCH_RELOC(evergreen->DB_Z_INFO.u32All,
950 rrb->bo,
951 evergreen->DB_Z_INFO.u32All,
952 0, RADEON_GEM_DOMAIN_VRAM, 0);
953 END_BATCH();
954
955 //5
956 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_ENABLE_bit) > 0)
957 {
958 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
959 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_READ_BASE, evergreen->DB_Z_READ_BASE.u32All);
960 R600_OUT_BATCH_RELOC(evergreen->DB_Z_READ_BASE.u32All,
961 rrb->bo,
962 evergreen->DB_Z_READ_BASE.u32All,
963 0, RADEON_GEM_DOMAIN_VRAM, 0);
964 END_BATCH();
965 }
966 //5
967 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_WRITE_ENABLE_bit) > 0)
968 {
969 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
970 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_WRITE_BASE, evergreen->DB_Z_READ_BASE.u32All);
971 R600_OUT_BATCH_RELOC(evergreen->DB_Z_WRITE_BASE.u32All,
972 rrb->bo,
973 evergreen->DB_Z_WRITE_BASE.u32All,
974 0, RADEON_GEM_DOMAIN_VRAM, 0);
975 END_BATCH();
976 }
977 }
978 /*
979 if (ctx->DrawBuffer)
980 {
981 rrb = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
982
983 if((rrb != NULL) && (rrb->bo != NULL))
984 {
985 //5
986 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
987 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_INFO, evergreen->DB_Z_INFO.u32All);
988 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_INFO.u32All,
989 rrb->bo,
990 evergreen->DB_STENCIL_INFO.u32All,
991 0, RADEON_GEM_DOMAIN_VRAM, 0);
992 END_BATCH();
993
994 //10
995 if((evergreen->DB_DEPTH_CONTROL.u32All & STENCIL_ENABLE_bit) > 0)
996 {
997 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
998 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, evergreen->DB_STENCIL_READ_BASE.u32All);
999 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_READ_BASE.u32All,
1000 rrb->bo,
1001 evergreen->DB_STENCIL_READ_BASE.u32All,
1002 0, RADEON_GEM_DOMAIN_VRAM, 0);
1003 END_BATCH();
1004
1005 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1006 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, evergreen->DB_STENCIL_WRITE_BASE.u32All);
1007 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_WRITE_BASE.u32All,
1008 rrb->bo,
1009 evergreen->DB_STENCIL_WRITE_BASE.u32All,
1010 0, RADEON_GEM_DOMAIN_VRAM, 0);
1011 END_BATCH();
1012 }
1013 }
1014 }
1015 */
1016 COMMIT_BATCH();
1017 }
1018
1019 static void evergreenSetRenderTarget(context_t *context, int id)
1020 {
1021 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1022
1023 struct radeon_renderbuffer *rrb;
1024 unsigned int nPitchInPixel;
1025
1026 rrb = radeon_get_colorbuffer(&context->radeon);
1027 if (!rrb || !rrb->bo) {
1028 return;
1029 }
1030
1031 EVERGREEN_STATECHANGE(context, cb);
1032
1033 /* addr */
1034 evergreen->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
1035
1036 /* pitch */
1037 nPitchInPixel = rrb->pitch/rrb->cpp;
1038
1039 SETfield(evergreen->render_target[id].CB_COLOR0_PITCH.u32All, (nPitchInPixel/8)-1,
1040 EG_CB_COLOR0_PITCH__TILE_MAX_shift,
1041 EG_CB_COLOR0_PITCH__TILE_MAX_mask);
1042
1043 /* skice */
1044 SETfield(evergreen->render_target[id].CB_COLOR0_SLICE.u32All,
1045 //( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1046 ( (nPitchInPixel * 240)/64 )-1,
1047 EG_CB_COLOR0_SLICE__TILE_MAX_shift,
1048 EG_CB_COLOR0_SLICE__TILE_MAX_mask);
1049
1050 /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
1051 SETbit(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All,
1052 EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
1053
1054 /* CB_COLOR0_INFO */
1055 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1056 ENDIAN_NONE,
1057 EG_CB_COLOR0_INFO__ENDIAN_shift,
1058 EG_CB_COLOR0_INFO__ENDIAN_mask);
1059 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1060 ARRAY_LINEAR_GENERAL,
1061 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1062 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1063 if(4 == rrb->cpp)
1064 {
1065 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1066 COLOR_8_8_8_8,
1067 EG_CB_COLOR0_INFO__FORMAT_shift,
1068 EG_CB_COLOR0_INFO__FORMAT_mask);
1069 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1070 SWAP_ALT, //SWAP_STD
1071 EG_CB_COLOR0_INFO__COMP_SWAP_shift,
1072 EG_CB_COLOR0_INFO__COMP_SWAP_mask);
1073 }
1074 else
1075 {
1076 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1077 COLOR_5_6_5,
1078 EG_CB_COLOR0_INFO__FORMAT_shift,
1079 EG_CB_COLOR0_INFO__FORMAT_mask);
1080 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1081 SWAP_ALT_REV,
1082 EG_CB_COLOR0_INFO__COMP_SWAP_shift,
1083 EG_CB_COLOR0_INFO__COMP_SWAP_mask);
1084 }
1085 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1086 1,
1087 EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
1088 EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
1089 SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1090 EG_CB_COLOR0_INFO__BLEND_CLAMP_bit);
1091 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1092 NUMBER_UNORM,
1093 EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
1094 EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
1095
1096 evergreen->render_target[id].CB_COLOR0_VIEW.u32All = 0;
1097 evergreen->render_target[id].CB_COLOR0_CMASK.u32All = 0;
1098 evergreen->render_target[id].CB_COLOR0_FMASK.u32All = 0;
1099 evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0;
1100
1101 evergreen->render_target[id].enabled = GL_TRUE;
1102 }
1103
1104 static void evergreenSendCB(GLcontext *ctx, struct radeon_state_atom *atom)
1105 {
1106 context_t *context = EVERGREEN_CONTEXT(ctx);
1107 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1108 struct radeon_renderbuffer *rrb;
1109 BATCH_LOCALS(&context->radeon);
1110 int id = 0;
1111 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1112
1113 rrb = radeon_get_colorbuffer(&context->radeon);
1114 if (!rrb || !rrb->bo) {
1115 return;
1116 }
1117
1118 evergreenSetRenderTarget(context, 0);
1119
1120 if (!evergreen->render_target[id].enabled)
1121 return;
1122
1123 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1124 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
1125 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_BASE.u32All);
1126 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1127 rrb->bo,
1128 evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1129 0, RADEON_GEM_DOMAIN_VRAM, 0);
1130 END_BATCH();
1131
1132 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1133 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, evergreen->render_target[id].CB_COLOR0_INFO.u32All);
1134 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1135 rrb->bo,
1136 evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1137 0, RADEON_GEM_DOMAIN_VRAM, 0);
1138 END_BATCH();
1139
1140 BEGIN_BATCH_NO_AUTOSTATE(5);
1141 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
1142 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_PITCH.u32All);
1143 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_SLICE.u32All);
1144 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_VIEW.u32All);
1145 END_BATCH();
1146
1147 BEGIN_BATCH_NO_AUTOSTATE(4);
1148 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 2);
1149 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All);
1150 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_DIM.u32All);
1151 /*
1152 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
1153 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
1154 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
1155 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
1156 */
1157 END_BATCH();
1158
1159 BEGIN_BATCH_NO_AUTOSTATE(4);
1160 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_TARGET_MASK, 2);
1161 R600_OUT_BATCH(evergreen->CB_TARGET_MASK.u32All);
1162 R600_OUT_BATCH(evergreen->CB_SHADER_MASK.u32All);
1163 END_BATCH();
1164
1165 BEGIN_BATCH_NO_AUTOSTATE(5);
1166 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_BLEND_RED, 3);
1167 R600_OUT_BATCH(evergreen->CB_BLEND_RED.u32All);
1168 R600_OUT_BATCH(evergreen->CB_BLEND_GREEN.u32All);
1169 R600_OUT_BATCH(evergreen->CB_BLEND_BLUE.u32All);
1170 END_BATCH();
1171
1172 BEGIN_BATCH_NO_AUTOSTATE(9);
1173 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND_ALPHA, evergreen->CB_BLEND_ALPHA.u32All);
1174 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, evergreen->CB_BLEND0_CONTROL.u32All);
1175 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR_CONTROL, evergreen->CB_COLOR_CONTROL.u32All);
1176 END_BATCH();
1177
1178 COMMIT_BATCH();
1179 }
1180 static void evergreenSendCP(GLcontext *ctx, struct radeon_state_atom *atom)
1181 {
1182 context_t *context = EVERGREEN_CONTEXT(ctx);
1183 BATCH_LOCALS(&context->radeon);
1184 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1185
1186 //first to send
1187 //r700Start3D
1188 BEGIN_BATCH_NO_AUTOSTATE(3);
1189 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); //IT_CONTEXT_CONTROL 0x28
1190 R600_OUT_BATCH(0x80000000);
1191 R600_OUT_BATCH(0x80000000);
1192 END_BATCH();
1193
1194 COMMIT_BATCH();
1195 }
1196 static void evergreenSendVGT(GLcontext *ctx, struct radeon_state_atom *atom)
1197 {
1198 context_t *context = EVERGREEN_CONTEXT(ctx);
1199 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1200 BATCH_LOCALS(&context->radeon);
1201 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1202
1203 /* moved to draw:
1204 VGT_DRAW_INITIATOR
1205 VGT_INDEX_TYPE
1206 VGT_PRIMITIVE_TYPE
1207 */
1208 BEGIN_BATCH_NO_AUTOSTATE(5);
1209 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 3);
1210 R600_OUT_BATCH(evergreen->VGT_MAX_VTX_INDX.u32All);
1211 R600_OUT_BATCH(evergreen->VGT_MIN_VTX_INDX.u32All);
1212 R600_OUT_BATCH(evergreen->VGT_INDX_OFFSET.u32All);
1213 END_BATCH();
1214
1215 BEGIN_BATCH_NO_AUTOSTATE(6);
1216 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_OUTPUT_PATH_CNTL, evergreen->VGT_OUTPUT_PATH_CNTL.u32All);
1217
1218 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_GS_MODE, evergreen->VGT_GS_MODE.u32All);
1219 END_BATCH();
1220
1221 BEGIN_BATCH_NO_AUTOSTATE(3);
1222 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVEID_EN, 1);
1223 R600_OUT_BATCH(evergreen->VGT_PRIMITIVEID_EN.u32All);
1224 END_BATCH();
1225
1226 BEGIN_BATCH_NO_AUTOSTATE(4);
1227 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
1228 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_0.u32All);
1229 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_1.u32All);
1230 END_BATCH();
1231
1232 BEGIN_BATCH_NO_AUTOSTATE(4);
1233 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
1234 R600_OUT_BATCH(evergreen->VGT_REUSE_OFF.u32All);
1235 R600_OUT_BATCH(evergreen->VGT_VTX_CNT_EN.u32All);
1236 END_BATCH();
1237
1238 BEGIN_BATCH_NO_AUTOSTATE(3);
1239 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, evergreen->VGT_SHADER_STAGES_EN.u32All);
1240 END_BATCH();
1241
1242 BEGIN_BATCH_NO_AUTOSTATE(4);
1243 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
1244 R600_OUT_BATCH(evergreen->VGT_STRMOUT_CONFIG.u32All);
1245 R600_OUT_BATCH(evergreen->VGT_STRMOUT_BUFFER_CONFIG.u32All);
1246 END_BATCH();
1247
1248 COMMIT_BATCH();
1249 }
1250
1251 static void evergreenSendTIMESTAMP(GLcontext *ctx, struct radeon_state_atom *atom)
1252 {
1253 context_t *context = EVERGREEN_CONTEXT(ctx);
1254 BATCH_LOCALS(&context->radeon);
1255 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1256 }
1257
1258 void evergreenInitAtoms(context_t *context)
1259 {
1260 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1261 context->radeon.hw.max_state_size = 10 + 5 + 14 + 3; /* start 3d, idle, cb/db flush, 3 for time stamp */
1262
1263 /* Setup the atom linked list */
1264 make_empty_list(&context->radeon.hw.atomlist);
1265 context->radeon.hw.atomlist.name = "atom-list";
1266
1267 EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig);
1268
1269 //make sure send first
1270 EVERGREEN_ALLOC_STATE(cp, always, 3, evergreenSendCP);
1271
1272 EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (6 + (VERT_ATTRIB_MAX * 12)), evergreenSendVTX);
1273 EVERGREEN_ALLOC_STATE(pa, always, 124, evergreenSendPA);
1274 EVERGREEN_ALLOC_STATE(tp, always, 0, evergreenSendTP);
1275 EVERGREEN_ALLOC_STATE(sq, always, 86, evergreenSendSQ); /* 85 */
1276 EVERGREEN_ALLOC_STATE(vs, always, 16, evergreenSendVSresource);
1277 EVERGREEN_ALLOC_STATE(spi, always, 59, evergreenSendSPI);
1278 EVERGREEN_ALLOC_STATE(sx, always, 9, evergreenSendSX);
1279 EVERGREEN_ALLOC_STATE(tx, evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */
1280 EVERGREEN_ALLOC_STATE(db, always, 60, evergreenSendDB);
1281 EVERGREEN_ALLOC_STATE(cb, always, 35, evergreenSendCB);
1282 EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT);
1283 EVERGREEN_ALLOC_STATE(timestamp, always, 3, evergreenSendTIMESTAMP);
1284
1285 //evergreen_init_query_stateobj(&context->radeon, 6 * 2);
1286
1287 context->radeon.hw.is_dirty = GL_TRUE;
1288 context->radeon.hw.all_dirty = GL_TRUE;
1289 }