src/mesa/drivers/dri/r600/r600_blit.c

   1 /*
   2  * Copyright (C) 2009 Advanced Micro Devices, Inc.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r600_context.h"
  30
  31 #include "r600_blit.h"
  32 #include "r600_blit_shaders.h"
  33 #include "r600_cmdbuf.h"
  34
  35 /* common formats supported as both textures and render targets */
  36 unsigned r600_check_blit(gl_format mesa_format)
  37 {
  38     switch (mesa_format) {
  39     case MESA_FORMAT_RGBA8888:
  40     case MESA_FORMAT_SIGNED_RGBA8888:
  41     case MESA_FORMAT_RGBA8888_REV:
  42     case MESA_FORMAT_SIGNED_RGBA8888_REV:
  43     case MESA_FORMAT_ARGB8888:
  44     case MESA_FORMAT_XRGB8888:
  45     case MESA_FORMAT_ARGB8888_REV:
  46     case MESA_FORMAT_XRGB8888_REV:
  47     case MESA_FORMAT_RGB565:
  48     case MESA_FORMAT_RGB565_REV:
  49     case MESA_FORMAT_ARGB4444:
  50     case MESA_FORMAT_ARGB4444_REV:
  51     case MESA_FORMAT_ARGB1555:
  52     case MESA_FORMAT_ARGB1555_REV:
  53     case MESA_FORMAT_AL88:
  54     case MESA_FORMAT_AL88_REV:
  55     case MESA_FORMAT_RGB332:
  56     case MESA_FORMAT_A8:
  57     case MESA_FORMAT_I8:
  58     case MESA_FORMAT_CI8:
  59     case MESA_FORMAT_L8:
  60     case MESA_FORMAT_RGBA_FLOAT32:
  61     case MESA_FORMAT_RGBA_FLOAT16:
  62     case MESA_FORMAT_ALPHA_FLOAT32:
  63     case MESA_FORMAT_ALPHA_FLOAT16:
  64     case MESA_FORMAT_LUMINANCE_FLOAT32:
  65     case MESA_FORMAT_LUMINANCE_FLOAT16:
  66     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
  67     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
  68     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
  69     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
  70     case MESA_FORMAT_X8_Z24:
  71     case MESA_FORMAT_S8_Z24:
  72     case MESA_FORMAT_Z24_S8:
  73     case MESA_FORMAT_Z16:
  74     case MESA_FORMAT_Z32:
  75     case MESA_FORMAT_SARGB8:
  76     case MESA_FORMAT_SLA8:
  77     case MESA_FORMAT_SL8:
  78             break;
  79     default:
  80             return 0;
  81     }
  82
  83     /* ??? */
  84     /* not sure blit to depth works or not yet */
  85     if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
  86             return 0;
  87
  88     return 1;
  89 }
  90
  91 static inline void
  92 set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
  93                   int nPitchInPixel, int w, int h, intptr_t dst_offset)
  94 {
  95     uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, cb_color0_view = 0;
  96     int id = 0;
  97     uint32_t comp_swap, format;
  98     BATCH_LOCALS(&context->radeon);
  99
 100     cb_color0_base = dst_offset / 256;
 101
 102     SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
 103              PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
 104     SETfield(cb_color0_size, ((nPitchInPixel * h) / 64) - 1,
 105              SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
 106
 107     SETfield(cb_color0_info, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
 108     SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
 109              CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 110
 111     SETbit(cb_color0_info, BLEND_BYPASS_bit);
 112
 113     switch(mesa_format) {
 114     case MESA_FORMAT_RGBA8888:
 115             format = COLOR_8_8_8_8;
 116             comp_swap = SWAP_STD_REV;
 117             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 118             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 119             break;
 120     case MESA_FORMAT_SIGNED_RGBA8888:
 121             format = COLOR_8_8_8_8;
 122             comp_swap = SWAP_STD_REV;
 123             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 124             SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 125             break;
 126     case MESA_FORMAT_RGBA8888_REV:
 127             format = COLOR_8_8_8_8;
 128             comp_swap = SWAP_STD;
 129             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 130             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 131             break;
 132     case MESA_FORMAT_SIGNED_RGBA8888_REV:
 133             format = COLOR_8_8_8_8;
 134             comp_swap = SWAP_STD;
 135             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 136             SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 137             break;
 138     case MESA_FORMAT_ARGB8888:
 139     case MESA_FORMAT_XRGB8888:
 140             format = COLOR_8_8_8_8;
 141             comp_swap = SWAP_ALT;
 142             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 143             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 144             break;
 145     case MESA_FORMAT_ARGB8888_REV:
 146     case MESA_FORMAT_XRGB8888_REV:
 147             format = COLOR_8_8_8_8;
 148             comp_swap = SWAP_ALT_REV;
 149             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 150             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 151             break;
 152     case MESA_FORMAT_RGB565:
 153             format = COLOR_5_6_5;
 154             comp_swap = SWAP_STD_REV;
 155             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 156             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 157             break;
 158     case MESA_FORMAT_RGB565_REV:
 159             format = COLOR_5_6_5;
 160             comp_swap = SWAP_STD;
 161             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 162             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 163             break;
 164     case MESA_FORMAT_ARGB4444:
 165             format = COLOR_4_4_4_4;
 166             comp_swap = SWAP_ALT;
 167             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 168             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 169             break;
 170     case MESA_FORMAT_ARGB4444_REV:
 171             format = COLOR_4_4_4_4;
 172             comp_swap = SWAP_ALT_REV;
 173             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 174             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 175             break;
 176     case MESA_FORMAT_ARGB1555:
 177             format = COLOR_1_5_5_5;
 178             comp_swap = SWAP_ALT;
 179             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 180             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 181             break;
 182     case MESA_FORMAT_ARGB1555_REV:
 183             format = COLOR_1_5_5_5;
 184             comp_swap = SWAP_ALT_REV;
 185             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 186             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 187             break;
 188     case MESA_FORMAT_AL88:
 189             format = COLOR_8_8;
 190             comp_swap = SWAP_STD;
 191             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 192             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 193             break;
 194     case MESA_FORMAT_AL88_REV:
 195             format = COLOR_8_8;
 196             comp_swap = SWAP_STD_REV;
 197             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 198             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 199             break;
 200     case MESA_FORMAT_RGB332:
 201             format = COLOR_3_3_2;
 202             comp_swap = SWAP_STD_REV;
 203             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 204             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 205             break;
 206     case MESA_FORMAT_A8:
 207             format = COLOR_8;
 208             comp_swap = SWAP_ALT_REV;
 209             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 210             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 211             break;
 212     case MESA_FORMAT_I8:
 213     case MESA_FORMAT_CI8:
 214             format = COLOR_8;
 215             comp_swap = SWAP_STD;
 216             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 217             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 218             break;
 219     case MESA_FORMAT_L8:
 220             format = COLOR_8;
 221             comp_swap = SWAP_ALT;
 222             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 223             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 224             break;
 225     case MESA_FORMAT_RGBA_FLOAT32:
 226             format = COLOR_32_32_32_32_FLOAT;
 227             comp_swap = SWAP_STD_REV;
 228             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 229             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 230             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 231             break;
 232     case MESA_FORMAT_RGBA_FLOAT16:
 233             format = COLOR_16_16_16_16_FLOAT;
 234             comp_swap = SWAP_STD_REV;
 235             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 236             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 237             break;
 238     case MESA_FORMAT_ALPHA_FLOAT32:
 239             format = COLOR_32_FLOAT;
 240             comp_swap = SWAP_ALT_REV;
 241             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 242             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 243             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 244             break;
 245     case MESA_FORMAT_ALPHA_FLOAT16:
 246             format = COLOR_16_FLOAT;
 247             comp_swap = SWAP_ALT_REV;
 248             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 249             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 250             break;
 251     case MESA_FORMAT_LUMINANCE_FLOAT32:
 252             format = COLOR_32_FLOAT;
 253             comp_swap = SWAP_ALT;
 254             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 255             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 256             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 257             break;
 258     case MESA_FORMAT_LUMINANCE_FLOAT16:
 259             format = COLOR_16_FLOAT;
 260             comp_swap = SWAP_ALT;
 261             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 262             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 263             break;
 264     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 265             format = COLOR_32_32_FLOAT;
 266             comp_swap = SWAP_ALT_REV;
 267             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 268             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 269             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 270             break;
 271     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 272             format = COLOR_16_16_FLOAT;
 273             comp_swap = SWAP_ALT_REV;
 274             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 275             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 276             break;
 277     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 278             format = COLOR_32_FLOAT;
 279             comp_swap = SWAP_STD;
 280             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 281             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 282             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 283             break;
 284     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 285             format = COLOR_16_FLOAT;
 286             comp_swap = SWAP_STD;
 287             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 288             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 289             break;
 290     case MESA_FORMAT_X8_Z24:
 291     case MESA_FORMAT_S8_Z24:
 292             format = COLOR_8_24;
 293             comp_swap = SWAP_STD;
 294             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 295                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 296             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 297             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 298             break;
 299     case MESA_FORMAT_Z24_S8:
 300             format = COLOR_24_8;
 301             comp_swap = SWAP_STD;
 302             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 303                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 304             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 305             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 306             break;
 307     case MESA_FORMAT_Z16:
 308             format = COLOR_16;
 309             comp_swap = SWAP_STD;
 310             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 311                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 312             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 313             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 314             break;
 315     case MESA_FORMAT_Z32:
 316             format = COLOR_32;
 317             comp_swap = SWAP_STD;
 318             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 319                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 320             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 321             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 322             break;
 323     case MESA_FORMAT_SARGB8:
 324             format = COLOR_8_8_8_8;
 325             comp_swap = SWAP_ALT;
 326             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 327             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 328             break;
 329     case MESA_FORMAT_SLA8:
 330             format = COLOR_8_8;
 331             comp_swap = SWAP_ALT_REV;
 332             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 333             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 334             break;
 335     case MESA_FORMAT_SL8:
 336             format = COLOR_8;
 337             comp_swap = SWAP_ALT_REV;
 338             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 339             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 340             break;
 341     default:
 342             fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
 343             assert("Invalid format for US output\n");
 344             return;
 345     }
 346
 347     /* must be 0 on r7xx */
 348     if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
 349             CLEARbit(cb_color0_info, BLEND_FLOAT32_bit);
 350
 351     SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
 352              CB_COLOR0_INFO__FORMAT_mask);
 353     SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);
 354
 355     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 356     R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
 357     R600_OUT_BATCH(cb_color0_base);
 358     R600_OUT_BATCH_RELOC(0,
 359                          bo,
 360                          0,
 361                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 362     END_BATCH();
 363
 364     if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
 365         (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
 366             BEGIN_BATCH_NO_AUTOSTATE(2);
 367             R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
 368             R600_OUT_BATCH((2 << id));
 369             END_BATCH();
 370     }
 371
 372     /* Set CMASK & TILE buffer to the offset of color buffer as
 373      * we don't use those this shouldn't cause any issue and we
 374      * then have a valid cmd stream
 375      */
 376     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 377     R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
 378     R600_OUT_BATCH(cb_color0_base);
 379     R600_OUT_BATCH_RELOC(0,
 380                          bo,
 381                          0,
 382                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 383     END_BATCH();
 384     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 385     R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
 386     R600_OUT_BATCH(cb_color0_base);
 387     R600_OUT_BATCH_RELOC(0,
 388                          bo,
 389                          0,
 390                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 391     END_BATCH();
 392
 393     BEGIN_BATCH_NO_AUTOSTATE(9);
 394     R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), cb_color0_size);
 395     R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), cb_color0_view);
 396     R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), 0);
 397     END_BATCH();
 398
 399     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 400     R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
 401     R600_OUT_BATCH_RELOC(0,
 402                          bo,
 403                          0,
 404                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 405     END_BATCH();
 406
 407     COMMIT_BATCH();
 408
 409 }
 410
 411 static inline void load_shaders(GLcontext * ctx)
 412 {
 413
 414     radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
 415     context_t *context = R700_CONTEXT(ctx);
 416     int i, size;
 417     uint32_t *shader;
 418
 419     if (context->blit_bo_loaded == 1)
 420         return;
 421
 422     size = 4096;
 423     context->blit_bo = radeon_bo_open(radeonctx->radeonScreen->bom, 0,
 424                                       size, 256, RADEON_GEM_DOMAIN_GTT, 0);
 425     radeon_bo_map(context->blit_bo, 1);
 426     shader = context->blit_bo->ptr;
 427
 428     for(i=0; i<sizeof(r6xx_vs)/4; i++) {
 429         shader[128+i] = r6xx_vs[i];
 430     }
 431     for(i=0; i<sizeof(r6xx_ps)/4; i++) {
 432         shader[256+i] = r6xx_ps[i];
 433     }
 434
 435     radeon_bo_unmap(context->blit_bo);
 436     context->blit_bo_loaded = 1;
 437
 438 }
 439
 440 static inline void
 441 set_shaders(context_t *context)
 442 {
 443     struct radeon_bo * pbo = context->blit_bo;
 444     BATCH_LOCALS(&context->radeon);
 445
 446     uint32_t sq_pgm_start_fs = (512 >> 8);
 447     uint32_t sq_pgm_resources_fs = 0;
 448     uint32_t sq_pgm_cf_offset_fs = 0;
 449
 450     uint32_t sq_pgm_start_vs = (512 >> 8);
 451     uint32_t sq_pgm_resources_vs = (1 << NUM_GPRS_shift);
 452     uint32_t sq_pgm_cf_offset_vs = 0;
 453
 454     uint32_t sq_pgm_start_ps = (1024 >> 8);
 455     uint32_t sq_pgm_resources_ps = (1 << NUM_GPRS_shift);
 456     uint32_t sq_pgm_cf_offset_ps = 0;
 457     uint32_t sq_pgm_exports_ps = (1 << 1);
 458
 459     r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 460
 461     /* FS */
 462     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 463     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
 464     R600_OUT_BATCH(sq_pgm_start_fs);
 465     R600_OUT_BATCH_RELOC(sq_pgm_start_fs,
 466                          pbo,
 467                          sq_pgm_start_fs,
 468                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 469     END_BATCH();
 470
 471     BEGIN_BATCH_NO_AUTOSTATE(6);
 472     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, sq_pgm_resources_fs);
 473     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, sq_pgm_cf_offset_fs);
 474     END_BATCH();
 475
 476     /* VS */
 477     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 478     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
 479     R600_OUT_BATCH(sq_pgm_start_vs);
 480     R600_OUT_BATCH_RELOC(sq_pgm_start_vs,
 481                          pbo,
 482                          sq_pgm_start_vs,
 483                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 484     END_BATCH();
 485
 486     BEGIN_BATCH_NO_AUTOSTATE(6);
 487     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, sq_pgm_resources_vs);
 488     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, sq_pgm_cf_offset_vs);
 489     END_BATCH();
 490
 491     /* PS */
 492     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 493     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
 494     R600_OUT_BATCH(sq_pgm_start_ps);
 495     R600_OUT_BATCH_RELOC(sq_pgm_start_ps,
 496                          pbo,
 497                          sq_pgm_start_ps,
 498                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 499     END_BATCH();
 500
 501     BEGIN_BATCH_NO_AUTOSTATE(9);
 502     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, sq_pgm_resources_ps);
 503     R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, sq_pgm_exports_ps);
 504     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, sq_pgm_cf_offset_ps);
 505     END_BATCH();
 506
 507     BEGIN_BATCH_NO_AUTOSTATE(18);
 508     R600_OUT_BATCH_REGVAL(SPI_VS_OUT_CONFIG, 0); //EXPORT_COUNT is - 1
 509     R600_OUT_BATCH_REGVAL(SPI_VS_OUT_ID_0, 0);
 510     R600_OUT_BATCH_REGVAL(SPI_PS_INPUT_CNTL_0, SEL_CENTROID_bit);
 511     R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_0, (1 << NUM_INTERP_shift));
 512     R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_1, 0);
 513     R600_OUT_BATCH_REGVAL(SPI_INTERP_CONTROL_0, 0);
 514     END_BATCH();
 515
 516     COMMIT_BATCH();
 517
 518 }
 519
 520 static inline void
 521 set_vtx_resource(context_t *context)
 522 {
 523     struct radeon_bo *bo = context->blit_bo;
 524     BATCH_LOCALS(&context->radeon);
 525
 526     BEGIN_BATCH_NO_AUTOSTATE(6);
 527     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 528     R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
 529     R600_OUT_BATCH(0);
 530
 531     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 532     R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
 533     R600_OUT_BATCH(0);
 534     END_BATCH();
 535     COMMIT_BATCH();
 536
 537     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
 538         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
 539         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
 540         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
 541         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
 542             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
 543     else
 544             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
 545
 546     BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
 547
 548     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 549     R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE);
 550     R600_OUT_BATCH(0);
 551     R600_OUT_BATCH(48 - 1);
 552     R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
 553     R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift);
 554     R600_OUT_BATCH(0);
 555     R600_OUT_BATCH(0);
 556     R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
 557     R600_OUT_BATCH_RELOC(SQ_VTX_CONSTANT_WORD0_0,
 558                          bo,
 559                          SQ_VTX_CONSTANT_WORD0_0,
 560                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 561     END_BATCH();
 562     COMMIT_BATCH();
 563
 564 }
 565
 566 static inline void
 567 set_tex_resource(context_t * context,
 568                  gl_format mesa_format, struct radeon_bo *bo, int w, int h,
 569                  int TexelPitch, intptr_t src_offset)
 570 {
 571     uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource6;
 572
 573     sq_tex_resource0 = sq_tex_resource1 = sq_tex_resource2 = sq_tex_resource4 = sq_tex_resource6 = 0;
 574     BATCH_LOCALS(&context->radeon);
 575
 576     SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
 577     SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
 578                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 579                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 580
 581     switch (mesa_format) {
 582     case MESA_FORMAT_RGBA8888:
 583     case MESA_FORMAT_SIGNED_RGBA8888:
 584             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 585                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 586
 587             SETfield(sq_tex_resource4, SQ_SEL_W,
 588                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 589             SETfield(sq_tex_resource4, SQ_SEL_Z,
 590                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 591             SETfield(sq_tex_resource4, SQ_SEL_Y,
 592                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 593             SETfield(sq_tex_resource4, SQ_SEL_X,
 594                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 595             if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
 596                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 597                              FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 598                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 599                              FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 600                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 601                              FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 602                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 603                              FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 604             }
 605             break;
 606     case MESA_FORMAT_RGBA8888_REV:
 607     case MESA_FORMAT_SIGNED_RGBA8888_REV:
 608             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 609                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 610
 611             SETfield(sq_tex_resource4, SQ_SEL_X,
 612                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 613             SETfield(sq_tex_resource4, SQ_SEL_Y,
 614                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 615             SETfield(sq_tex_resource4, SQ_SEL_Z,
 616                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 617             SETfield(sq_tex_resource4, SQ_SEL_W,
 618                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 619             if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
 620                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 621                              FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 622                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 623                              FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 624                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 625                              FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 626                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 627                              FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 628             }
 629             break;
 630     case MESA_FORMAT_ARGB8888:
 631             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 632                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 633
 634             SETfield(sq_tex_resource4, SQ_SEL_Z,
 635                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 636             SETfield(sq_tex_resource4, SQ_SEL_Y,
 637                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 638             SETfield(sq_tex_resource4, SQ_SEL_X,
 639                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 640             SETfield(sq_tex_resource4, SQ_SEL_W,
 641                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 642             break;
 643     case MESA_FORMAT_XRGB8888:
 644             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 645                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 646
 647             SETfield(sq_tex_resource4, SQ_SEL_Z,
 648                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 649             SETfield(sq_tex_resource4, SQ_SEL_Y,
 650                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 651             SETfield(sq_tex_resource4, SQ_SEL_X,
 652                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 653             SETfield(sq_tex_resource4, SQ_SEL_1,
 654                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 655             break;
 656     case MESA_FORMAT_ARGB8888_REV:
 657             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 658                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 659
 660             SETfield(sq_tex_resource4, SQ_SEL_Y,
 661                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 662             SETfield(sq_tex_resource4, SQ_SEL_Z,
 663                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 664             SETfield(sq_tex_resource4, SQ_SEL_W,
 665                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 666             SETfield(sq_tex_resource4, SQ_SEL_X,
 667                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 668             break;
 669     case MESA_FORMAT_XRGB8888_REV:
 670             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 671                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 672
 673             SETfield(sq_tex_resource4, SQ_SEL_1,
 674                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 675             SETfield(sq_tex_resource4, SQ_SEL_Z,
 676                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 677             SETfield(sq_tex_resource4, SQ_SEL_W,
 678                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 679             SETfield(sq_tex_resource4, SQ_SEL_X,
 680                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 681             break;
 682     case MESA_FORMAT_RGB565:
 683             SETfield(sq_tex_resource1, FMT_5_6_5,
 684                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 685
 686             SETfield(sq_tex_resource4, SQ_SEL_Z,
 687                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 688             SETfield(sq_tex_resource4, SQ_SEL_Y,
 689                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 690             SETfield(sq_tex_resource4, SQ_SEL_X,
 691                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 692             SETfield(sq_tex_resource4, SQ_SEL_1,
 693                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 694             break;
 695     case MESA_FORMAT_RGB565_REV:
 696             SETfield(sq_tex_resource1, FMT_5_6_5,
 697                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 698
 699             SETfield(sq_tex_resource4, SQ_SEL_X,
 700                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 701             SETfield(sq_tex_resource4, SQ_SEL_Y,
 702                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 703             SETfield(sq_tex_resource4, SQ_SEL_Z,
 704                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 705             SETfield(sq_tex_resource4, SQ_SEL_1,
 706                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 707             break;
 708     case MESA_FORMAT_ARGB4444:
 709             SETfield(sq_tex_resource1, FMT_4_4_4_4,
 710                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 711
 712             SETfield(sq_tex_resource4, SQ_SEL_Z,
 713                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 714             SETfield(sq_tex_resource4, SQ_SEL_Y,
 715                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 716             SETfield(sq_tex_resource4, SQ_SEL_X,
 717                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 718             SETfield(sq_tex_resource4, SQ_SEL_W,
 719                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 720             break;
 721     case MESA_FORMAT_ARGB4444_REV:
 722             SETfield(sq_tex_resource1, FMT_4_4_4_4,
 723                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 724
 725             SETfield(sq_tex_resource4, SQ_SEL_Y,
 726                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 727             SETfield(sq_tex_resource4, SQ_SEL_Z,
 728                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 729             SETfield(sq_tex_resource4, SQ_SEL_W,
 730                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 731             SETfield(sq_tex_resource4, SQ_SEL_X,
 732                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 733             break;
 734     case MESA_FORMAT_ARGB1555:
 735             SETfield(sq_tex_resource1, FMT_1_5_5_5,
 736                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 737
 738             SETfield(sq_tex_resource4, SQ_SEL_Z,
 739                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 740             SETfield(sq_tex_resource4, SQ_SEL_Y,
 741                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 742             SETfield(sq_tex_resource4, SQ_SEL_X,
 743                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 744             SETfield(sq_tex_resource4, SQ_SEL_W,
 745                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 746             break;
 747     case MESA_FORMAT_ARGB1555_REV:
 748             SETfield(sq_tex_resource1, FMT_1_5_5_5,
 749                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 750
 751             SETfield(sq_tex_resource4, SQ_SEL_Y,
 752                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 753             SETfield(sq_tex_resource4, SQ_SEL_Z,
 754                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 755             SETfield(sq_tex_resource4, SQ_SEL_W,
 756                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 757             SETfield(sq_tex_resource4, SQ_SEL_X,
 758                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 759             break;
 760     case MESA_FORMAT_AL88:
 761     case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
 762             SETfield(sq_tex_resource1, FMT_8_8,
 763                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 764
 765             SETfield(sq_tex_resource4, SQ_SEL_X,
 766                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 767             SETfield(sq_tex_resource4, SQ_SEL_X,
 768                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 769             SETfield(sq_tex_resource4, SQ_SEL_X,
 770                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 771             SETfield(sq_tex_resource4, SQ_SEL_Y,
 772                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 773             break;
 774     case MESA_FORMAT_RGB332:
 775             SETfield(sq_tex_resource1, FMT_3_3_2,
 776                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 777
 778             SETfield(sq_tex_resource4, SQ_SEL_Z,
 779                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 780             SETfield(sq_tex_resource4, SQ_SEL_Y,
 781                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 782             SETfield(sq_tex_resource4, SQ_SEL_X,
 783                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 784             SETfield(sq_tex_resource4, SQ_SEL_1,
 785                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 786             break;
 787     case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
 788             SETfield(sq_tex_resource1, FMT_8,
 789                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 790
 791             SETfield(sq_tex_resource4, SQ_SEL_0,
 792                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 793             SETfield(sq_tex_resource4, SQ_SEL_0,
 794                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 795             SETfield(sq_tex_resource4, SQ_SEL_0,
 796                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 797             SETfield(sq_tex_resource4, SQ_SEL_X,
 798                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 799             break;
 800     case MESA_FORMAT_L8: /* X, X, X, ONE */
 801             SETfield(sq_tex_resource1, FMT_8,
 802                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 803
 804             SETfield(sq_tex_resource4, SQ_SEL_X,
 805                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 806             SETfield(sq_tex_resource4, SQ_SEL_X,
 807                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 808             SETfield(sq_tex_resource4, SQ_SEL_X,
 809                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 810             SETfield(sq_tex_resource4, SQ_SEL_1,
 811                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 812             break;
 813     case MESA_FORMAT_I8: /* X, X, X, X */
 814     case MESA_FORMAT_CI8:
 815             SETfield(sq_tex_resource1, FMT_8,
 816                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 817
 818             SETfield(sq_tex_resource4, SQ_SEL_X,
 819                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 820             SETfield(sq_tex_resource4, SQ_SEL_X,
 821                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 822             SETfield(sq_tex_resource4, SQ_SEL_X,
 823                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 824             SETfield(sq_tex_resource4, SQ_SEL_X,
 825                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 826             break;
 827     case MESA_FORMAT_RGBA_FLOAT32:
 828             SETfield(sq_tex_resource1, FMT_32_32_32_32_FLOAT,
 829                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 830
 831             SETfield(sq_tex_resource4, SQ_SEL_X,
 832                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 833             SETfield(sq_tex_resource4, SQ_SEL_Y,
 834                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 835             SETfield(sq_tex_resource4, SQ_SEL_Z,
 836                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 837             SETfield(sq_tex_resource4, SQ_SEL_W,
 838                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 839             break;
 840     case MESA_FORMAT_RGBA_FLOAT16:
 841             SETfield(sq_tex_resource1, FMT_16_16_16_16_FLOAT,
 842                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 843
 844             SETfield(sq_tex_resource4, SQ_SEL_X,
 845                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 846             SETfield(sq_tex_resource4, SQ_SEL_Y,
 847                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 848             SETfield(sq_tex_resource4, SQ_SEL_Z,
 849                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 850             SETfield(sq_tex_resource4, SQ_SEL_W,
 851                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 852             break;
 853     case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
 854             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 855                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 856
 857             SETfield(sq_tex_resource4, SQ_SEL_0,
 858                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 859             SETfield(sq_tex_resource4, SQ_SEL_0,
 860                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 861             SETfield(sq_tex_resource4, SQ_SEL_0,
 862                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 863             SETfield(sq_tex_resource4, SQ_SEL_X,
 864                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 865             break;
 866     case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
 867             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 868                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 869
 870             SETfield(sq_tex_resource4, SQ_SEL_0,
 871                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 872             SETfield(sq_tex_resource4, SQ_SEL_0,
 873                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 874             SETfield(sq_tex_resource4, SQ_SEL_0,
 875                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 876             SETfield(sq_tex_resource4, SQ_SEL_X,
 877                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 878             break;
 879     case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
 880             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 881                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 882
 883             SETfield(sq_tex_resource4, SQ_SEL_X,
 884                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 885             SETfield(sq_tex_resource4, SQ_SEL_X,
 886                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 887             SETfield(sq_tex_resource4, SQ_SEL_X,
 888                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 889             SETfield(sq_tex_resource4, SQ_SEL_1,
 890                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 891             break;
 892     case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
 893             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 894                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 895
 896             SETfield(sq_tex_resource4, SQ_SEL_X,
 897                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 898             SETfield(sq_tex_resource4, SQ_SEL_X,
 899                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 900             SETfield(sq_tex_resource4, SQ_SEL_X,
 901                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 902             SETfield(sq_tex_resource4, SQ_SEL_1,
 903                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 904             break;
 905     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 906             SETfield(sq_tex_resource1, FMT_32_32_FLOAT,
 907                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 908
 909             SETfield(sq_tex_resource4, SQ_SEL_X,
 910                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 911             SETfield(sq_tex_resource4, SQ_SEL_X,
 912                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 913             SETfield(sq_tex_resource4, SQ_SEL_X,
 914                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 915             SETfield(sq_tex_resource4, SQ_SEL_Y,
 916                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 917             break;
 918     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 919             SETfield(sq_tex_resource1, FMT_16_16_FLOAT,
 920                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 921
 922             SETfield(sq_tex_resource4, SQ_SEL_X,
 923                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 924             SETfield(sq_tex_resource4, SQ_SEL_X,
 925                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 926             SETfield(sq_tex_resource4, SQ_SEL_X,
 927                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 928             SETfield(sq_tex_resource4, SQ_SEL_Y,
 929                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 930             break;
 931     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 932             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 933                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 934
 935             SETfield(sq_tex_resource4, SQ_SEL_X,
 936                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 937             SETfield(sq_tex_resource4, SQ_SEL_X,
 938                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 939             SETfield(sq_tex_resource4, SQ_SEL_X,
 940                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 941             SETfield(sq_tex_resource4, SQ_SEL_X,
 942                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 943             break;
 944     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 945             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 946                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 947
 948             SETfield(sq_tex_resource4, SQ_SEL_X,
 949                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 950             SETfield(sq_tex_resource4, SQ_SEL_X,
 951                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 952             SETfield(sq_tex_resource4, SQ_SEL_X,
 953                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 954             SETfield(sq_tex_resource4, SQ_SEL_X,
 955                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 956             break;
 957     case MESA_FORMAT_Z16:
 958             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 959             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 960                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 961                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 962             SETfield(sq_tex_resource1, FMT_16,
 963                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 964             SETfield(sq_tex_resource4, SQ_SEL_X,
 965                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 966             SETfield(sq_tex_resource4, SQ_SEL_X,
 967                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 968             SETfield(sq_tex_resource4, SQ_SEL_X,
 969                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 970             SETfield(sq_tex_resource4, SQ_SEL_X,
 971                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 972             break;
 973     case MESA_FORMAT_X8_Z24:
 974             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 975             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 976                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 977                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 978             SETfield(sq_tex_resource1, FMT_8_24,
 979                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 980             SETfield(sq_tex_resource4, SQ_SEL_X,
 981                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 982             SETfield(sq_tex_resource4, SQ_SEL_1,
 983                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 984             SETfield(sq_tex_resource4, SQ_SEL_0,
 985                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 986             SETfield(sq_tex_resource4, SQ_SEL_1,
 987                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 988             break;
 989     case MESA_FORMAT_S8_Z24:
 990             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 991             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 992                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 993                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 994             SETfield(sq_tex_resource1, FMT_8_24,
 995                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 996             SETfield(sq_tex_resource4, SQ_SEL_X,
 997                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 998             SETfield(sq_tex_resource4, SQ_SEL_Y,
 999                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1000             SETfield(sq_tex_resource4, SQ_SEL_0,
1001                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1002             SETfield(sq_tex_resource4, SQ_SEL_1,
1003                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1004             break;
1005     case MESA_FORMAT_Z24_S8:
1006             SETbit(sq_tex_resource0, TILE_TYPE_bit);
1007             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1008                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1009                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1010             SETfield(sq_tex_resource1, FMT_24_8,
1011                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1012             SETfield(sq_tex_resource4, SQ_SEL_X,
1013                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1014             SETfield(sq_tex_resource4, SQ_SEL_Y,
1015                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1016             SETfield(sq_tex_resource4, SQ_SEL_0,
1017                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1018             SETfield(sq_tex_resource4, SQ_SEL_1,
1019                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1020             break;
1021     case MESA_FORMAT_Z32:
1022             SETbit(sq_tex_resource0, TILE_TYPE_bit);
1023             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1024                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1025                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1026             SETfield(sq_tex_resource1, FMT_32,
1027                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1028             SETfield(sq_tex_resource4, SQ_SEL_X,
1029                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1030             SETfield(sq_tex_resource4, SQ_SEL_X,
1031                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1032             SETfield(sq_tex_resource4, SQ_SEL_X,
1033                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1034             SETfield(sq_tex_resource4, SQ_SEL_X,
1035                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1036             break;
1037     case MESA_FORMAT_S8:
1038             SETbit(sq_tex_resource0, TILE_TYPE_bit);
1039             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1040                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1041                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1042             SETfield(sq_tex_resource1, FMT_8,
1043                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1044             SETfield(sq_tex_resource4, SQ_SEL_X,
1045                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1046             SETfield(sq_tex_resource4, SQ_SEL_X,
1047                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1048             SETfield(sq_tex_resource4, SQ_SEL_X,
1049                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1050             SETfield(sq_tex_resource4, SQ_SEL_X,
1051                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1052             break;
1053     case MESA_FORMAT_SARGB8:
1054             SETfield(sq_tex_resource1, FMT_8_8_8_8,
1055                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1056
1057             SETfield(sq_tex_resource4, SQ_SEL_Z,
1058                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1059             SETfield(sq_tex_resource4, SQ_SEL_Y,
1060                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1061             SETfield(sq_tex_resource4, SQ_SEL_X,
1062                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1063             SETfield(sq_tex_resource4, SQ_SEL_W,
1064                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1065             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1066             break;
1067     case MESA_FORMAT_SLA8:
1068             SETfield(sq_tex_resource1, FMT_8_8,
1069                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1070
1071             SETfield(sq_tex_resource4, SQ_SEL_X,
1072                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1073             SETfield(sq_tex_resource4, SQ_SEL_X,
1074                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1075             SETfield(sq_tex_resource4, SQ_SEL_X,
1076                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1077             SETfield(sq_tex_resource4, SQ_SEL_Y,
1078                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1079             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1080             break;
1081     case MESA_FORMAT_SL8: /* X, X, X, ONE */
1082             SETfield(sq_tex_resource1, FMT_8,
1083                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1084
1085             SETfield(sq_tex_resource4, SQ_SEL_X,
1086                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1087             SETfield(sq_tex_resource4, SQ_SEL_X,
1088                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1089             SETfield(sq_tex_resource4, SQ_SEL_X,
1090                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1091             SETfield(sq_tex_resource4, SQ_SEL_1,
1092                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1093             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1094             break;
1095     default:
1096             fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
1097             assert("Invalid format for US output\n");
1098             return;
1099     };
1100
1101     SETfield(sq_tex_resource0, (TexelPitch/8)-1, PITCH_shift, PITCH_mask);
1102     SETfield(sq_tex_resource0, w - 1, TEX_WIDTH_shift, TEX_WIDTH_mask);
1103     SETfield(sq_tex_resource1, h - 1, TEX_HEIGHT_shift, TEX_HEIGHT_mask);
1104
1105     sq_tex_resource2 = src_offset / 256;
1106
1107     SETfield(sq_tex_resource6, SQ_TEX_VTX_VALID_TEXTURE,
1108              SQ_TEX_RESOURCE_WORD6_0__TYPE_shift,
1109              SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
1110
1111     r700SyncSurf(context, bo,
1112                  RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
1113                  0, TC_ACTION_ENA_bit);
1114
1115     BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
1116     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
1117     R600_OUT_BATCH(0 * 7);
1118
1119     R600_OUT_BATCH(sq_tex_resource0);
1120     R600_OUT_BATCH(sq_tex_resource1);
1121     R600_OUT_BATCH(sq_tex_resource2);
1122     R600_OUT_BATCH(0); //SQ_TEX_RESOURCE3
1123     R600_OUT_BATCH(sq_tex_resource4);
1124     R600_OUT_BATCH(0); //SQ_TEX_RESOURCE5
1125     R600_OUT_BATCH(sq_tex_resource6);
1126     R600_OUT_BATCH_RELOC(0,
1127                      bo,
1128                      0,
1129                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1130     R600_OUT_BATCH_RELOC(0,
1131                      bo,
1132                      0,
1133                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1134     END_BATCH();
1135     COMMIT_BATCH();
1136 }
1137
1138 static inline void
1139 set_tex_sampler(context_t * context)
1140 {
1141     uint32_t sq_tex_sampler_word0 = 0, sq_tex_sampler_word1 = 0, sq_tex_sampler_word2 = 0;
1142     int i = 0;
1143
1144     SETbit(sq_tex_sampler_word2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
1145
1146     BATCH_LOCALS(&context->radeon);
1147
1148     BEGIN_BATCH_NO_AUTOSTATE(5);
1149     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
1150     R600_OUT_BATCH(i * 3);
1151     R600_OUT_BATCH(sq_tex_sampler_word0);
1152     R600_OUT_BATCH(sq_tex_sampler_word1);
1153     R600_OUT_BATCH(sq_tex_sampler_word2);
1154     END_BATCH();
1155
1156 }
1157
1158 static inline void
1159 set_scissors(context_t *context, int x1, int y1, int x2, int y2)
1160 {
1161     BATCH_LOCALS(&context->radeon);
1162
1163     BEGIN_BATCH_NO_AUTOSTATE(17);
1164     R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1165     R600_OUT_BATCH((x1 << 0) | (y1 << 16));
1166     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1167
1168     R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 3);
1169     R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
1170     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL
1171     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1172
1173     R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1174     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1175     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1176
1177     /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
1178     R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL, 2 );
1179     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1180     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1181     END_BATCH();
1182
1183     COMMIT_BATCH();
1184
1185 }
1186
1187 static inline void
1188 set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y,
1189             int w, int h, int src_h, unsigned flip_y)
1190 {
1191     float *vb;
1192     radeon_bo_map(context->blit_bo, 1);
1193     vb = context->blit_bo->ptr;
1194
1195     vb[0] = (float)(dst_x);
1196     vb[1] = (float)(dst_y);
1197     vb[2] = (float)(src_x);
1198     vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y;
1199
1200     vb[4] = (float)(dst_x);
1201     vb[5] = (float)(dst_y + h);
1202     vb[6] = (float)(src_x);
1203     vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1204
1205     vb[8] = (float)(dst_x + w);
1206     vb[9] = (float)(dst_y + h);
1207     vb[10] = (float)(src_x + w);
1208     vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1209
1210     radeon_bo_unmap(context->blit_bo);
1211
1212 }
1213
1214 static inline void
1215 draw_auto(context_t *context)
1216 {
1217     BATCH_LOCALS(&context->radeon);
1218     uint32_t vgt_primitive_type = 0, vgt_index_type = 0, vgt_draw_initiator = 0, vgt_num_indices;
1219
1220     SETfield(vgt_primitive_type, DI_PT_RECTLIST,
1221              VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift,
1222              VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
1223     SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift,
1224              INDEX_TYPE_mask);
1225     SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift,
1226              MAJOR_MODE_mask);
1227     SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift,
1228              SOURCE_SELECT_mask);
1229
1230     vgt_num_indices = 3;
1231
1232     BEGIN_BATCH_NO_AUTOSTATE(10);
1233     // prim
1234     R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
1235     R600_OUT_BATCH(vgt_primitive_type);
1236     // index type
1237     R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
1238     R600_OUT_BATCH(vgt_index_type);
1239     // num instances
1240     R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
1241     R600_OUT_BATCH(1);
1242     //
1243     R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
1244     R600_OUT_BATCH(vgt_num_indices);
1245     R600_OUT_BATCH(vgt_draw_initiator);
1246
1247     END_BATCH();
1248     COMMIT_BATCH();
1249 }
1250
1251 static inline void
1252 set_default_state(context_t *context)
1253 {
1254     int ps_prio = 0;
1255     int vs_prio = 1;
1256     int gs_prio = 2;
1257     int es_prio = 3;
1258     int num_ps_gprs;
1259     int num_vs_gprs;
1260     int num_gs_gprs;
1261     int num_es_gprs;
1262     int num_temp_gprs;
1263     int num_ps_threads;
1264     int num_vs_threads;
1265     int num_gs_threads;
1266     int num_es_threads;
1267     int num_ps_stack_entries;
1268     int num_vs_stack_entries;
1269     int num_gs_stack_entries;
1270     int num_es_stack_entries;
1271     uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
1272     uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
1273     uint32_t ta_cntl_aux, db_watermarks, sq_dyn_gpr_cntl_ps_flush_req, db_debug;
1274     BATCH_LOCALS(&context->radeon);
1275
1276     switch (context->radeon.radeonScreen->chip_family) {
1277     case CHIP_FAMILY_R600:
1278             num_ps_gprs = 192;
1279             num_vs_gprs = 56;
1280             num_temp_gprs = 4;
1281             num_gs_gprs = 0;
1282             num_es_gprs = 0;
1283             num_ps_threads = 136;
1284             num_vs_threads = 48;
1285             num_gs_threads = 4;
1286             num_es_threads = 4;
1287             num_ps_stack_entries = 128;
1288             num_vs_stack_entries = 128;
1289             num_gs_stack_entries = 0;
1290             num_es_stack_entries = 0;
1291             break;
1292     case CHIP_FAMILY_RV630:
1293     case CHIP_FAMILY_RV635:
1294             num_ps_gprs = 84;
1295             num_vs_gprs = 36;
1296             num_temp_gprs = 4;
1297             num_gs_gprs = 0;
1298             num_es_gprs = 0;
1299             num_ps_threads = 144;
1300             num_vs_threads = 40;
1301             num_gs_threads = 4;
1302             num_es_threads = 4;
1303             num_ps_stack_entries = 40;
1304             num_vs_stack_entries = 40;
1305             num_gs_stack_entries = 32;
1306             num_es_stack_entries = 16;
1307             break;
1308     case CHIP_FAMILY_RV610:
1309     case CHIP_FAMILY_RV620:
1310     case CHIP_FAMILY_RS780:
1311     case CHIP_FAMILY_RS880:
1312     default:
1313             num_ps_gprs = 84;
1314             num_vs_gprs = 36;
1315             num_temp_gprs = 4;
1316             num_gs_gprs = 0;
1317             num_es_gprs = 0;
1318             num_ps_threads = 136;
1319             num_vs_threads = 48;
1320             num_gs_threads = 4;
1321             num_es_threads = 4;
1322             num_ps_stack_entries = 40;
1323             num_vs_stack_entries = 40;
1324             num_gs_stack_entries = 32;
1325             num_es_stack_entries = 16;
1326             break;
1327     case CHIP_FAMILY_RV670:
1328             num_ps_gprs = 144;
1329             num_vs_gprs = 40;
1330             num_temp_gprs = 4;
1331             num_gs_gprs = 0;
1332             num_es_gprs = 0;
1333             num_ps_threads = 136;
1334             num_vs_threads = 48;
1335             num_gs_threads = 4;
1336             num_es_threads = 4;
1337             num_ps_stack_entries = 40;
1338             num_vs_stack_entries = 40;
1339             num_gs_stack_entries = 32;
1340             num_es_stack_entries = 16;
1341             break;
1342     case CHIP_FAMILY_RV770:
1343             num_ps_gprs = 192;
1344             num_vs_gprs = 56;
1345             num_temp_gprs = 4;
1346             num_gs_gprs = 0;
1347             num_es_gprs = 0;
1348             num_ps_threads = 188;
1349             num_vs_threads = 60;
1350             num_gs_threads = 0;
1351             num_es_threads = 0;
1352             num_ps_stack_entries = 256;
1353             num_vs_stack_entries = 256;
1354             num_gs_stack_entries = 0;
1355             num_es_stack_entries = 0;
1356             break;
1357     case CHIP_FAMILY_RV730:
1358     case CHIP_FAMILY_RV740:
1359             num_ps_gprs = 84;
1360             num_vs_gprs = 36;
1361             num_temp_gprs = 4;
1362             num_gs_gprs = 0;
1363             num_es_gprs = 0;
1364             num_ps_threads = 188;
1365             num_vs_threads = 60;
1366             num_gs_threads = 0;
1367             num_es_threads = 0;
1368             num_ps_stack_entries = 128;
1369             num_vs_stack_entries = 128;
1370             num_gs_stack_entries = 0;
1371             num_es_stack_entries = 0;
1372             break;
1373     case CHIP_FAMILY_RV710:
1374             num_ps_gprs = 192;
1375             num_vs_gprs = 56;
1376             num_temp_gprs = 4;
1377             num_gs_gprs = 0;
1378             num_es_gprs = 0;
1379             num_ps_threads = 144;
1380             num_vs_threads = 48;
1381             num_gs_threads = 0;
1382             num_es_threads = 0;
1383             num_ps_stack_entries = 128;
1384             num_vs_stack_entries = 128;
1385             num_gs_stack_entries = 0;
1386             num_es_stack_entries = 0;
1387             break;
1388     }
1389
1390     sq_config = 0;
1391     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1392         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1393         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1394         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1395         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1396             CLEARbit(sq_config, VC_ENABLE_bit);
1397     else
1398             SETbit(sq_config, VC_ENABLE_bit);
1399     SETbit(sq_config, DX9_CONSTS_bit);
1400     SETbit(sq_config, ALU_INST_PREFER_VECTOR_bit);
1401     SETfield(sq_config, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1402     SETfield(sq_config, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
1403     SETfield(sq_config, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
1404     SETfield(sq_config, es_prio, ES_PRIO_shift, ES_PRIO_mask);
1405
1406     sq_gpr_resource_mgmt_1 = 0;
1407     SETfield(sq_gpr_resource_mgmt_1, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1408     SETfield(sq_gpr_resource_mgmt_1, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1409     SETfield(sq_gpr_resource_mgmt_1, num_temp_gprs,
1410              NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1411
1412     sq_gpr_resource_mgmt_2 = 0;
1413     SETfield(sq_gpr_resource_mgmt_2, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1414     SETfield(sq_gpr_resource_mgmt_2, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1415
1416     sq_thread_resource_mgmt = 0;
1417     SETfield(sq_thread_resource_mgmt, num_ps_threads,
1418              NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1419     SETfield(sq_thread_resource_mgmt, num_vs_threads,
1420              NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1421     SETfield(sq_thread_resource_mgmt, num_gs_threads,
1422              NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1423     SETfield(sq_thread_resource_mgmt, num_es_threads,
1424              NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1425
1426     sq_stack_resource_mgmt_1 = 0;
1427     SETfield(sq_stack_resource_mgmt_1, num_ps_stack_entries,
1428              NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1429     SETfield(sq_stack_resource_mgmt_1, num_vs_stack_entries,
1430              NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1431
1432     sq_stack_resource_mgmt_2 = 0;
1433     SETfield(sq_stack_resource_mgmt_2, num_gs_stack_entries,
1434              NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1435     SETfield(sq_stack_resource_mgmt_2, num_es_stack_entries,
1436              NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1437
1438     ta_cntl_aux = 0;
1439     SETfield(ta_cntl_aux, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1440     db_watermarks = 0;
1441     SETfield(db_watermarks, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1442     SETfield(db_watermarks, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1443     SETfield(db_watermarks, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1444     SETfield(db_watermarks, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1445     sq_dyn_gpr_cntl_ps_flush_req = 0;
1446     db_debug = 0;
1447     if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1448             SETfield(ta_cntl_aux, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1449             db_debug = 0x82000000;
1450             SETfield(db_watermarks, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1451     } else {
1452             SETfield(ta_cntl_aux, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1453             SETfield(db_watermarks, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1454             SETbit(sq_dyn_gpr_cntl_ps_flush_req, VS_PC_LIMIT_ENABLE_bit);
1455     }
1456
1457     BEGIN_BATCH_NO_AUTOSTATE(120);
1458     R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
1459     R600_OUT_BATCH(sq_config);
1460     R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
1461     R600_OUT_BATCH(sq_gpr_resource_mgmt_2);
1462     R600_OUT_BATCH(sq_thread_resource_mgmt);
1463     R600_OUT_BATCH(sq_stack_resource_mgmt_1);
1464     R600_OUT_BATCH(sq_stack_resource_mgmt_2);
1465
1466     R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, ta_cntl_aux);
1467     R600_OUT_BATCH_REGVAL(VC_ENHANCE, 0);
1468     R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, sq_dyn_gpr_cntl_ps_flush_req);
1469     R600_OUT_BATCH_REGVAL(DB_DEBUG, db_debug);
1470     R600_OUT_BATCH_REGVAL(DB_WATERMARKS, db_watermarks);
1471
1472     R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
1473     R600_OUT_BATCH(0);
1474     R600_OUT_BATCH(0);
1475     R600_OUT_BATCH(0);
1476     R600_OUT_BATCH(0);
1477     R600_OUT_BATCH(0);
1478     R600_OUT_BATCH(0);
1479     R600_OUT_BATCH(0);
1480     R600_OUT_BATCH(0);
1481     R600_OUT_BATCH(0);
1482
1483     R600_OUT_BATCH_REGVAL(CB_CLRCMP_CONTROL,
1484                          (CLRCMP_SEL_SRC << CLRCMP_FCN_SEL_shift));
1485     R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC, 0);
1486     R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC, 0);
1487     R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, 0);
1488     R600_OUT_BATCH_REGVAL(CB_SHADER_MASK, (OUTPUT0_ENABLE_mask));
1489     R600_OUT_BATCH_REGVAL(CB_TARGET_MASK, (TARGET0_ENABLE_mask));
1490     R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit));
1491     R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, (0xcc << ROP3_shift));
1492
1493     R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, VTX_XY_FMT_bit);
1494     R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, 0);
1495     R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, CLIP_DISABLE_bit);
1496     R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, (FACE_bit) |
1497         (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) |
1498         (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift));
1499     R600_OUT_BATCH_REGVAL(PA_SU_VTX_CNTL, (PIX_CENTER_bit) |
1500         (X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
1501         (X_1_256TH << QUANT_MODE_shift));
1502     R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, 0);
1503
1504     R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
1505     R600_OUT_BATCH(0xffffff);
1506     R600_OUT_BATCH(0);
1507     R600_OUT_BATCH(0);
1508     R600_OUT_BATCH(0);
1509
1510     R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
1511     R600_OUT_BATCH(0);
1512     R600_OUT_BATCH(0);
1513     R600_OUT_BATCH(0);
1514     R600_OUT_BATCH(0);
1515     R600_OUT_BATCH(0);
1516     R600_OUT_BATCH(0);
1517     R600_OUT_BATCH(0);
1518     R600_OUT_BATCH(0);
1519     R600_OUT_BATCH(0);
1520     R600_OUT_BATCH(0);
1521     R600_OUT_BATCH(0);
1522     R600_OUT_BATCH(0);
1523     R600_OUT_BATCH(0);
1524
1525     R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, 0);
1526     R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, 0);
1527     R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, 0);
1528     R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, 0);
1529
1530     R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
1531     R600_OUT_BATCH(0);
1532     R600_OUT_BATCH(0);
1533     R600_OUT_BATCH(0);
1534
1535     R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, 0);
1536     R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, 0);
1537
1538     END_BATCH();
1539     COMMIT_BATCH();
1540 }
1541
1542 static GLboolean validate_buffers(context_t *rmesa,
1543                                   struct radeon_bo *src_bo,
1544                                   struct radeon_bo *dst_bo)
1545 {
1546     int ret;
1547
1548     radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
1549
1550     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1551                                         src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
1552     if (ret)
1553         return GL_FALSE;
1554
1555     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1556                                         dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
1557     if (ret)
1558         return GL_FALSE;
1559
1560     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1561                                         rmesa->blit_bo,
1562                                         RADEON_GEM_DOMAIN_GTT, 0);
1563     if (ret)
1564         return GL_FALSE;
1565
1566     return GL_TRUE;
1567 }
1568
1569 unsigned r600_blit(GLcontext *ctx,
1570                    struct radeon_bo *src_bo,
1571                    intptr_t src_offset,
1572                    gl_format src_mesaformat,
1573                    unsigned src_pitch,
1574                    unsigned src_width,
1575                    unsigned src_height,
1576                    unsigned src_x,
1577                    unsigned src_y,
1578                    struct radeon_bo *dst_bo,
1579                    intptr_t dst_offset,
1580                    gl_format dst_mesaformat,
1581                    unsigned dst_pitch,
1582                    unsigned dst_width,
1583                    unsigned dst_height,
1584                    unsigned dst_x,
1585                    unsigned dst_y,
1586                    unsigned w,
1587                    unsigned h,
1588                    unsigned flip_y)
1589 {
1590     context_t *context = R700_CONTEXT(ctx);
1591     int id = 0;
1592
1593     if (!r600_check_blit(dst_mesaformat))
1594         return GL_FALSE;
1595
1596     if (src_bo == dst_bo) {
1597         return GL_FALSE;
1598     }
1599
1600     if (src_offset % 256 || dst_offset % 256) {
1601         return GL_FALSE;
1602     }
1603
1604     if (0) {
1605         fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
1606                 src_width, src_height, src_pitch,
1607                 _mesa_format_row_stride(src_mesaformat, src_width),
1608                 _mesa_get_format_name(src_mesaformat));
1609         fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n",
1610                 dst_width, dst_height,
1611                 _mesa_format_row_stride(dst_mesaformat, dst_width),
1612                 _mesa_get_format_name(dst_mesaformat));
1613     }
1614
1615     /* Flush is needed to make sure that source buffer has correct data */
1616     radeonFlush(ctx);
1617
1618     rcommonEnsureCmdBufSpace(&context->radeon, 311, __FUNCTION__);
1619
1620     /* load shaders */
1621     load_shaders(context->radeon.glCtx);
1622
1623     if (!validate_buffers(context, src_bo, dst_bo))
1624         return GL_FALSE;
1625
1626     /* set clear state */
1627     /* 120 */
1628     set_default_state(context);
1629
1630     /* shaders */
1631     /* 72 */
1632     set_shaders(context);
1633
1634     /* src */
1635     /* 20 */
1636     set_tex_resource(context, src_mesaformat, src_bo,
1637                      src_width, src_height, src_pitch, src_offset);
1638
1639     /* 5 */
1640     set_tex_sampler(context);
1641
1642     /* dst */
1643     /* 31 */
1644     set_render_target(context, dst_bo, dst_mesaformat,
1645                       dst_pitch, dst_width, dst_height, dst_offset);
1646     /* scissors */
1647     /* 17 */
1648     set_scissors(context, dst_x, dst_y, dst_x + dst_width, dst_y + dst_height);
1649
1650     set_vb_data(context, src_x, src_y, dst_x, dst_y, w, h, src_height, flip_y);
1651     /* Vertex buffer setup */
1652     /* 24 */
1653     set_vtx_resource(context);
1654
1655     /* draw */
1656     /* 10 */
1657     draw_auto(context);
1658
1659     /* 7 */
1660     r700SyncSurf(context, dst_bo, 0,
1661                  RADEON_GEM_DOMAIN_VRAM|RADEON_GEM_DOMAIN_GTT,
1662                  CB_ACTION_ENA_bit | (1 << (id + 6)));
1663
1664     /* 5 */
1665     /* XXX drm should handle this in fence submit */
1666     r700WaitForIdleClean(context);
1667
1668     radeonFlush(ctx);
1669
1670     return GL_TRUE;
1671 }