src/mesa/drivers/dri/r600/r600_tex.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27 */
  28
  29 /**
  30  * \file
  31  *
  32  * \author Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/imports.h"
  37 #include "main/colormac.h"
  38 #include "main/context.h"
  39 #include "main/enums.h"
  40 #include "main/image.h"
  41 #include "main/mipmap.h"
  42 #include "main/simple_list.h"
  43 #include "main/texstore.h"
  44 #include "main/texobj.h"
  45
  46 #include "texmem.h"
  47
  48 #include "r600_context.h"
  49 #include "radeon_mipmap_tree.h"
  50 #include "r600_tex.h"
  51
  52
  53 static unsigned int translate_wrap_mode(GLenum wrapmode)
  54 {
  55         switch(wrapmode) {
  56         case GL_REPEAT: return SQ_TEX_WRAP;
  57         case GL_CLAMP: return SQ_TEX_CLAMP_HALF_BORDER;
  58         case GL_CLAMP_TO_EDGE: return SQ_TEX_CLAMP_LAST_TEXEL;
  59         case GL_CLAMP_TO_BORDER: return SQ_TEX_CLAMP_BORDER;
  60         case GL_MIRRORED_REPEAT: return SQ_TEX_MIRROR;
  61         case GL_MIRROR_CLAMP_EXT: return SQ_TEX_MIRROR_ONCE_HALF_BORDER;
  62         case GL_MIRROR_CLAMP_TO_EDGE_EXT: return SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
  63         case GL_MIRROR_CLAMP_TO_BORDER_EXT: return SQ_TEX_MIRROR_ONCE_BORDER;
  64         default:
  65                 radeon_error("bad wrap mode in %s", __FUNCTION__);
  66                 return 0;
  67         }
  68 }
  69
  70
  71 /**
  72  * Update the cached hardware registers based on the current texture wrap modes.
  73  *
  74  * \param t Texture object whose wrap modes are to be set
  75  */
  76 static void r600UpdateTexWrap(radeonTexObjPtr t)
  77 {
  78         struct gl_texture_object *tObj = &t->base;
  79
  80         SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapS),
  81                  SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
  82
  83         if (tObj->Target != GL_TEXTURE_1D) {
  84                 SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapT),
  85                          CLAMP_Y_shift, CLAMP_Y_mask);
  86
  87                 if (tObj->Target == GL_TEXTURE_3D)
  88                         SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapR),
  89                                  CLAMP_Z_shift, CLAMP_Z_mask);
  90         }
  91 }
  92
  93 static void r600SetTexDefaultState(radeonTexObjPtr t)
  94 {
  95         /* Init text object to default states. */
  96         t->SQ_TEX_RESOURCE0              = 0;
  97         SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
  98         SETfield(t->SQ_TEX_RESOURCE0, ARRAY_LINEAR_GENERAL,
  99                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 100         CLEARbit(t->SQ_TEX_RESOURCE0, TILE_TYPE_bit);
 101
 102         t->SQ_TEX_RESOURCE1                = 0;
 103         SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 104                  SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 105
 106         t->SQ_TEX_RESOURCE2                = 0;
 107         t->SQ_TEX_RESOURCE3                = 0;
 108
 109         t->SQ_TEX_RESOURCE4                   = 0;
 110         SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
 111                  FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 112         SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
 113                  FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 114         SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
 115                  FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 116         SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
 117                  FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 118         SETfield(t->SQ_TEX_RESOURCE4, SQ_NUM_FORMAT_NORM,
 119                  SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask);
 120         CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit);
 121         CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
 122         SETfield(t->SQ_TEX_RESOURCE4, SQ_ENDIAN_NONE,
 123                  SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask);
 124         SETfield(t->SQ_TEX_RESOURCE4, 1, REQUEST_SIZE_shift, REQUEST_SIZE_mask);
 125         SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
 126                  SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift,
 127                  SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 128         SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
 129                  SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift,
 130                  SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 131         SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
 132                  SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift,
 133                  SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 134         SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
 135                  SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift,
 136                  SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 137         SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask); /* mip-maps */
 138
 139         t->SQ_TEX_RESOURCE5 = 0;
 140         t->SQ_TEX_RESOURCE6 = 0;
 141
 142         SETfield(t->SQ_TEX_RESOURCE6, SQ_TEX_VTX_VALID_TEXTURE,
 143                  SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
 144
 145         /* Initialize sampler registers */
 146         t->SQ_TEX_SAMPLER0                           = 0;
 147         SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift,
 148                  SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
 149         SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP, CLAMP_Y_shift, CLAMP_Y_mask);
 150         SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP, CLAMP_Z_shift, CLAMP_Z_mask);
 151         SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_XY_FILTER_POINT, XY_MAG_FILTER_shift, XY_MAG_FILTER_mask);
 152         SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_XY_FILTER_POINT, XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 153         SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_Z_FILTER_NONE, Z_FILTER_shift, Z_FILTER_mask);
 154         SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_Z_FILTER_NONE, MIP_FILTER_shift, MIP_FILTER_mask);
 155         SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_TRANS_BLACK, BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask);
 156
 157         t->SQ_TEX_SAMPLER1                           = 0;
 158         SETfield(t->SQ_TEX_SAMPLER1, 0x3ff, MAX_LOD_shift, MAX_LOD_mask);
 159
 160         t->SQ_TEX_SAMPLER2                          = 0;
 161         SETbit(t->SQ_TEX_SAMPLER2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
 162 }
 163
 164
 165 #if 0
 166 static GLuint aniso_filter(GLfloat anisotropy)
 167 {
 168         if (anisotropy >= 16.0) {
 169                 return R300_TX_MAX_ANISO_16_TO_1;
 170         } else if (anisotropy >= 8.0) {
 171                 return R300_TX_MAX_ANISO_8_TO_1;
 172         } else if (anisotropy >= 4.0) {
 173                 return R300_TX_MAX_ANISO_4_TO_1;
 174         } else if (anisotropy >= 2.0) {
 175                 return R300_TX_MAX_ANISO_2_TO_1;
 176         } else {
 177                 return R300_TX_MAX_ANISO_1_TO_1;
 178         }
 179         return 0;
 180 }
 181 #endif
 182
 183 /**
 184  * Set the texture magnification and minification modes.
 185  *
 186  * \param t Texture whose filter modes are to be set
 187  * \param minf Texture minification mode
 188  * \param magf Texture magnification mode
 189  * \param anisotropy Maximum anisotropy level
 190  */
 191 static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy)
 192 {
 193         /* Force revalidation to account for switches from/to mipmapping. */
 194         t->validated = GL_FALSE;
 195
 196         /* Note that EXT_texture_filter_anisotropic is extremely vague about
 197          * how anisotropic filtering interacts with the "normal" filter modes.
 198          * When anisotropic filtering is enabled, we override min and mag
 199          * filter settings completely. This includes driconf's settings.
 200          */
 201         if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) {
 202                 /*t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO
 203                         | R300_TX_MIN_FILTER_ANISO
 204                         | R300_TX_MIN_FILTER_MIP_LINEAR
 205                         | aniso_filter(anisotropy);*/
 206                 radeon_print(RADEON_TEXTURE, RADEON_NORMAL, "Using maximum anisotropy of %f\n", anisotropy);
 207                 return;
 208         }
 209
 210         switch (minf) {
 211         case GL_NEAREST:
 212                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
 213                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 214                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None,
 215                          MIP_FILTER_shift, MIP_FILTER_mask);
 216                 break;
 217         case GL_LINEAR:
 218                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
 219                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 220                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None,
 221                          MIP_FILTER_shift, MIP_FILTER_mask);
 222                 break;
 223         case GL_NEAREST_MIPMAP_NEAREST:
 224                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
 225                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 226                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point,
 227                          MIP_FILTER_shift, MIP_FILTER_mask);
 228                 break;
 229         case GL_NEAREST_MIPMAP_LINEAR:
 230                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
 231                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 232                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear,
 233                          MIP_FILTER_shift, MIP_FILTER_mask);
 234                 break;
 235         case GL_LINEAR_MIPMAP_NEAREST:
 236                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
 237                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 238                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point,
 239                          MIP_FILTER_shift, MIP_FILTER_mask);
 240                 break;
 241         case GL_LINEAR_MIPMAP_LINEAR:
 242                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
 243                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 244                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear,
 245                          MIP_FILTER_shift, MIP_FILTER_mask);
 246                 break;
 247         }
 248
 249         /* Note we don't have 3D mipmaps so only use the mag filter setting
 250          * to set the 3D texture filter mode.
 251          */
 252         switch (magf) {
 253         case GL_NEAREST:
 254                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
 255                          XY_MAG_FILTER_shift, XY_MAG_FILTER_mask);
 256                 break;
 257         case GL_LINEAR:
 258                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
 259                          XY_MAG_FILTER_shift, XY_MAG_FILTER_mask);
 260                 break;
 261         }
 262 }
 263
 264 static void r600SetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4])
 265 {
 266         t->TD_PS_SAMPLER0_BORDER_ALPHA = *((uint32_t*)&(color[3]));
 267         t->TD_PS_SAMPLER0_BORDER_RED = *((uint32_t*)&(color[2]));
 268         t->TD_PS_SAMPLER0_BORDER_GREEN = *((uint32_t*)&(color[1]));
 269         t->TD_PS_SAMPLER0_BORDER_BLUE = *((uint32_t*)&(color[0]));
 270         SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_REGISTER,
 271                  BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask);
 272 }
 273
 274 /**
 275  * Changes variables and flags for a state update, which will happen at the
 276  * next UpdateTextureState
 277  */
 278
 279 static void r600TexParameter(struct gl_context * ctx, GLenum target,
 280                              struct gl_texture_object *texObj,
 281                              GLenum pname, const GLfloat * params)
 282 {
 283         radeonTexObj* t = radeon_tex_obj(texObj);
 284         GLenum baseFormat;
 285
 286         radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_VERBOSE,
 287                         "%s( %s )\n", __FUNCTION__,
 288                         _mesa_lookup_enum_by_nr(pname));
 289
 290         switch (pname) {
 291         case GL_TEXTURE_MIN_FILTER:
 292         case GL_TEXTURE_MAG_FILTER:
 293         case GL_TEXTURE_MAX_ANISOTROPY_EXT:
 294                 r600SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy);
 295                 break;
 296
 297         case GL_TEXTURE_WRAP_S:
 298         case GL_TEXTURE_WRAP_T:
 299         case GL_TEXTURE_WRAP_R:
 300                 r600UpdateTexWrap(t);
 301                 break;
 302
 303         case GL_TEXTURE_BORDER_COLOR:
 304                 r600SetTexBorderColor(t, texObj->BorderColor.f);
 305                 break;
 306
 307         case GL_TEXTURE_BASE_LEVEL:
 308         case GL_TEXTURE_MAX_LEVEL:
 309         case GL_TEXTURE_MIN_LOD:
 310         case GL_TEXTURE_MAX_LOD:
 311                 t->validated = GL_FALSE;
 312                 break;
 313
 314         case GL_DEPTH_TEXTURE_MODE:
 315                 if (!texObj->Image[0][texObj->BaseLevel])
 316                         return;
 317                 baseFormat = texObj->Image[0][texObj->BaseLevel]->_BaseFormat;
 318                 if (baseFormat == GL_DEPTH_COMPONENT ||
 319                     baseFormat == GL_DEPTH_STENCIL) {
 320                         r600SetDepthTexMode(texObj);
 321                         break;
 322                 } else {
 323                         /* If the texture isn't a depth texture, changing this
 324                          * state won't cause any changes to the hardware.
 325                          * Don't force a flush of texture state.
 326                          */
 327                         return;
 328                 }
 329
 330         default:
 331                 return;
 332         }
 333 }
 334
 335 static void r600DeleteTexture(struct gl_context * ctx, struct gl_texture_object *texObj)
 336 {
 337         context_t* rmesa = R700_CONTEXT(ctx);
 338         radeonTexObj* t = radeon_tex_obj(texObj);
 339
 340         radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL,
 341                 "%s( %p (target = %s) )\n", __FUNCTION__,
 342                         (void *)texObj,
 343                         _mesa_lookup_enum_by_nr(texObj->Target));
 344
 345         if (rmesa) {
 346                 int i;
 347                 radeon_firevertices(&rmesa->radeon);
 348
 349                 for(i = 0; i < R700_MAX_TEXTURE_UNITS; ++i)
 350                         if (rmesa->hw.textures[i] == t)
 351                                 rmesa->hw.textures[i] = 0;
 352         }
 353
 354         if (t->bo) {
 355                 radeon_bo_unref(t->bo);
 356                 t->bo = NULL;
 357         }
 358
 359         radeon_miptree_unreference(&t->mt);
 360
 361         _mesa_delete_texture_object(ctx, texObj);
 362 }
 363
 364 /**
 365  * Allocate a new texture object.
 366  * Called via ctx->Driver.NewTextureObject.
 367  * Note: this function will be called during context creation to
 368  * allocate the default texture objects.
 369  * Fixup MaxAnisotropy according to user preference.
 370  */
 371 static struct gl_texture_object *r600NewTextureObject(struct gl_context * ctx,
 372                                                       GLuint name,
 373                                                       GLenum target)
 374 {
 375         context_t* rmesa = R700_CONTEXT(ctx);
 376         radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
 377
 378
 379         radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL,
 380                 "%s( %p (target = %s) )\n", __FUNCTION__,
 381                         t, _mesa_lookup_enum_by_nr(target));
 382
 383         _mesa_initialize_texture_object(&t->base, name, target);
 384         t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
 385
 386         /* Initialize hardware state */
 387         r600SetTexDefaultState(t);
 388         r600UpdateTexWrap(t);
 389         r600SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy);
 390         r600SetTexBorderColor(t, t->base.BorderColor.f);
 391
 392         return &t->base;
 393 }
 394
 395 unsigned r600IsFormatRenderable(gl_format mesa_format)
 396 {
 397         switch (mesa_format) {
 398         case MESA_FORMAT_RGBA8888:
 399         case MESA_FORMAT_SIGNED_RGBA8888:
 400         case MESA_FORMAT_RGBA8888_REV:
 401         case MESA_FORMAT_SIGNED_RGBA8888_REV:
 402         case MESA_FORMAT_ARGB8888:
 403         case MESA_FORMAT_XRGB8888:
 404         case MESA_FORMAT_ARGB8888_REV:
 405         case MESA_FORMAT_XRGB8888_REV:
 406         case MESA_FORMAT_RGB565:
 407         case MESA_FORMAT_RGB565_REV:
 408         case MESA_FORMAT_ARGB4444:
 409         case MESA_FORMAT_ARGB4444_REV:
 410         case MESA_FORMAT_ARGB1555:
 411         case MESA_FORMAT_ARGB1555_REV:
 412         case MESA_FORMAT_AL88:
 413         case MESA_FORMAT_AL88_REV:
 414         case MESA_FORMAT_RGB332:
 415         case MESA_FORMAT_A8:
 416         case MESA_FORMAT_I8:
 417         case MESA_FORMAT_CI8:
 418         case MESA_FORMAT_L8:
 419         case MESA_FORMAT_RGBA_FLOAT32:
 420         case MESA_FORMAT_RGBA_FLOAT16:
 421         case MESA_FORMAT_ALPHA_FLOAT32:
 422         case MESA_FORMAT_ALPHA_FLOAT16:
 423         case MESA_FORMAT_LUMINANCE_FLOAT32:
 424         case MESA_FORMAT_LUMINANCE_FLOAT16:
 425         case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 426         case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 427         case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 428         case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 429         case MESA_FORMAT_X8_Z24:
 430         case MESA_FORMAT_S8_Z24:
 431         case MESA_FORMAT_Z24_S8:
 432         case MESA_FORMAT_Z16:
 433         case MESA_FORMAT_Z32:
 434         case MESA_FORMAT_SARGB8:
 435         case MESA_FORMAT_SLA8:
 436         case MESA_FORMAT_SL8:
 437                 return 1;
 438         default:
 439                 return 0;
 440         }
 441 }
 442
 443 void r600InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
 444 {
 445         /* Note: we only plug in the functions we implement in the driver
 446          * since _mesa_init_driver_functions() was already called.
 447          */
 448         functions->NewTextureImage = radeonNewTextureImage;
 449         functions->FreeTexImageData = radeonFreeTexImageData;
 450         functions->MapTexture = radeonMapTexture;
 451         functions->UnmapTexture = radeonUnmapTexture;
 452
 453         functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa;
 454         functions->TexImage1D = radeonTexImage1D;
 455         functions->TexImage2D = radeonTexImage2D;
 456         functions->TexImage3D = radeonTexImage3D;
 457         functions->TexSubImage1D = radeonTexSubImage1D;
 458         functions->TexSubImage2D = radeonTexSubImage2D;
 459         functions->TexSubImage3D = radeonTexSubImage3D;
 460         functions->GetTexImage = radeonGetTexImage;
 461         functions->GetCompressedTexImage = radeonGetCompressedTexImage;
 462         functions->NewTextureObject = r600NewTextureObject;
 463         functions->DeleteTexture = r600DeleteTexture;
 464         functions->IsTextureResident = driIsTextureResident;
 465
 466         functions->TexParameter = r600TexParameter;
 467
 468         functions->CompressedTexImage2D = radeonCompressedTexImage2D;
 469         functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D;
 470
 471         if (radeon->radeonScreen->kernel_mm) {
 472                 functions->CopyTexImage2D = radeonCopyTexImage2D;
 473                 functions->CopyTexSubImage2D = radeonCopyTexSubImage2D;
 474         }
 475
 476         functions->GenerateMipmap = radeonGenerateMipmap;
 477
 478 #if FEATURE_OES_EGL_image
 479         functions->EGLImageTargetTexture2D = radeon_image_target_texture_2d;
 480 #endif
 481
 482         driInitTextureFormats();
 483 }