Merge branch '7.8' into master
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/imports.h"
30 #include "main/enums.h"
31 #include "main/macros.h"
32 #include "main/context.h"
33 #include "main/dd.h"
34 #include "main/simple_list.h"
35
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast/swrast.h"
39 #include "swrast_setup/swrast_setup.h"
40 #include "main/api_arrayelt.h"
41 #include "main/framebuffer.h"
42 #include "drivers/common/meta.h"
43
44 #include "shader/prog_parameter.h"
45 #include "shader/prog_statevars.h"
46 #include "vbo/vbo.h"
47
48 #include "r600_context.h"
49
50 #include "r700_state.h"
51
52 #include "r700_fragprog.h"
53 #include "r700_vertprog.h"
54
55 void r600UpdateTextureState(GLcontext * ctx);
56 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
57 static void r700UpdatePolygonMode(GLcontext * ctx);
58 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
59 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
60 static void r700UpdateWindow(GLcontext * ctx, int id);
61
62 void r700UpdateShaders(GLcontext * ctx)
63 {
64 context_t *context = R700_CONTEXT(ctx);
65
66 /* should only happenen once, just after context is created */
67 /* TODO: shouldn't we fallback to sw here? */
68 if (!ctx->FragmentProgram._Current) {
69 fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
70 return;
71 }
72
73 r700SelectFragmentShader(ctx);
74
75 r700SelectVertexShader(ctx);
76 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
77 context->radeon.NewGLState = 0;
78 }
79
80 /*
81 * To correctly position primitives:
82 */
83 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
84 {
85 context_t *context = R700_CONTEXT(ctx);
86 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
87 __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
88 GLfloat xoffset = (GLfloat) dPriv->x;
89 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
90 const GLfloat *v = ctx->Viewport._WindowMap.m;
91 int id = 0;
92
93 GLfloat tx = v[MAT_TX] + xoffset;
94 GLfloat ty = (-v[MAT_TY]) + yoffset;
95
96 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
97 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
98 /* Note: this should also modify whatever data the context reset
99 * code uses...
100 */
101 R600_STATECHANGE(context, vpt);
102 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
103 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
104 }
105
106 radeonUpdateScissor(ctx);
107 }
108
109 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
110 {
111 struct r700_fragment_program *fp =
112 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
113 struct gl_program_parameter_list *paramList;
114
115 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
116 return;
117
118 if (!ctx->FragmentProgram._Current || !fp)
119 return;
120
121 paramList = ctx->FragmentProgram._Current->Base.Parameters;
122
123 if (!paramList)
124 return;
125
126 _mesa_load_state_parameters(ctx, paramList);
127
128 }
129
130 /**
131 * Called by Mesa after an internal state update.
132 */
133 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
134 {
135 context_t *context = R700_CONTEXT(ctx);
136
137 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
138
139 _swrast_InvalidateState(ctx, new_state);
140 _swsetup_InvalidateState(ctx, new_state);
141 _vbo_InvalidateState(ctx, new_state);
142 _tnl_InvalidateState(ctx, new_state);
143 _ae_invalidate_state(ctx, new_state);
144
145 if (new_state & _NEW_BUFFERS) {
146 _mesa_update_framebuffer(ctx);
147 /* this updates the DrawBuffer's Width/Height if it's a FBO */
148 _mesa_update_draw_buffer_bounds(ctx);
149
150 R600_STATECHANGE(context, cb_target);
151 R600_STATECHANGE(context, db_target);
152 }
153
154 if (new_state & (_NEW_LIGHT)) {
155 R600_STATECHANGE(context, su);
156 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
157 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
158 else
159 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
160 }
161
162 r700UpdateStateParameters(ctx, new_state);
163
164 R600_STATECHANGE(context, cl);
165 R600_STATECHANGE(context, spi);
166
167 if(GL_TRUE == r700->bEnablePerspective)
168 {
169 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
170 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
171 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
172
173 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
174
175 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
176 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
177 }
178 else
179 {
180 /* For orthogonal case. */
181 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
182 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
183
184 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
185
186 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
187 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
188 }
189
190 context->radeon.NewGLState |= new_state;
191 }
192
193 static void r700SetDBRenderState(GLcontext * ctx)
194 {
195 context_t *context = R700_CONTEXT(ctx);
196 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
197 struct r700_fragment_program *fp = (struct r700_fragment_program *)
198 (ctx->FragmentProgram._Current);
199
200 R600_STATECHANGE(context, db);
201
202 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
203 SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask);
204 /* XXX need to enable htile for hiz/s */
205 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
206 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
207 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
208
209 if (context->radeon.query.current)
210 {
211 SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
212 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
213 {
214 SETbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
215 }
216 }
217 else
218 {
219 CLEARbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
220 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
221 {
222 CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
223 }
224 }
225
226 if (fp)
227 {
228 if (fp->r700Shader.killIsUsed)
229 {
230 SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
231 }
232 else
233 {
234 CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
235 }
236
237 if (fp->r700Shader.depthIsExported)
238 {
239 SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
240 }
241 else
242 {
243 CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
244 }
245 }
246 }
247
248 void r700UpdateShaderStates(GLcontext * ctx)
249 {
250 r700SetDBRenderState(ctx);
251 r600UpdateTextureState(ctx);
252 }
253
254 static void r700SetDepthState(GLcontext * ctx)
255 {
256 context_t *context = R700_CONTEXT(ctx);
257 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
258
259 R600_STATECHANGE(context, db);
260
261 if (ctx->Depth.Test)
262 {
263 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
264 if (ctx->Depth.Mask)
265 {
266 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
267 }
268 else
269 {
270 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
271 }
272
273 switch (ctx->Depth.Func)
274 {
275 case GL_NEVER:
276 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
277 ZFUNC_shift, ZFUNC_mask);
278 break;
279 case GL_LESS:
280 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
281 ZFUNC_shift, ZFUNC_mask);
282 break;
283 case GL_EQUAL:
284 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
285 ZFUNC_shift, ZFUNC_mask);
286 break;
287 case GL_LEQUAL:
288 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
289 ZFUNC_shift, ZFUNC_mask);
290 break;
291 case GL_GREATER:
292 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
293 ZFUNC_shift, ZFUNC_mask);
294 break;
295 case GL_NOTEQUAL:
296 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
297 ZFUNC_shift, ZFUNC_mask);
298 break;
299 case GL_GEQUAL:
300 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
301 ZFUNC_shift, ZFUNC_mask);
302 break;
303 case GL_ALWAYS:
304 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
305 ZFUNC_shift, ZFUNC_mask);
306 break;
307 default:
308 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
309 ZFUNC_shift, ZFUNC_mask);
310 break;
311 }
312 }
313 else
314 {
315 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
316 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
317 }
318 }
319
320 static void r700SetAlphaState(GLcontext * ctx)
321 {
322 context_t *context = R700_CONTEXT(ctx);
323 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
324 uint32_t alpha_func = REF_ALWAYS;
325 GLboolean really_enabled = ctx->Color.AlphaEnabled;
326
327 R600_STATECHANGE(context, sx);
328
329 switch (ctx->Color.AlphaFunc) {
330 case GL_NEVER:
331 alpha_func = REF_NEVER;
332 break;
333 case GL_LESS:
334 alpha_func = REF_LESS;
335 break;
336 case GL_EQUAL:
337 alpha_func = REF_EQUAL;
338 break;
339 case GL_LEQUAL:
340 alpha_func = REF_LEQUAL;
341 break;
342 case GL_GREATER:
343 alpha_func = REF_GREATER;
344 break;
345 case GL_NOTEQUAL:
346 alpha_func = REF_NOTEQUAL;
347 break;
348 case GL_GEQUAL:
349 alpha_func = REF_GEQUAL;
350 break;
351 case GL_ALWAYS:
352 /*alpha_func = REF_ALWAYS; */
353 really_enabled = GL_FALSE;
354 break;
355 }
356
357 if (really_enabled) {
358 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
359 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
360 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
361 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
362 } else {
363 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
364 }
365
366 }
367
368 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
369 {
370 (void)func;
371 (void)ref;
372 r700SetAlphaState(ctx);
373 }
374
375
376 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
377 {
378 context_t *context = R700_CONTEXT(ctx);
379 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
380
381 R600_STATECHANGE(context, blnd_clr);
382
383 r700->CB_BLEND_RED.f32All = cf[0];
384 r700->CB_BLEND_GREEN.f32All = cf[1];
385 r700->CB_BLEND_BLUE.f32All = cf[2];
386 r700->CB_BLEND_ALPHA.f32All = cf[3];
387 }
388
389 static int blend_factor(GLenum factor, GLboolean is_src)
390 {
391 switch (factor) {
392 case GL_ZERO:
393 return BLEND_ZERO;
394 break;
395 case GL_ONE:
396 return BLEND_ONE;
397 break;
398 case GL_DST_COLOR:
399 return BLEND_DST_COLOR;
400 break;
401 case GL_ONE_MINUS_DST_COLOR:
402 return BLEND_ONE_MINUS_DST_COLOR;
403 break;
404 case GL_SRC_COLOR:
405 return BLEND_SRC_COLOR;
406 break;
407 case GL_ONE_MINUS_SRC_COLOR:
408 return BLEND_ONE_MINUS_SRC_COLOR;
409 break;
410 case GL_SRC_ALPHA:
411 return BLEND_SRC_ALPHA;
412 break;
413 case GL_ONE_MINUS_SRC_ALPHA:
414 return BLEND_ONE_MINUS_SRC_ALPHA;
415 break;
416 case GL_DST_ALPHA:
417 return BLEND_DST_ALPHA;
418 break;
419 case GL_ONE_MINUS_DST_ALPHA:
420 return BLEND_ONE_MINUS_DST_ALPHA;
421 break;
422 case GL_SRC_ALPHA_SATURATE:
423 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
424 break;
425 case GL_CONSTANT_COLOR:
426 return BLEND_CONSTANT_COLOR;
427 break;
428 case GL_ONE_MINUS_CONSTANT_COLOR:
429 return BLEND_ONE_MINUS_CONSTANT_COLOR;
430 break;
431 case GL_CONSTANT_ALPHA:
432 return BLEND_CONSTANT_ALPHA;
433 break;
434 case GL_ONE_MINUS_CONSTANT_ALPHA:
435 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
436 break;
437 default:
438 fprintf(stderr, "unknown blend factor %x\n", factor);
439 return (is_src) ? BLEND_ONE : BLEND_ZERO;
440 break;
441 }
442 }
443
444 static void r700SetBlendState(GLcontext * ctx)
445 {
446 context_t *context = R700_CONTEXT(ctx);
447 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
448 int id = 0;
449 uint32_t blend_reg = 0, eqn, eqnA;
450
451 R600_STATECHANGE(context, blnd);
452
453 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
454 SETfield(blend_reg,
455 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
456 SETfield(blend_reg,
457 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
458 SETfield(blend_reg,
459 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
460 SETfield(blend_reg,
461 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
462 SETfield(blend_reg,
463 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
464 SETfield(blend_reg,
465 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
466 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
467 r700->CB_BLEND_CONTROL.u32All = blend_reg;
468 else
469 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
470 return;
471 }
472
473 SETfield(blend_reg,
474 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
475 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
476 SETfield(blend_reg,
477 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
478 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
479
480 switch (ctx->Color.BlendEquationRGB) {
481 case GL_FUNC_ADD:
482 eqn = COMB_DST_PLUS_SRC;
483 break;
484 case GL_FUNC_SUBTRACT:
485 eqn = COMB_SRC_MINUS_DST;
486 break;
487 case GL_FUNC_REVERSE_SUBTRACT:
488 eqn = COMB_DST_MINUS_SRC;
489 break;
490 case GL_MIN:
491 eqn = COMB_MIN_DST_SRC;
492 SETfield(blend_reg,
493 BLEND_ONE,
494 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
495 SETfield(blend_reg,
496 BLEND_ONE,
497 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
498 break;
499 case GL_MAX:
500 eqn = COMB_MAX_DST_SRC;
501 SETfield(blend_reg,
502 BLEND_ONE,
503 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
504 SETfield(blend_reg,
505 BLEND_ONE,
506 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
507 break;
508
509 default:
510 fprintf(stderr,
511 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
512 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
513 return;
514 }
515 SETfield(blend_reg,
516 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
517
518 SETfield(blend_reg,
519 blend_factor(ctx->Color.BlendSrcA, GL_TRUE),
520 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
521 SETfield(blend_reg,
522 blend_factor(ctx->Color.BlendDstA, GL_FALSE),
523 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
524
525 switch (ctx->Color.BlendEquationA) {
526 case GL_FUNC_ADD:
527 eqnA = COMB_DST_PLUS_SRC;
528 break;
529 case GL_FUNC_SUBTRACT:
530 eqnA = COMB_SRC_MINUS_DST;
531 break;
532 case GL_FUNC_REVERSE_SUBTRACT:
533 eqnA = COMB_DST_MINUS_SRC;
534 break;
535 case GL_MIN:
536 eqnA = COMB_MIN_DST_SRC;
537 SETfield(blend_reg,
538 BLEND_ONE,
539 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
540 SETfield(blend_reg,
541 BLEND_ONE,
542 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
543 break;
544 case GL_MAX:
545 eqnA = COMB_MAX_DST_SRC;
546 SETfield(blend_reg,
547 BLEND_ONE,
548 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
549 SETfield(blend_reg,
550 BLEND_ONE,
551 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
552 break;
553 default:
554 fprintf(stderr,
555 "[%s:%u] Invalid A blend equation (0x%04x).\n",
556 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
557 return;
558 }
559
560 SETfield(blend_reg,
561 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
562
563 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
564
565 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
566 r700->CB_BLEND_CONTROL.u32All = blend_reg;
567 else {
568 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
569 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
570 }
571 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
572 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
573
574 }
575
576 static void r700BlendEquationSeparate(GLcontext * ctx,
577 GLenum modeRGB, GLenum modeA) //-----------------
578 {
579 r700SetBlendState(ctx);
580 }
581
582 static void r700BlendFuncSeparate(GLcontext * ctx,
583 GLenum sfactorRGB, GLenum dfactorRGB,
584 GLenum sfactorA, GLenum dfactorA) //------------------------
585 {
586 r700SetBlendState(ctx);
587 }
588
589 /**
590 * Translate LogicOp enums into hardware representation.
591 */
592 static GLuint translate_logicop(GLenum logicop)
593 {
594 switch (logicop) {
595 case GL_CLEAR:
596 return 0x00;
597 case GL_SET:
598 return 0xff;
599 case GL_COPY:
600 return 0xcc;
601 case GL_COPY_INVERTED:
602 return 0x33;
603 case GL_NOOP:
604 return 0xaa;
605 case GL_INVERT:
606 return 0x55;
607 case GL_AND:
608 return 0x88;
609 case GL_NAND:
610 return 0x77;
611 case GL_OR:
612 return 0xee;
613 case GL_NOR:
614 return 0x11;
615 case GL_XOR:
616 return 0x66;
617 case GL_EQUIV:
618 return 0x99;
619 case GL_AND_REVERSE:
620 return 0x44;
621 case GL_AND_INVERTED:
622 return 0x22;
623 case GL_OR_REVERSE:
624 return 0xdd;
625 case GL_OR_INVERTED:
626 return 0xbb;
627 default:
628 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
629 return 0xcc;
630 }
631 }
632
633 /**
634 * Used internally to update the r300->hw hardware state to match the
635 * current OpenGL state.
636 */
637 static void r700SetLogicOpState(GLcontext *ctx)
638 {
639 context_t *context = R700_CONTEXT(ctx);
640 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
641
642 R600_STATECHANGE(context, blnd);
643
644 if (RGBA_LOGICOP_ENABLED(ctx))
645 SETfield(r700->CB_COLOR_CONTROL.u32All,
646 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
647 else
648 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
649 }
650
651 /**
652 * Called by Mesa when an application program changes the LogicOp state
653 * via glLogicOp.
654 */
655 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
656 {
657 if (RGBA_LOGICOP_ENABLED(ctx))
658 r700SetLogicOpState(ctx);
659 }
660
661 static void r700UpdateCulling(GLcontext * ctx)
662 {
663 context_t *context = R700_CONTEXT(ctx);
664 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
665
666 R600_STATECHANGE(context, su);
667
668 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
669 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
670 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
671
672 if (ctx->Polygon.CullFlag)
673 {
674 switch (ctx->Polygon.CullFaceMode)
675 {
676 case GL_FRONT:
677 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
678 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
679 break;
680 case GL_BACK:
681 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
682 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
683 break;
684 case GL_FRONT_AND_BACK:
685 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
686 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
687 break;
688 default:
689 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
690 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
691 break;
692 }
693 }
694
695 switch (ctx->Polygon.FrontFace)
696 {
697 case GL_CW:
698 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
699 break;
700 case GL_CCW:
701 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
702 break;
703 default:
704 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
705 break;
706 }
707
708 /* Winding is inverted when rendering to FBO */
709 if (ctx->DrawBuffer && ctx->DrawBuffer->Name)
710 r700->PA_SU_SC_MODE_CNTL.u32All ^= FACE_bit;
711 }
712
713 static void r700UpdateLineStipple(GLcontext * ctx)
714 {
715 context_t *context = R700_CONTEXT(ctx);
716 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
717
718 R600_STATECHANGE(context, sc);
719
720 if (ctx->Line.StippleFlag)
721 {
722 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
723 }
724 else
725 {
726 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
727 }
728 }
729
730 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
731 {
732 context_t *context = R700_CONTEXT(ctx);
733
734 switch (cap) {
735 case GL_TEXTURE_1D:
736 case GL_TEXTURE_2D:
737 case GL_TEXTURE_3D:
738 /* empty */
739 break;
740 case GL_FOG:
741 /* empty */
742 break;
743 case GL_ALPHA_TEST:
744 r700SetAlphaState(ctx);
745 break;
746 case GL_COLOR_LOGIC_OP:
747 r700SetLogicOpState(ctx);
748 /* fall-through, because logic op overrides blending */
749 case GL_BLEND:
750 r700SetBlendState(ctx);
751 break;
752 case GL_CLIP_PLANE0:
753 case GL_CLIP_PLANE1:
754 case GL_CLIP_PLANE2:
755 case GL_CLIP_PLANE3:
756 case GL_CLIP_PLANE4:
757 case GL_CLIP_PLANE5:
758 r700SetClipPlaneState(ctx, cap, state);
759 break;
760 case GL_DEPTH_TEST:
761 r700SetDepthState(ctx);
762 break;
763 case GL_STENCIL_TEST:
764 r700SetStencilState(ctx, state);
765 break;
766 case GL_CULL_FACE:
767 r700UpdateCulling(ctx);
768 break;
769 case GL_POLYGON_OFFSET_POINT:
770 case GL_POLYGON_OFFSET_LINE:
771 case GL_POLYGON_OFFSET_FILL:
772 r700SetPolygonOffsetState(ctx, state);
773 break;
774 case GL_SCISSOR_TEST:
775 radeon_firevertices(&context->radeon);
776 context->radeon.state.scissor.enabled = state;
777 radeonUpdateScissor(ctx);
778 break;
779 case GL_LINE_STIPPLE:
780 r700UpdateLineStipple(ctx);
781 break;
782 case GL_DEPTH_CLAMP:
783 r700UpdateWindow(ctx, 0);
784 break;
785 default:
786 break;
787 }
788
789 }
790
791 /**
792 * Handle glColorMask()
793 */
794 static void r700ColorMask(GLcontext * ctx,
795 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
796 {
797 context_t *context = R700_CONTEXT(ctx);
798 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
799 unsigned int mask = ((r ? 1 : 0) |
800 (g ? 2 : 0) |
801 (b ? 4 : 0) |
802 (a ? 8 : 0));
803
804 if (mask != r700->CB_TARGET_MASK.u32All) {
805 R600_STATECHANGE(context, cb);
806 SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
807 }
808 }
809
810 /**
811 * Change the depth testing function.
812 *
813 * \note Mesa already filters redundant calls to this function.
814 */
815 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
816 {
817 r700SetDepthState(ctx);
818 }
819
820 /**
821 * Enable/Disable depth writing.
822 *
823 * \note Mesa already filters redundant calls to this function.
824 */
825 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
826 {
827 r700SetDepthState(ctx);
828 }
829
830 /**
831 * Change the culling mode.
832 *
833 * \note Mesa already filters redundant calls to this function.
834 */
835 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
836 {
837 r700UpdateCulling(ctx);
838 }
839
840 /* =============================================================
841 * Fog
842 */
843 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
844 {
845 }
846
847 /**
848 * Change the polygon orientation.
849 *
850 * \note Mesa already filters redundant calls to this function.
851 */
852 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
853 {
854 r700UpdateCulling(ctx);
855 r700UpdatePolygonMode(ctx);
856 }
857
858 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
859 {
860 context_t *context = R700_CONTEXT(ctx);
861 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
862
863 R600_STATECHANGE(context, spi);
864
865 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
866 switch (mode) {
867 case GL_FLAT:
868 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
869 break;
870 case GL_SMOOTH:
871 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
872 break;
873 default:
874 return;
875 }
876 }
877
878 /* =============================================================
879 * Point state
880 */
881 static void r700PointSize(GLcontext * ctx, GLfloat size)
882 {
883 context_t *context = R700_CONTEXT(ctx);
884 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
885
886 R600_STATECHANGE(context, su);
887
888 /* We need to clamp to user defined range here, because
889 * the HW clamping happens only for per vertex point size. */
890 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
891
892 /* same size limits for AA, non-AA points */
893 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
894
895 /* format is 12.4 fixed point */
896 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
897 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
898 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
899 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
900
901 }
902
903 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
904 {
905 context_t *context = R700_CONTEXT(ctx);
906 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
907
908 R600_STATECHANGE(context, su);
909
910 /* format is 12.4 fixed point */
911 switch (pname) {
912 case GL_POINT_SIZE_MIN:
913 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
914 MIN_SIZE_shift, MIN_SIZE_mask);
915 r700PointSize(ctx, ctx->Point.Size);
916 break;
917 case GL_POINT_SIZE_MAX:
918 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
919 MAX_SIZE_shift, MAX_SIZE_mask);
920 r700PointSize(ctx, ctx->Point.Size);
921 break;
922 case GL_POINT_DISTANCE_ATTENUATION:
923 break;
924 case GL_POINT_FADE_THRESHOLD_SIZE:
925 break;
926 default:
927 break;
928 }
929 }
930
931 static int translate_stencil_func(int func)
932 {
933 switch (func) {
934 case GL_NEVER:
935 return REF_NEVER;
936 case GL_LESS:
937 return REF_LESS;
938 case GL_EQUAL:
939 return REF_EQUAL;
940 case GL_LEQUAL:
941 return REF_LEQUAL;
942 case GL_GREATER:
943 return REF_GREATER;
944 case GL_NOTEQUAL:
945 return REF_NOTEQUAL;
946 case GL_GEQUAL:
947 return REF_GEQUAL;
948 case GL_ALWAYS:
949 return REF_ALWAYS;
950 }
951 return 0;
952 }
953
954 static int translate_stencil_op(int op)
955 {
956 switch (op) {
957 case GL_KEEP:
958 return STENCIL_KEEP;
959 case GL_ZERO:
960 return STENCIL_ZERO;
961 case GL_REPLACE:
962 return STENCIL_REPLACE;
963 case GL_INCR:
964 return STENCIL_INCR_CLAMP;
965 case GL_DECR:
966 return STENCIL_DECR_CLAMP;
967 case GL_INCR_WRAP_EXT:
968 return STENCIL_INCR_WRAP;
969 case GL_DECR_WRAP_EXT:
970 return STENCIL_DECR_WRAP;
971 case GL_INVERT:
972 return STENCIL_INVERT;
973 default:
974 WARN_ONCE("Do not know how to translate stencil op");
975 return STENCIL_KEEP;
976 }
977 return 0;
978 }
979
980 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
981 {
982 context_t *context = R700_CONTEXT(ctx);
983 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
984 GLboolean hw_stencil = GL_FALSE;
985
986 if (ctx->DrawBuffer) {
987 struct radeon_renderbuffer *rrbStencil
988 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
989 hw_stencil = (rrbStencil && rrbStencil->bo);
990 }
991
992 if (hw_stencil) {
993 R600_STATECHANGE(context, db);
994 if (state) {
995 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
996 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
997 } else
998 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
999 }
1000 }
1001
1002 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
1003 GLenum func, GLint ref, GLuint mask) //---------------------
1004 {
1005 context_t *context = R700_CONTEXT(ctx);
1006 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1007 const unsigned back = ctx->Stencil._BackFace;
1008
1009 R600_STATECHANGE(context, stencil);
1010 R600_STATECHANGE(context, db);
1011
1012 //front
1013 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
1014 STENCILREF_shift, STENCILREF_mask);
1015 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
1016 STENCILMASK_shift, STENCILMASK_mask);
1017
1018 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
1019 STENCILFUNC_shift, STENCILFUNC_mask);
1020
1021 //back
1022 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
1023 STENCILREF_BF_shift, STENCILREF_BF_mask);
1024 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
1025 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1026
1027 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1028 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1029
1030 }
1031
1032 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1033 {
1034 context_t *context = R700_CONTEXT(ctx);
1035 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1036 const unsigned back = ctx->Stencil._BackFace;
1037
1038 R600_STATECHANGE(context, stencil);
1039
1040 // front
1041 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1042 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1043
1044 // back
1045 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1046 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1047
1048 }
1049
1050 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1051 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1052 {
1053 context_t *context = R700_CONTEXT(ctx);
1054 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1055 const unsigned back = ctx->Stencil._BackFace;
1056
1057 R600_STATECHANGE(context, db);
1058
1059 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1060 STENCILFAIL_shift, STENCILFAIL_mask);
1061 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1062 STENCILZFAIL_shift, STENCILZFAIL_mask);
1063 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1064 STENCILZPASS_shift, STENCILZPASS_mask);
1065
1066 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1067 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1068 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1069 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1070 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1071 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1072 }
1073
1074 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1075 {
1076 context_t *context = R700_CONTEXT(ctx);
1077 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1078 __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
1079 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1080 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1081 const GLfloat *v = ctx->Viewport._WindowMap.m;
1082 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1083 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1084 GLfloat y_scale, y_bias;
1085
1086 if (render_to_fbo) {
1087 y_scale = 1.0;
1088 y_bias = 0;
1089 } else {
1090 y_scale = -1.0;
1091 y_bias = yoffset;
1092 }
1093
1094 GLfloat sx = v[MAT_SX];
1095 GLfloat tx = v[MAT_TX] + xoffset;
1096 GLfloat sy = v[MAT_SY] * y_scale;
1097 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1098 GLfloat sz = v[MAT_SZ] * depthScale;
1099 GLfloat tz = v[MAT_TZ] * depthScale;
1100
1101 R600_STATECHANGE(context, vpt);
1102 R600_STATECHANGE(context, cl);
1103
1104 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1105 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1106
1107 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1108 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1109
1110 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1111 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1112
1113 if (ctx->Transform.DepthClamp) {
1114 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
1115 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
1116 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1117 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1118 } else {
1119 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0;
1120 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0;
1121 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1122 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1123 }
1124
1125 r700->viewport[id].enabled = GL_TRUE;
1126
1127 r700SetScissor(context);
1128 }
1129
1130
1131 static void r700Viewport(GLcontext * ctx,
1132 GLint x,
1133 GLint y,
1134 GLsizei width,
1135 GLsizei height) //--------------------
1136 {
1137 r700UpdateWindow(ctx, 0);
1138
1139 radeon_viewport(ctx, x, y, width, height);
1140 }
1141
1142 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1143 {
1144 r700UpdateWindow(ctx, 0);
1145 }
1146
1147 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1148 {
1149 context_t *context = R700_CONTEXT(ctx);
1150 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1151 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1152
1153 R600_STATECHANGE(context, su);
1154
1155 if (lineWidth > 0xFFFF)
1156 lineWidth = 0xFFFF;
1157 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1158 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1159 }
1160
1161 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1162 {
1163 context_t *context = R700_CONTEXT(ctx);
1164 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1165
1166 R600_STATECHANGE(context, sc);
1167
1168 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1169 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1170 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1171 }
1172
1173 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1174 {
1175 context_t *context = R700_CONTEXT(ctx);
1176 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1177
1178 R600_STATECHANGE(context, su);
1179
1180 if (state) {
1181 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1182 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1183 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1184 } else {
1185 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1186 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1187 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1188 }
1189 }
1190
1191 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1192 {
1193 context_t *context = R700_CONTEXT(ctx);
1194 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1195 GLfloat constant = units;
1196 GLchar depth = 0;
1197
1198 R600_STATECHANGE(context, poly);
1199
1200 switch (ctx->Visual.depthBits) {
1201 case 16:
1202 constant *= 4.0;
1203 depth = -16;
1204 break;
1205 case 24:
1206 constant *= 2.0;
1207 depth = -24;
1208 break;
1209 }
1210
1211 factor *= 12.0;
1212 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1213 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1214 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1215 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1216 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1217 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1218 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1219 }
1220
1221 static void r700UpdatePolygonMode(GLcontext * ctx)
1222 {
1223 context_t *context = R700_CONTEXT(ctx);
1224 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1225
1226 R600_STATECHANGE(context, su);
1227
1228 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1229
1230 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1231 if (ctx->Polygon.FrontMode != GL_FILL ||
1232 ctx->Polygon.BackMode != GL_FILL) {
1233 GLenum f, b;
1234
1235 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1236 * correctly by selecting the correct front and back face
1237 */
1238 f = ctx->Polygon.FrontMode;
1239 b = ctx->Polygon.BackMode;
1240
1241 /* Enable polygon mode */
1242 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1243
1244 switch (f) {
1245 case GL_LINE:
1246 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1247 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1248 break;
1249 case GL_POINT:
1250 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1251 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1252 break;
1253 case GL_FILL:
1254 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1255 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1256 break;
1257 }
1258
1259 switch (b) {
1260 case GL_LINE:
1261 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1262 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1263 break;
1264 case GL_POINT:
1265 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1266 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1267 break;
1268 case GL_FILL:
1269 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1270 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1271 break;
1272 }
1273 }
1274 }
1275
1276 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1277 {
1278 (void)face;
1279 (void)mode;
1280
1281 r700UpdatePolygonMode(ctx);
1282 }
1283
1284 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1285 {
1286 }
1287
1288 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1289 {
1290 context_t *context = R700_CONTEXT(ctx);
1291 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1292 GLint p;
1293 GLint *ip;
1294
1295 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1296 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1297
1298 R600_STATECHANGE(context, ucp);
1299
1300 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1301 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1302 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1303 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1304 }
1305
1306 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1307 {
1308 context_t *context = R700_CONTEXT(ctx);
1309 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1310 GLuint p;
1311
1312 p = cap - GL_CLIP_PLANE0;
1313
1314 R600_STATECHANGE(context, cl);
1315
1316 if (state) {
1317 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1318 r700->ucp[p].enabled = GL_TRUE;
1319 r700ClipPlane(ctx, cap, NULL);
1320 } else {
1321 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1322 r700->ucp[p].enabled = GL_FALSE;
1323 }
1324 }
1325
1326 void r700SetScissor(context_t *context) //---------------
1327 {
1328 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1329 unsigned x1, y1, x2, y2;
1330 int id = 0;
1331 struct radeon_renderbuffer *rrb;
1332
1333 rrb = radeon_get_colorbuffer(&context->radeon);
1334 if (!rrb || !rrb->bo) {
1335 return;
1336 }
1337 if (context->radeon.state.scissor.enabled) {
1338 x1 = context->radeon.state.scissor.rect.x1;
1339 y1 = context->radeon.state.scissor.rect.y1;
1340 x2 = context->radeon.state.scissor.rect.x2;
1341 y2 = context->radeon.state.scissor.rect.y2;
1342 /* r600 has exclusive BR scissors */
1343 if (context->radeon.radeonScreen->kernel_mm) {
1344 x2++;
1345 y2++;
1346 }
1347 } else {
1348 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1349 x1 = 0;
1350 y1 = 0;
1351 x2 = rrb->base.Width;
1352 y2 = rrb->base.Height;
1353 } else {
1354 x1 = rrb->dPriv->x;
1355 y1 = rrb->dPriv->y;
1356 x2 = rrb->dPriv->x + rrb->dPriv->w;
1357 y2 = rrb->dPriv->y + rrb->dPriv->h;
1358 }
1359 }
1360
1361 R600_STATECHANGE(context, scissor);
1362
1363 /* screen */
1364 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1365 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1366 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1367 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1368 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1369
1370 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1371 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1372 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1373 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1374
1375 /* window */
1376 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1377 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1378 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1379 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1380 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1381
1382 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1383 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1384 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1385 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1386
1387
1388 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1389 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1390 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1391 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1392 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1393 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1394 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1395 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1396
1397 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1398 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1399 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1400 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1401 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1402 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1403
1404 /* more....2d clip */
1405 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1406 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1407 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1408 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1409 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1410 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1411 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1412 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1413 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1414
1415 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1416 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1417 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1418 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1419 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1420 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1421 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1422 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1423 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1424
1425 r700->viewport[id].enabled = GL_TRUE;
1426 }
1427
1428 static void r700InitSQConfig(GLcontext * ctx)
1429 {
1430 context_t *context = R700_CONTEXT(ctx);
1431 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1432 int ps_prio;
1433 int vs_prio;
1434 int gs_prio;
1435 int es_prio;
1436 int num_ps_gprs;
1437 int num_vs_gprs;
1438 int num_gs_gprs;
1439 int num_es_gprs;
1440 int num_temp_gprs;
1441 int num_ps_threads;
1442 int num_vs_threads;
1443 int num_gs_threads;
1444 int num_es_threads;
1445 int num_ps_stack_entries;
1446 int num_vs_stack_entries;
1447 int num_gs_stack_entries;
1448 int num_es_stack_entries;
1449
1450 R600_STATECHANGE(context, sq);
1451
1452 // SQ
1453 ps_prio = 0;
1454 vs_prio = 1;
1455 gs_prio = 2;
1456 es_prio = 3;
1457 switch (context->radeon.radeonScreen->chip_family) {
1458 case CHIP_FAMILY_R600:
1459 num_ps_gprs = 192;
1460 num_vs_gprs = 56;
1461 num_temp_gprs = 4;
1462 num_gs_gprs = 0;
1463 num_es_gprs = 0;
1464 num_ps_threads = 136;
1465 num_vs_threads = 48;
1466 num_gs_threads = 4;
1467 num_es_threads = 4;
1468 num_ps_stack_entries = 128;
1469 num_vs_stack_entries = 128;
1470 num_gs_stack_entries = 0;
1471 num_es_stack_entries = 0;
1472 break;
1473 case CHIP_FAMILY_RV630:
1474 case CHIP_FAMILY_RV635:
1475 num_ps_gprs = 84;
1476 num_vs_gprs = 36;
1477 num_temp_gprs = 4;
1478 num_gs_gprs = 0;
1479 num_es_gprs = 0;
1480 num_ps_threads = 144;
1481 num_vs_threads = 40;
1482 num_gs_threads = 4;
1483 num_es_threads = 4;
1484 num_ps_stack_entries = 40;
1485 num_vs_stack_entries = 40;
1486 num_gs_stack_entries = 32;
1487 num_es_stack_entries = 16;
1488 break;
1489 case CHIP_FAMILY_RV610:
1490 case CHIP_FAMILY_RV620:
1491 case CHIP_FAMILY_RS780:
1492 case CHIP_FAMILY_RS880:
1493 default:
1494 num_ps_gprs = 84;
1495 num_vs_gprs = 36;
1496 num_temp_gprs = 4;
1497 num_gs_gprs = 0;
1498 num_es_gprs = 0;
1499 num_ps_threads = 136;
1500 num_vs_threads = 48;
1501 num_gs_threads = 4;
1502 num_es_threads = 4;
1503 num_ps_stack_entries = 40;
1504 num_vs_stack_entries = 40;
1505 num_gs_stack_entries = 32;
1506 num_es_stack_entries = 16;
1507 break;
1508 case CHIP_FAMILY_RV670:
1509 num_ps_gprs = 144;
1510 num_vs_gprs = 40;
1511 num_temp_gprs = 4;
1512 num_gs_gprs = 0;
1513 num_es_gprs = 0;
1514 num_ps_threads = 136;
1515 num_vs_threads = 48;
1516 num_gs_threads = 4;
1517 num_es_threads = 4;
1518 num_ps_stack_entries = 40;
1519 num_vs_stack_entries = 40;
1520 num_gs_stack_entries = 32;
1521 num_es_stack_entries = 16;
1522 break;
1523 case CHIP_FAMILY_RV770:
1524 num_ps_gprs = 192;
1525 num_vs_gprs = 56;
1526 num_temp_gprs = 4;
1527 num_gs_gprs = 0;
1528 num_es_gprs = 0;
1529 num_ps_threads = 188;
1530 num_vs_threads = 60;
1531 num_gs_threads = 0;
1532 num_es_threads = 0;
1533 num_ps_stack_entries = 256;
1534 num_vs_stack_entries = 256;
1535 num_gs_stack_entries = 0;
1536 num_es_stack_entries = 0;
1537 break;
1538 case CHIP_FAMILY_RV730:
1539 case CHIP_FAMILY_RV740:
1540 num_ps_gprs = 84;
1541 num_vs_gprs = 36;
1542 num_temp_gprs = 4;
1543 num_gs_gprs = 0;
1544 num_es_gprs = 0;
1545 num_ps_threads = 188;
1546 num_vs_threads = 60;
1547 num_gs_threads = 0;
1548 num_es_threads = 0;
1549 num_ps_stack_entries = 128;
1550 num_vs_stack_entries = 128;
1551 num_gs_stack_entries = 0;
1552 num_es_stack_entries = 0;
1553 break;
1554 case CHIP_FAMILY_RV710:
1555 num_ps_gprs = 192;
1556 num_vs_gprs = 56;
1557 num_temp_gprs = 4;
1558 num_gs_gprs = 0;
1559 num_es_gprs = 0;
1560 num_ps_threads = 144;
1561 num_vs_threads = 48;
1562 num_gs_threads = 0;
1563 num_es_threads = 0;
1564 num_ps_stack_entries = 128;
1565 num_vs_stack_entries = 128;
1566 num_gs_stack_entries = 0;
1567 num_es_stack_entries = 0;
1568 break;
1569 }
1570
1571 r700->sq_config.SQ_CONFIG.u32All = 0;
1572 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1573 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1574 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1575 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1576 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1577 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1578 else
1579 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1580 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1581 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1582 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1583 SETfield(r700->sq_config.SQ_CONFIG.u32All, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
1584 SETfield(r700->sq_config.SQ_CONFIG.u32All, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
1585 SETfield(r700->sq_config.SQ_CONFIG.u32All, es_prio, ES_PRIO_shift, ES_PRIO_mask);
1586
1587 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1588 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1589 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1590 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1591 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1592
1593 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1594 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1595 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1596
1597 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1598 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1599 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1600 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1601 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1602 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1603 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1604 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1605 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1606
1607 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1608 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1609 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1610 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1611 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1612
1613 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1614 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1615 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1616 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1617 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1618
1619 }
1620
1621 /**
1622 * Calculate initial hardware state and register state functions.
1623 * Assumes that the command buffer and state atoms have been
1624 * initialized already.
1625 */
1626 void r700InitState(GLcontext * ctx) //-------------------
1627 {
1628 context_t *context = R700_CONTEXT(ctx);
1629 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1630 int id = 0;
1631
1632 r700->TA_CNTL_AUX.u32All = 0;
1633 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1634 r700->VC_ENHANCE.u32All = 0;
1635 r700->DB_WATERMARKS.u32All = 0;
1636 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1637 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1638 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1639 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1640 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1641 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1642 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1643 r700->DB_DEBUG.u32All = 0x82000000;
1644 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1645 } else {
1646 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1647 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1648 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1649 }
1650
1651 /* Turn off vgt reuse */
1652 r700->VGT_REUSE_OFF.u32All = 0;
1653 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1654
1655 /* Specify offsetting and clamp values for vertices */
1656 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1657 r700->VGT_MIN_VTX_INDX.u32All = 0;
1658 r700->VGT_INDX_OFFSET.u32All = 0;
1659
1660 /* default shader connections. */
1661 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1662 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1663 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1664 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1665
1666 r700->SPI_THREAD_GROUPING.u32All = 0;
1667 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1668 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1669
1670 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1671 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1672 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1673
1674 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1675 r700->PA_SC_EDGERULE.u32All = 0;
1676 else
1677 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1678
1679 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1680 r700->PA_SC_MODE_CNTL.u32All = 0;
1681 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1682 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1683 } else {
1684 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1685 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1686 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1687 }
1688
1689 /* Do scale XY and Z by 1/W0. */
1690 r700->bEnablePerspective = GL_TRUE;
1691 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1692 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1693 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1694
1695 /* Enable viewport scaling for all three axis */
1696 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1697 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1698 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1699 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1700 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1701 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1702
1703 /* GL uses last vtx for flat shading components */
1704 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1705
1706 /* Set up vertex control */
1707 r700->PA_SU_VTX_CNTL.u32All = 0;
1708 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1709 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1710 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1711 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1712
1713 /* to 1.0 = no guard band */
1714 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1715 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1716 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1717 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1718
1719 /* Enable all samples for multi-sample anti-aliasing */
1720 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1721 /* Turn off AA */
1722 r700->PA_SC_AA_CONFIG.u32All = 0;
1723
1724 r700->SX_MISC.u32All = 0;
1725
1726 r700InitSQConfig(ctx);
1727
1728 r700ColorMask(ctx,
1729 ctx->Color.ColorMask[0][RCOMP],
1730 ctx->Color.ColorMask[0][GCOMP],
1731 ctx->Color.ColorMask[0][BCOMP],
1732 ctx->Color.ColorMask[0][ACOMP]);
1733
1734 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1735 r700DepthMask(ctx, ctx->Depth.Mask);
1736 r700DepthFunc(ctx, ctx->Depth.Func);
1737 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1738 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1739 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1740 r700SetDBRenderState(ctx);
1741
1742 r700->DB_ALPHA_TO_MASK.u32All = 0;
1743 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1744 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1745 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1746 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1747
1748 /* stencil */
1749 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1750 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1751 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1752 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1753 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1754 ctx->Stencil.ZFailFunc[0],
1755 ctx->Stencil.ZPassFunc[0]);
1756
1757 r700UpdateCulling(ctx);
1758
1759 r700SetBlendState(ctx);
1760 r700SetLogicOpState(ctx);
1761
1762 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1763 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1764
1765 r700PointSize(ctx, 1.0);
1766
1767 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1768 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1769
1770 r700LineWidth(ctx, 1.0);
1771
1772 r700->PA_SC_LINE_CNTL.u32All = 0;
1773 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1774 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1775
1776 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1777 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1778 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1779 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1780 ctx->Polygon.OffsetUnits);
1781 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1782 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1783 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1784
1785 /* CB */
1786 r700BlendColor(ctx, ctx->Color.BlendColor);
1787
1788 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1789 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1790 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1791 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1792 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1793 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1794 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1795
1796 /* Disable color compares */
1797 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1798 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1799 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1800 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1801 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1802 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1803
1804 /* Zero out source */
1805 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1806
1807 /* Put a compare color in for error checking */
1808 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1809
1810 /* Set up color compare mask */
1811 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1812
1813 /* screen/window/view */
1814 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask);
1815
1816 context->radeon.hw.all_dirty = GL_TRUE;
1817
1818 }
1819
1820 void r700InitStateFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
1821 {
1822 functions->UpdateState = r700InvalidateState;
1823 functions->AlphaFunc = r700AlphaFunc;
1824 functions->BlendColor = r700BlendColor;
1825 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1826 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1827 functions->Enable = r700Enable;
1828 functions->ColorMask = r700ColorMask;
1829 functions->DepthFunc = r700DepthFunc;
1830 functions->DepthMask = r700DepthMask;
1831 functions->CullFace = r700CullFace;
1832 functions->Fogfv = r700Fogfv;
1833 functions->FrontFace = r700FrontFace;
1834 functions->ShadeModel = r700ShadeModel;
1835 functions->LogicOpcode = r700LogicOpcode;
1836
1837 /* ARB_point_parameters */
1838 functions->PointParameterfv = r700PointParameter;
1839
1840 /* Stencil related */
1841 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1842 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1843 functions->StencilOpSeparate = r700StencilOpSeparate;
1844
1845 /* Viewport related */
1846 functions->Viewport = r700Viewport;
1847 functions->DepthRange = r700DepthRange;
1848 functions->PointSize = r700PointSize;
1849 functions->LineWidth = r700LineWidth;
1850 functions->LineStipple = r700LineStipple;
1851
1852 functions->PolygonOffset = r700PolygonOffset;
1853 functions->PolygonMode = r700PolygonMode;
1854
1855 functions->RenderMode = r700RenderMode;
1856
1857 functions->ClipPlane = r700ClipPlane;
1858
1859 functions->Scissor = radeonScissor;
1860
1861 functions->DrawBuffer = radeonDrawBuffer;
1862 functions->ReadBuffer = radeonReadBuffer;
1863
1864 if (radeon->radeonScreen->kernel_mm) {
1865 functions->CopyPixels = _mesa_meta_CopyPixels;
1866 functions->DrawPixels = _mesa_meta_DrawPixels;
1867 functions->ReadPixels = radeonReadPixels;
1868 }
1869 }
1870