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Merge remote branch 'origin/master' into nv50-compiler
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/imports.h"
30 #include "main/enums.h"
31 #include "main/macros.h"
32 #include "main/context.h"
33 #include "main/dd.h"
34 #include "main/simple_list.h"
35
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast/swrast.h"
39 #include "swrast_setup/swrast_setup.h"
40 #include "main/api_arrayelt.h"
41 #include "main/framebuffer.h"
42 #include "drivers/common/meta.h"
43
44 #include "program/prog_parameter.h"
45 #include "program/prog_statevars.h"
46 #include "vbo/vbo.h"
47
48 #include "r600_context.h"
49
50 #include "r700_state.h"
51
52 #include "r700_fragprog.h"
53 #include "r700_vertprog.h"
54
55 void r600UpdateTextureState(GLcontext * ctx);
56 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
57 static void r700UpdatePolygonMode(GLcontext * ctx);
58 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
59 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
60 static void r700UpdateWindow(GLcontext * ctx, int id);
61
62 void r700UpdateShaders(GLcontext * ctx)
63 {
64 context_t *context = R700_CONTEXT(ctx);
65
66 /* should only happenen once, just after context is created */
67 /* TODO: shouldn't we fallback to sw here? */
68 if (!ctx->FragmentProgram._Current) {
69 fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
70 return;
71 }
72
73 r700SelectFragmentShader(ctx);
74
75 r700SelectVertexShader(ctx);
76 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
77 context->radeon.NewGLState = 0;
78 }
79
80 /*
81 * To correctly position primitives:
82 */
83 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
84 {
85 context_t *context = R700_CONTEXT(ctx);
86 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
87 __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
88 GLfloat xoffset = (GLfloat) dPriv->x;
89 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
90 const GLfloat *v = ctx->Viewport._WindowMap.m;
91 int id = 0;
92
93 GLfloat tx = v[MAT_TX] + xoffset;
94 GLfloat ty = (-v[MAT_TY]) + yoffset;
95
96 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
97 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
98 /* Note: this should also modify whatever data the context reset
99 * code uses...
100 */
101 R600_STATECHANGE(context, vpt);
102 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
103 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
104 }
105
106 radeonUpdateScissor(ctx);
107 }
108
109 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
110 {
111 struct r700_fragment_program *fp =
112 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
113 struct gl_program_parameter_list *paramList;
114
115 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
116 return;
117
118 if (!ctx->FragmentProgram._Current || !fp)
119 return;
120
121 paramList = ctx->FragmentProgram._Current->Base.Parameters;
122
123 if (!paramList)
124 return;
125
126 _mesa_load_state_parameters(ctx, paramList);
127
128 }
129
130 /**
131 * Called by Mesa after an internal state update.
132 */
133 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
134 {
135 context_t *context = R700_CONTEXT(ctx);
136
137 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
138
139 _swrast_InvalidateState(ctx, new_state);
140 _swsetup_InvalidateState(ctx, new_state);
141 _vbo_InvalidateState(ctx, new_state);
142 _tnl_InvalidateState(ctx, new_state);
143 _ae_invalidate_state(ctx, new_state);
144
145 if (new_state & _NEW_BUFFERS) {
146 _mesa_update_framebuffer(ctx);
147 /* this updates the DrawBuffer's Width/Height if it's a FBO */
148 _mesa_update_draw_buffer_bounds(ctx);
149
150 R600_STATECHANGE(context, cb_target);
151 R600_STATECHANGE(context, db_target);
152 }
153
154 if (new_state & (_NEW_LIGHT)) {
155 R600_STATECHANGE(context, su);
156 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
157 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
158 else
159 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
160 }
161
162 r700UpdateStateParameters(ctx, new_state);
163
164 R600_STATECHANGE(context, cl);
165 R600_STATECHANGE(context, spi);
166
167 if(GL_TRUE == r700->bEnablePerspective)
168 {
169 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
170 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
171 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
172
173 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
174
175 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
176 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
177 }
178 else
179 {
180 /* For orthogonal case. */
181 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
182 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
183
184 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
185
186 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
187 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
188 }
189
190 context->radeon.NewGLState |= new_state;
191 }
192
193 static void r700SetDBRenderState(GLcontext * ctx)
194 {
195 context_t *context = R700_CONTEXT(ctx);
196 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
197 struct r700_fragment_program *fp = (struct r700_fragment_program *)
198 (ctx->FragmentProgram._Current);
199
200 R600_STATECHANGE(context, db);
201
202 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
203 SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask);
204 /* XXX need to enable htile for hiz/s */
205 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
206 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
207 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
208
209 if (context->radeon.query.current)
210 {
211 SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
212 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
213 {
214 SETbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
215 }
216 }
217 else
218 {
219 CLEARbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
220 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
221 {
222 CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
223 }
224 }
225
226 if (fp)
227 {
228 if (fp->r700Shader.killIsUsed)
229 {
230 SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
231 }
232 else
233 {
234 CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
235 }
236
237 if (fp->r700Shader.depthIsExported)
238 {
239 SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
240 }
241 else
242 {
243 CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
244 }
245 }
246 }
247
248 void r700UpdateShaderStates(GLcontext * ctx)
249 {
250 r700SetDBRenderState(ctx);
251 r600UpdateTextureState(ctx);
252 }
253
254 static void r700SetDepthState(GLcontext * ctx)
255 {
256 struct radeon_renderbuffer *rrb;
257 context_t *context = R700_CONTEXT(ctx);
258 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
259
260 R600_STATECHANGE(context, db);
261
262 rrb = radeon_get_depthbuffer(&context->radeon);
263
264 if (ctx->Depth.Test && rrb && rrb->bo)
265 {
266 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
267 if (ctx->Depth.Mask)
268 {
269 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
270 }
271 else
272 {
273 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
274 }
275
276 switch (ctx->Depth.Func)
277 {
278 case GL_NEVER:
279 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
280 ZFUNC_shift, ZFUNC_mask);
281 break;
282 case GL_LESS:
283 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
284 ZFUNC_shift, ZFUNC_mask);
285 break;
286 case GL_EQUAL:
287 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
288 ZFUNC_shift, ZFUNC_mask);
289 break;
290 case GL_LEQUAL:
291 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
292 ZFUNC_shift, ZFUNC_mask);
293 break;
294 case GL_GREATER:
295 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
296 ZFUNC_shift, ZFUNC_mask);
297 break;
298 case GL_NOTEQUAL:
299 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
300 ZFUNC_shift, ZFUNC_mask);
301 break;
302 case GL_GEQUAL:
303 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
304 ZFUNC_shift, ZFUNC_mask);
305 break;
306 case GL_ALWAYS:
307 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
308 ZFUNC_shift, ZFUNC_mask);
309 break;
310 default:
311 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
312 ZFUNC_shift, ZFUNC_mask);
313 break;
314 }
315 }
316 else
317 {
318 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
319 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
320 }
321 }
322
323 static void r700SetAlphaState(GLcontext * ctx)
324 {
325 context_t *context = R700_CONTEXT(ctx);
326 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
327 uint32_t alpha_func = REF_ALWAYS;
328 GLboolean really_enabled = ctx->Color.AlphaEnabled;
329
330 R600_STATECHANGE(context, sx);
331
332 switch (ctx->Color.AlphaFunc) {
333 case GL_NEVER:
334 alpha_func = REF_NEVER;
335 break;
336 case GL_LESS:
337 alpha_func = REF_LESS;
338 break;
339 case GL_EQUAL:
340 alpha_func = REF_EQUAL;
341 break;
342 case GL_LEQUAL:
343 alpha_func = REF_LEQUAL;
344 break;
345 case GL_GREATER:
346 alpha_func = REF_GREATER;
347 break;
348 case GL_NOTEQUAL:
349 alpha_func = REF_NOTEQUAL;
350 break;
351 case GL_GEQUAL:
352 alpha_func = REF_GEQUAL;
353 break;
354 case GL_ALWAYS:
355 /*alpha_func = REF_ALWAYS; */
356 really_enabled = GL_FALSE;
357 break;
358 }
359
360 if (really_enabled) {
361 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
362 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
363 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
364 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
365 } else {
366 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
367 }
368
369 }
370
371 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
372 {
373 (void)func;
374 (void)ref;
375 r700SetAlphaState(ctx);
376 }
377
378
379 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
380 {
381 context_t *context = R700_CONTEXT(ctx);
382 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
383
384 R600_STATECHANGE(context, blnd_clr);
385
386 r700->CB_BLEND_RED.f32All = cf[0];
387 r700->CB_BLEND_GREEN.f32All = cf[1];
388 r700->CB_BLEND_BLUE.f32All = cf[2];
389 r700->CB_BLEND_ALPHA.f32All = cf[3];
390 }
391
392 static int blend_factor(GLenum factor, GLboolean is_src)
393 {
394 switch (factor) {
395 case GL_ZERO:
396 return BLEND_ZERO;
397 break;
398 case GL_ONE:
399 return BLEND_ONE;
400 break;
401 case GL_DST_COLOR:
402 return BLEND_DST_COLOR;
403 break;
404 case GL_ONE_MINUS_DST_COLOR:
405 return BLEND_ONE_MINUS_DST_COLOR;
406 break;
407 case GL_SRC_COLOR:
408 return BLEND_SRC_COLOR;
409 break;
410 case GL_ONE_MINUS_SRC_COLOR:
411 return BLEND_ONE_MINUS_SRC_COLOR;
412 break;
413 case GL_SRC_ALPHA:
414 return BLEND_SRC_ALPHA;
415 break;
416 case GL_ONE_MINUS_SRC_ALPHA:
417 return BLEND_ONE_MINUS_SRC_ALPHA;
418 break;
419 case GL_DST_ALPHA:
420 return BLEND_DST_ALPHA;
421 break;
422 case GL_ONE_MINUS_DST_ALPHA:
423 return BLEND_ONE_MINUS_DST_ALPHA;
424 break;
425 case GL_SRC_ALPHA_SATURATE:
426 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
427 break;
428 case GL_CONSTANT_COLOR:
429 return BLEND_CONSTANT_COLOR;
430 break;
431 case GL_ONE_MINUS_CONSTANT_COLOR:
432 return BLEND_ONE_MINUS_CONSTANT_COLOR;
433 break;
434 case GL_CONSTANT_ALPHA:
435 return BLEND_CONSTANT_ALPHA;
436 break;
437 case GL_ONE_MINUS_CONSTANT_ALPHA:
438 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
439 break;
440 default:
441 fprintf(stderr, "unknown blend factor %x\n", factor);
442 return (is_src) ? BLEND_ONE : BLEND_ZERO;
443 break;
444 }
445 }
446
447 static void r700SetBlendState(GLcontext * ctx)
448 {
449 context_t *context = R700_CONTEXT(ctx);
450 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
451 int id = 0;
452 uint32_t blend_reg = 0, eqn, eqnA;
453
454 R600_STATECHANGE(context, blnd);
455
456 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
457 SETfield(blend_reg,
458 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
459 SETfield(blend_reg,
460 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
461 SETfield(blend_reg,
462 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
463 SETfield(blend_reg,
464 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
465 SETfield(blend_reg,
466 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
467 SETfield(blend_reg,
468 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
469 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
470 r700->CB_BLEND_CONTROL.u32All = blend_reg;
471 else
472 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
473 return;
474 }
475
476 SETfield(blend_reg,
477 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
478 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
479 SETfield(blend_reg,
480 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
481 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
482
483 switch (ctx->Color.BlendEquationRGB) {
484 case GL_FUNC_ADD:
485 eqn = COMB_DST_PLUS_SRC;
486 break;
487 case GL_FUNC_SUBTRACT:
488 eqn = COMB_SRC_MINUS_DST;
489 break;
490 case GL_FUNC_REVERSE_SUBTRACT:
491 eqn = COMB_DST_MINUS_SRC;
492 break;
493 case GL_MIN:
494 eqn = COMB_MIN_DST_SRC;
495 SETfield(blend_reg,
496 BLEND_ONE,
497 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
498 SETfield(blend_reg,
499 BLEND_ONE,
500 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
501 break;
502 case GL_MAX:
503 eqn = COMB_MAX_DST_SRC;
504 SETfield(blend_reg,
505 BLEND_ONE,
506 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
507 SETfield(blend_reg,
508 BLEND_ONE,
509 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
510 break;
511
512 default:
513 fprintf(stderr,
514 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
515 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
516 return;
517 }
518 SETfield(blend_reg,
519 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
520
521 SETfield(blend_reg,
522 blend_factor(ctx->Color.BlendSrcA, GL_TRUE),
523 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
524 SETfield(blend_reg,
525 blend_factor(ctx->Color.BlendDstA, GL_FALSE),
526 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
527
528 switch (ctx->Color.BlendEquationA) {
529 case GL_FUNC_ADD:
530 eqnA = COMB_DST_PLUS_SRC;
531 break;
532 case GL_FUNC_SUBTRACT:
533 eqnA = COMB_SRC_MINUS_DST;
534 break;
535 case GL_FUNC_REVERSE_SUBTRACT:
536 eqnA = COMB_DST_MINUS_SRC;
537 break;
538 case GL_MIN:
539 eqnA = COMB_MIN_DST_SRC;
540 SETfield(blend_reg,
541 BLEND_ONE,
542 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
543 SETfield(blend_reg,
544 BLEND_ONE,
545 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
546 break;
547 case GL_MAX:
548 eqnA = COMB_MAX_DST_SRC;
549 SETfield(blend_reg,
550 BLEND_ONE,
551 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
552 SETfield(blend_reg,
553 BLEND_ONE,
554 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
555 break;
556 default:
557 fprintf(stderr,
558 "[%s:%u] Invalid A blend equation (0x%04x).\n",
559 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
560 return;
561 }
562
563 SETfield(blend_reg,
564 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
565
566 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
567
568 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
569 r700->CB_BLEND_CONTROL.u32All = blend_reg;
570 else {
571 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
572 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
573 }
574 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
575 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
576
577 }
578
579 static void r700BlendEquationSeparate(GLcontext * ctx,
580 GLenum modeRGB, GLenum modeA) //-----------------
581 {
582 r700SetBlendState(ctx);
583 }
584
585 static void r700BlendFuncSeparate(GLcontext * ctx,
586 GLenum sfactorRGB, GLenum dfactorRGB,
587 GLenum sfactorA, GLenum dfactorA) //------------------------
588 {
589 r700SetBlendState(ctx);
590 }
591
592 /**
593 * Translate LogicOp enums into hardware representation.
594 */
595 static GLuint translate_logicop(GLenum logicop)
596 {
597 switch (logicop) {
598 case GL_CLEAR:
599 return 0x00;
600 case GL_SET:
601 return 0xff;
602 case GL_COPY:
603 return 0xcc;
604 case GL_COPY_INVERTED:
605 return 0x33;
606 case GL_NOOP:
607 return 0xaa;
608 case GL_INVERT:
609 return 0x55;
610 case GL_AND:
611 return 0x88;
612 case GL_NAND:
613 return 0x77;
614 case GL_OR:
615 return 0xee;
616 case GL_NOR:
617 return 0x11;
618 case GL_XOR:
619 return 0x66;
620 case GL_EQUIV:
621 return 0x99;
622 case GL_AND_REVERSE:
623 return 0x44;
624 case GL_AND_INVERTED:
625 return 0x22;
626 case GL_OR_REVERSE:
627 return 0xdd;
628 case GL_OR_INVERTED:
629 return 0xbb;
630 default:
631 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
632 return 0xcc;
633 }
634 }
635
636 /**
637 * Used internally to update the r300->hw hardware state to match the
638 * current OpenGL state.
639 */
640 static void r700SetLogicOpState(GLcontext *ctx)
641 {
642 context_t *context = R700_CONTEXT(ctx);
643 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
644
645 R600_STATECHANGE(context, blnd);
646
647 if (RGBA_LOGICOP_ENABLED(ctx))
648 SETfield(r700->CB_COLOR_CONTROL.u32All,
649 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
650 else
651 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
652 }
653
654 /**
655 * Called by Mesa when an application program changes the LogicOp state
656 * via glLogicOp.
657 */
658 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
659 {
660 if (RGBA_LOGICOP_ENABLED(ctx))
661 r700SetLogicOpState(ctx);
662 }
663
664 static void r700UpdateCulling(GLcontext * ctx)
665 {
666 context_t *context = R700_CONTEXT(ctx);
667 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
668
669 R600_STATECHANGE(context, su);
670
671 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
672 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
673 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
674
675 if (ctx->Polygon.CullFlag)
676 {
677 switch (ctx->Polygon.CullFaceMode)
678 {
679 case GL_FRONT:
680 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
681 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
682 break;
683 case GL_BACK:
684 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
685 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
686 break;
687 case GL_FRONT_AND_BACK:
688 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
689 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
690 break;
691 default:
692 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
693 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
694 break;
695 }
696 }
697
698 switch (ctx->Polygon.FrontFace)
699 {
700 case GL_CW:
701 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
702 break;
703 case GL_CCW:
704 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
705 break;
706 default:
707 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
708 break;
709 }
710
711 /* Winding is inverted when rendering to FBO */
712 if (ctx->DrawBuffer && ctx->DrawBuffer->Name)
713 r700->PA_SU_SC_MODE_CNTL.u32All ^= FACE_bit;
714 }
715
716 static void r700UpdateLineStipple(GLcontext * ctx)
717 {
718 context_t *context = R700_CONTEXT(ctx);
719 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
720
721 R600_STATECHANGE(context, sc);
722
723 if (ctx->Line.StippleFlag)
724 {
725 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
726 }
727 else
728 {
729 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
730 }
731 }
732
733 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
734 {
735 context_t *context = R700_CONTEXT(ctx);
736
737 switch (cap) {
738 case GL_TEXTURE_1D:
739 case GL_TEXTURE_2D:
740 case GL_TEXTURE_3D:
741 /* empty */
742 break;
743 case GL_FOG:
744 /* empty */
745 break;
746 case GL_ALPHA_TEST:
747 r700SetAlphaState(ctx);
748 break;
749 case GL_COLOR_LOGIC_OP:
750 r700SetLogicOpState(ctx);
751 /* fall-through, because logic op overrides blending */
752 case GL_BLEND:
753 r700SetBlendState(ctx);
754 break;
755 case GL_CLIP_PLANE0:
756 case GL_CLIP_PLANE1:
757 case GL_CLIP_PLANE2:
758 case GL_CLIP_PLANE3:
759 case GL_CLIP_PLANE4:
760 case GL_CLIP_PLANE5:
761 r700SetClipPlaneState(ctx, cap, state);
762 break;
763 case GL_DEPTH_TEST:
764 r700SetDepthState(ctx);
765 break;
766 case GL_STENCIL_TEST:
767 r700SetStencilState(ctx, state);
768 break;
769 case GL_CULL_FACE:
770 r700UpdateCulling(ctx);
771 break;
772 case GL_POLYGON_OFFSET_POINT:
773 case GL_POLYGON_OFFSET_LINE:
774 case GL_POLYGON_OFFSET_FILL:
775 r700SetPolygonOffsetState(ctx, state);
776 break;
777 case GL_SCISSOR_TEST:
778 radeon_firevertices(&context->radeon);
779 context->radeon.state.scissor.enabled = state;
780 radeonUpdateScissor(ctx);
781 break;
782 case GL_LINE_STIPPLE:
783 r700UpdateLineStipple(ctx);
784 break;
785 case GL_DEPTH_CLAMP:
786 r700UpdateWindow(ctx, 0);
787 break;
788 default:
789 break;
790 }
791
792 }
793
794 /**
795 * Handle glColorMask()
796 */
797 static void r700ColorMask(GLcontext * ctx,
798 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
799 {
800 context_t *context = R700_CONTEXT(ctx);
801 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
802 unsigned int mask = ((r ? 1 : 0) |
803 (g ? 2 : 0) |
804 (b ? 4 : 0) |
805 (a ? 8 : 0));
806
807 if (mask != r700->CB_TARGET_MASK.u32All) {
808 R600_STATECHANGE(context, cb);
809 SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
810 }
811 }
812
813 /**
814 * Change the depth testing function.
815 *
816 * \note Mesa already filters redundant calls to this function.
817 */
818 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
819 {
820 r700SetDepthState(ctx);
821 }
822
823 /**
824 * Enable/Disable depth writing.
825 *
826 * \note Mesa already filters redundant calls to this function.
827 */
828 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
829 {
830 r700SetDepthState(ctx);
831 }
832
833 /**
834 * Change the culling mode.
835 *
836 * \note Mesa already filters redundant calls to this function.
837 */
838 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
839 {
840 r700UpdateCulling(ctx);
841 }
842
843 /* =============================================================
844 * Fog
845 */
846 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
847 {
848 }
849
850 /**
851 * Change the polygon orientation.
852 *
853 * \note Mesa already filters redundant calls to this function.
854 */
855 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
856 {
857 r700UpdateCulling(ctx);
858 r700UpdatePolygonMode(ctx);
859 }
860
861 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
862 {
863 context_t *context = R700_CONTEXT(ctx);
864 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
865
866 R600_STATECHANGE(context, spi);
867
868 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
869 switch (mode) {
870 case GL_FLAT:
871 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
872 break;
873 case GL_SMOOTH:
874 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
875 break;
876 default:
877 return;
878 }
879 }
880
881 /* =============================================================
882 * Point state
883 */
884 static void r700PointSize(GLcontext * ctx, GLfloat size)
885 {
886 context_t *context = R700_CONTEXT(ctx);
887 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
888
889 R600_STATECHANGE(context, su);
890
891 /* We need to clamp to user defined range here, because
892 * the HW clamping happens only for per vertex point size. */
893 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
894
895 /* same size limits for AA, non-AA points */
896 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
897
898 /* format is 12.4 fixed point */
899 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
900 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
901 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
902 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
903
904 }
905
906 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
907 {
908 context_t *context = R700_CONTEXT(ctx);
909 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
910
911 R600_STATECHANGE(context, su);
912
913 /* format is 12.4 fixed point */
914 switch (pname) {
915 case GL_POINT_SIZE_MIN:
916 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
917 MIN_SIZE_shift, MIN_SIZE_mask);
918 r700PointSize(ctx, ctx->Point.Size);
919 break;
920 case GL_POINT_SIZE_MAX:
921 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
922 MAX_SIZE_shift, MAX_SIZE_mask);
923 r700PointSize(ctx, ctx->Point.Size);
924 break;
925 case GL_POINT_DISTANCE_ATTENUATION:
926 break;
927 case GL_POINT_FADE_THRESHOLD_SIZE:
928 break;
929 default:
930 break;
931 }
932 }
933
934 static int translate_stencil_func(int func)
935 {
936 switch (func) {
937 case GL_NEVER:
938 return REF_NEVER;
939 case GL_LESS:
940 return REF_LESS;
941 case GL_EQUAL:
942 return REF_EQUAL;
943 case GL_LEQUAL:
944 return REF_LEQUAL;
945 case GL_GREATER:
946 return REF_GREATER;
947 case GL_NOTEQUAL:
948 return REF_NOTEQUAL;
949 case GL_GEQUAL:
950 return REF_GEQUAL;
951 case GL_ALWAYS:
952 return REF_ALWAYS;
953 }
954 return 0;
955 }
956
957 static int translate_stencil_op(int op)
958 {
959 switch (op) {
960 case GL_KEEP:
961 return STENCIL_KEEP;
962 case GL_ZERO:
963 return STENCIL_ZERO;
964 case GL_REPLACE:
965 return STENCIL_REPLACE;
966 case GL_INCR:
967 return STENCIL_INCR_CLAMP;
968 case GL_DECR:
969 return STENCIL_DECR_CLAMP;
970 case GL_INCR_WRAP_EXT:
971 return STENCIL_INCR_WRAP;
972 case GL_DECR_WRAP_EXT:
973 return STENCIL_DECR_WRAP;
974 case GL_INVERT:
975 return STENCIL_INVERT;
976 default:
977 WARN_ONCE("Do not know how to translate stencil op");
978 return STENCIL_KEEP;
979 }
980 return 0;
981 }
982
983 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
984 {
985 context_t *context = R700_CONTEXT(ctx);
986 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
987 GLboolean hw_stencil = GL_FALSE;
988
989 if (ctx->DrawBuffer) {
990 struct radeon_renderbuffer *rrbStencil
991 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
992 hw_stencil = (rrbStencil && rrbStencil->bo);
993 }
994
995 if (hw_stencil) {
996 R600_STATECHANGE(context, db);
997 if (state) {
998 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
999 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
1000 } else
1001 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
1002 }
1003 }
1004
1005 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
1006 GLenum func, GLint ref, GLuint mask) //---------------------
1007 {
1008 context_t *context = R700_CONTEXT(ctx);
1009 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1010 const unsigned back = ctx->Stencil._BackFace;
1011
1012 R600_STATECHANGE(context, stencil);
1013 R600_STATECHANGE(context, db);
1014
1015 //front
1016 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
1017 STENCILREF_shift, STENCILREF_mask);
1018 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
1019 STENCILMASK_shift, STENCILMASK_mask);
1020
1021 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
1022 STENCILFUNC_shift, STENCILFUNC_mask);
1023
1024 //back
1025 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
1026 STENCILREF_BF_shift, STENCILREF_BF_mask);
1027 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
1028 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1029
1030 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1031 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1032
1033 }
1034
1035 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1036 {
1037 context_t *context = R700_CONTEXT(ctx);
1038 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1039 const unsigned back = ctx->Stencil._BackFace;
1040
1041 R600_STATECHANGE(context, stencil);
1042
1043 // front
1044 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1045 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1046
1047 // back
1048 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1049 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1050
1051 }
1052
1053 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1054 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1055 {
1056 context_t *context = R700_CONTEXT(ctx);
1057 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1058 const unsigned back = ctx->Stencil._BackFace;
1059
1060 R600_STATECHANGE(context, db);
1061
1062 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1063 STENCILFAIL_shift, STENCILFAIL_mask);
1064 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1065 STENCILZFAIL_shift, STENCILZFAIL_mask);
1066 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1067 STENCILZPASS_shift, STENCILZPASS_mask);
1068
1069 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1070 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1071 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1072 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1073 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1074 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1075 }
1076
1077 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1078 {
1079 context_t *context = R700_CONTEXT(ctx);
1080 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1081 __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon);
1082 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1083 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1084 const GLfloat *v = ctx->Viewport._WindowMap.m;
1085 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1086 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1087 GLfloat y_scale, y_bias;
1088
1089 if (render_to_fbo) {
1090 y_scale = 1.0;
1091 y_bias = 0;
1092 } else {
1093 y_scale = -1.0;
1094 y_bias = yoffset;
1095 }
1096
1097 GLfloat sx = v[MAT_SX];
1098 GLfloat tx = v[MAT_TX] + xoffset;
1099 GLfloat sy = v[MAT_SY] * y_scale;
1100 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1101 GLfloat sz = v[MAT_SZ] * depthScale;
1102 GLfloat tz = v[MAT_TZ] * depthScale;
1103
1104 R600_STATECHANGE(context, vpt);
1105 R600_STATECHANGE(context, cl);
1106
1107 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1108 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1109
1110 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1111 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1112
1113 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1114 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1115
1116 if (ctx->Transform.DepthClamp) {
1117 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
1118 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
1119 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1120 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1121 } else {
1122 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0;
1123 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0;
1124 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1125 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1126 }
1127
1128 r700->viewport[id].enabled = GL_TRUE;
1129
1130 r700SetScissor(context);
1131 }
1132
1133
1134 static void r700Viewport(GLcontext * ctx,
1135 GLint x,
1136 GLint y,
1137 GLsizei width,
1138 GLsizei height) //--------------------
1139 {
1140 r700UpdateWindow(ctx, 0);
1141
1142 radeon_viewport(ctx, x, y, width, height);
1143 }
1144
1145 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1146 {
1147 r700UpdateWindow(ctx, 0);
1148 }
1149
1150 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1151 {
1152 context_t *context = R700_CONTEXT(ctx);
1153 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1154 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1155
1156 R600_STATECHANGE(context, su);
1157
1158 if (lineWidth > 0xFFFF)
1159 lineWidth = 0xFFFF;
1160 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1161 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1162 }
1163
1164 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1165 {
1166 context_t *context = R700_CONTEXT(ctx);
1167 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1168
1169 R600_STATECHANGE(context, sc);
1170
1171 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1172 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1173 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1174 }
1175
1176 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1177 {
1178 context_t *context = R700_CONTEXT(ctx);
1179 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1180
1181 R600_STATECHANGE(context, su);
1182
1183 if (state) {
1184 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1185 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1186 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1187 } else {
1188 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1189 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1190 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1191 }
1192 }
1193
1194 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1195 {
1196 context_t *context = R700_CONTEXT(ctx);
1197 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1198 GLfloat constant = units;
1199 GLchar depth = 0;
1200
1201 R600_STATECHANGE(context, poly);
1202
1203 switch (ctx->Visual.depthBits) {
1204 case 16:
1205 constant *= 4.0;
1206 depth = -16;
1207 break;
1208 case 24:
1209 constant *= 2.0;
1210 depth = -24;
1211 break;
1212 }
1213
1214 factor *= 12.0;
1215 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1216 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1217 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1218 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1219 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1220 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1221 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1222 }
1223
1224 static void r700UpdatePolygonMode(GLcontext * ctx)
1225 {
1226 context_t *context = R700_CONTEXT(ctx);
1227 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1228
1229 R600_STATECHANGE(context, su);
1230
1231 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1232
1233 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1234 if (ctx->Polygon.FrontMode != GL_FILL ||
1235 ctx->Polygon.BackMode != GL_FILL) {
1236 GLenum f, b;
1237
1238 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1239 * correctly by selecting the correct front and back face
1240 */
1241 f = ctx->Polygon.FrontMode;
1242 b = ctx->Polygon.BackMode;
1243
1244 /* Enable polygon mode */
1245 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1246
1247 switch (f) {
1248 case GL_LINE:
1249 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1250 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1251 break;
1252 case GL_POINT:
1253 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1254 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1255 break;
1256 case GL_FILL:
1257 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1258 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1259 break;
1260 }
1261
1262 switch (b) {
1263 case GL_LINE:
1264 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1265 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1266 break;
1267 case GL_POINT:
1268 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1269 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1270 break;
1271 case GL_FILL:
1272 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1273 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1274 break;
1275 }
1276 }
1277 }
1278
1279 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1280 {
1281 (void)face;
1282 (void)mode;
1283
1284 r700UpdatePolygonMode(ctx);
1285 }
1286
1287 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1288 {
1289 }
1290
1291 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1292 {
1293 context_t *context = R700_CONTEXT(ctx);
1294 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1295 GLint p;
1296 GLint *ip;
1297
1298 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1299 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1300
1301 R600_STATECHANGE(context, ucp);
1302
1303 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1304 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1305 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1306 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1307 }
1308
1309 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1310 {
1311 context_t *context = R700_CONTEXT(ctx);
1312 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1313 GLuint p;
1314
1315 p = cap - GL_CLIP_PLANE0;
1316
1317 R600_STATECHANGE(context, cl);
1318
1319 if (state) {
1320 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1321 r700->ucp[p].enabled = GL_TRUE;
1322 r700ClipPlane(ctx, cap, NULL);
1323 } else {
1324 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1325 r700->ucp[p].enabled = GL_FALSE;
1326 }
1327 }
1328
1329 void r700SetScissor(context_t *context) //---------------
1330 {
1331 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1332 unsigned x1, y1, x2, y2;
1333 int id = 0;
1334 struct radeon_renderbuffer *rrb;
1335
1336 rrb = radeon_get_colorbuffer(&context->radeon);
1337 if (!rrb || !rrb->bo) {
1338 return;
1339 }
1340 if (context->radeon.state.scissor.enabled) {
1341 x1 = context->radeon.state.scissor.rect.x1;
1342 y1 = context->radeon.state.scissor.rect.y1;
1343 x2 = context->radeon.state.scissor.rect.x2;
1344 y2 = context->radeon.state.scissor.rect.y2;
1345 /* r600 has exclusive BR scissors */
1346 if (context->radeon.radeonScreen->kernel_mm) {
1347 x2++;
1348 y2++;
1349 }
1350 } else {
1351 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1352 x1 = 0;
1353 y1 = 0;
1354 x2 = rrb->base.Width;
1355 y2 = rrb->base.Height;
1356 } else {
1357 x1 = rrb->dPriv->x;
1358 y1 = rrb->dPriv->y;
1359 x2 = rrb->dPriv->x + rrb->dPriv->w;
1360 y2 = rrb->dPriv->y + rrb->dPriv->h;
1361 }
1362 }
1363
1364 R600_STATECHANGE(context, scissor);
1365
1366 /* screen */
1367 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1368 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1369 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1370 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1371 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1372
1373 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1374 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1375 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1376 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1377
1378 /* window */
1379 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1380 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1381 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1382 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1383 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1384
1385 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1386 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1387 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1388 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1389
1390
1391 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1392 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1393 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1394 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1395 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1396 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1397 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1398 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1399
1400 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1401 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1402 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1403 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1404 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1405 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1406
1407 /* more....2d clip */
1408 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1409 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1410 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1411 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1412 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1413 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1414 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1415 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1416 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1417
1418 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1419 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1420 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1421 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1422 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1423 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1424 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1425 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1426 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1427
1428 r700->viewport[id].enabled = GL_TRUE;
1429 }
1430
1431 static void r700InitSQConfig(GLcontext * ctx)
1432 {
1433 context_t *context = R700_CONTEXT(ctx);
1434 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1435 int ps_prio;
1436 int vs_prio;
1437 int gs_prio;
1438 int es_prio;
1439 int num_ps_gprs;
1440 int num_vs_gprs;
1441 int num_gs_gprs;
1442 int num_es_gprs;
1443 int num_temp_gprs;
1444 int num_ps_threads;
1445 int num_vs_threads;
1446 int num_gs_threads;
1447 int num_es_threads;
1448 int num_ps_stack_entries;
1449 int num_vs_stack_entries;
1450 int num_gs_stack_entries;
1451 int num_es_stack_entries;
1452
1453 R600_STATECHANGE(context, sq);
1454
1455 // SQ
1456 ps_prio = 0;
1457 vs_prio = 1;
1458 gs_prio = 2;
1459 es_prio = 3;
1460 switch (context->radeon.radeonScreen->chip_family) {
1461 case CHIP_FAMILY_R600:
1462 num_ps_gprs = 192;
1463 num_vs_gprs = 56;
1464 num_temp_gprs = 4;
1465 num_gs_gprs = 0;
1466 num_es_gprs = 0;
1467 num_ps_threads = 136;
1468 num_vs_threads = 48;
1469 num_gs_threads = 4;
1470 num_es_threads = 4;
1471 num_ps_stack_entries = 128;
1472 num_vs_stack_entries = 128;
1473 num_gs_stack_entries = 0;
1474 num_es_stack_entries = 0;
1475 break;
1476 case CHIP_FAMILY_RV630:
1477 case CHIP_FAMILY_RV635:
1478 num_ps_gprs = 84;
1479 num_vs_gprs = 36;
1480 num_temp_gprs = 4;
1481 num_gs_gprs = 0;
1482 num_es_gprs = 0;
1483 num_ps_threads = 144;
1484 num_vs_threads = 40;
1485 num_gs_threads = 4;
1486 num_es_threads = 4;
1487 num_ps_stack_entries = 40;
1488 num_vs_stack_entries = 40;
1489 num_gs_stack_entries = 32;
1490 num_es_stack_entries = 16;
1491 break;
1492 case CHIP_FAMILY_RV610:
1493 case CHIP_FAMILY_RV620:
1494 case CHIP_FAMILY_RS780:
1495 case CHIP_FAMILY_RS880:
1496 default:
1497 num_ps_gprs = 84;
1498 num_vs_gprs = 36;
1499 num_temp_gprs = 4;
1500 num_gs_gprs = 0;
1501 num_es_gprs = 0;
1502 num_ps_threads = 136;
1503 num_vs_threads = 48;
1504 num_gs_threads = 4;
1505 num_es_threads = 4;
1506 num_ps_stack_entries = 40;
1507 num_vs_stack_entries = 40;
1508 num_gs_stack_entries = 32;
1509 num_es_stack_entries = 16;
1510 break;
1511 case CHIP_FAMILY_RV670:
1512 num_ps_gprs = 144;
1513 num_vs_gprs = 40;
1514 num_temp_gprs = 4;
1515 num_gs_gprs = 0;
1516 num_es_gprs = 0;
1517 num_ps_threads = 136;
1518 num_vs_threads = 48;
1519 num_gs_threads = 4;
1520 num_es_threads = 4;
1521 num_ps_stack_entries = 40;
1522 num_vs_stack_entries = 40;
1523 num_gs_stack_entries = 32;
1524 num_es_stack_entries = 16;
1525 break;
1526 case CHIP_FAMILY_RV770:
1527 num_ps_gprs = 192;
1528 num_vs_gprs = 56;
1529 num_temp_gprs = 4;
1530 num_gs_gprs = 0;
1531 num_es_gprs = 0;
1532 num_ps_threads = 188;
1533 num_vs_threads = 60;
1534 num_gs_threads = 0;
1535 num_es_threads = 0;
1536 num_ps_stack_entries = 256;
1537 num_vs_stack_entries = 256;
1538 num_gs_stack_entries = 0;
1539 num_es_stack_entries = 0;
1540 break;
1541 case CHIP_FAMILY_RV730:
1542 case CHIP_FAMILY_RV740:
1543 num_ps_gprs = 84;
1544 num_vs_gprs = 36;
1545 num_temp_gprs = 4;
1546 num_gs_gprs = 0;
1547 num_es_gprs = 0;
1548 num_ps_threads = 188;
1549 num_vs_threads = 60;
1550 num_gs_threads = 0;
1551 num_es_threads = 0;
1552 num_ps_stack_entries = 128;
1553 num_vs_stack_entries = 128;
1554 num_gs_stack_entries = 0;
1555 num_es_stack_entries = 0;
1556 break;
1557 case CHIP_FAMILY_RV710:
1558 num_ps_gprs = 192;
1559 num_vs_gprs = 56;
1560 num_temp_gprs = 4;
1561 num_gs_gprs = 0;
1562 num_es_gprs = 0;
1563 num_ps_threads = 144;
1564 num_vs_threads = 48;
1565 num_gs_threads = 0;
1566 num_es_threads = 0;
1567 num_ps_stack_entries = 128;
1568 num_vs_stack_entries = 128;
1569 num_gs_stack_entries = 0;
1570 num_es_stack_entries = 0;
1571 break;
1572 }
1573
1574 r700->sq_config.SQ_CONFIG.u32All = 0;
1575 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1576 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1577 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1578 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1579 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1580 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1581 else
1582 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1583
1584 if(GL_TRUE == r700->bShaderUseMemConstant)
1585 {
1586 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1587 }
1588 else
1589 {
1590 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1591 }
1592
1593 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1594 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1595 SETfield(r700->sq_config.SQ_CONFIG.u32All, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
1596 SETfield(r700->sq_config.SQ_CONFIG.u32All, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
1597 SETfield(r700->sq_config.SQ_CONFIG.u32All, es_prio, ES_PRIO_shift, ES_PRIO_mask);
1598
1599 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1600 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1601 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1602 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1603 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1604
1605 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1606 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1607 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1608
1609 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1610 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1611 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1612 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1613 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1614 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1615 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1616 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1617 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1618
1619 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1620 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1621 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1622 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1623 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1624
1625 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1626 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1627 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1628 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1629 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1630
1631 }
1632
1633 /**
1634 * Calculate initial hardware state and register state functions.
1635 * Assumes that the command buffer and state atoms have been
1636 * initialized already.
1637 */
1638 void r700InitState(GLcontext * ctx) //-------------------
1639 {
1640 context_t *context = R700_CONTEXT(ctx);
1641 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1642 int id = 0;
1643
1644 r700->TA_CNTL_AUX.u32All = 0;
1645 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1646 r700->VC_ENHANCE.u32All = 0;
1647 r700->DB_WATERMARKS.u32All = 0;
1648 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1649 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1650 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1651 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1652 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1653 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1654 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1655 r700->DB_DEBUG.u32All = 0x82000000;
1656 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1657 } else {
1658 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1659 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1660 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1661 }
1662
1663 /* Turn off vgt reuse */
1664 r700->VGT_REUSE_OFF.u32All = 0;
1665 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1666
1667 /* Specify offsetting and clamp values for vertices */
1668 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1669 r700->VGT_MIN_VTX_INDX.u32All = 0;
1670 r700->VGT_INDX_OFFSET.u32All = 0;
1671
1672 /* default shader connections. */
1673 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1674 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1675 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1676 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1677
1678 r700->SPI_THREAD_GROUPING.u32All = 0;
1679 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1680 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1681
1682 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1683 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1684 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1685
1686 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1687 r700->PA_SC_EDGERULE.u32All = 0;
1688 else
1689 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1690
1691 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1692 r700->PA_SC_MODE_CNTL.u32All = 0;
1693 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1694 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1695 } else {
1696 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1697 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1698 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1699 }
1700
1701 /* Do scale XY and Z by 1/W0. */
1702 r700->bEnablePerspective = GL_TRUE;
1703
1704 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1705 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1706 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1707
1708 /* Enable viewport scaling for all three axis */
1709 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1710 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1711 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1712 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1713 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1714 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1715
1716 /* GL uses last vtx for flat shading components */
1717 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1718
1719 /* Set up vertex control */
1720 r700->PA_SU_VTX_CNTL.u32All = 0;
1721 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1722 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1723 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1724 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1725
1726 /* to 1.0 = no guard band */
1727 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1728 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1729 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1730 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1731
1732 /* Enable all samples for multi-sample anti-aliasing */
1733 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1734 /* Turn off AA */
1735 r700->PA_SC_AA_CONFIG.u32All = 0;
1736
1737 r700->SX_MISC.u32All = 0;
1738
1739 r700InitSQConfig(ctx);
1740
1741 r700ColorMask(ctx,
1742 ctx->Color.ColorMask[0][RCOMP],
1743 ctx->Color.ColorMask[0][GCOMP],
1744 ctx->Color.ColorMask[0][BCOMP],
1745 ctx->Color.ColorMask[0][ACOMP]);
1746
1747 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1748 r700DepthMask(ctx, ctx->Depth.Mask);
1749 r700DepthFunc(ctx, ctx->Depth.Func);
1750 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1751 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1752 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1753 r700SetDBRenderState(ctx);
1754
1755 r700->DB_ALPHA_TO_MASK.u32All = 0;
1756 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1757 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1758 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1759 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1760
1761 /* stencil */
1762 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1763 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1764 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1765 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1766 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1767 ctx->Stencil.ZFailFunc[0],
1768 ctx->Stencil.ZPassFunc[0]);
1769
1770 r700UpdateCulling(ctx);
1771
1772 r700SetBlendState(ctx);
1773 r700SetLogicOpState(ctx);
1774
1775 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1776 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1777
1778 r700PointSize(ctx, 1.0);
1779
1780 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1781 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1782
1783 r700LineWidth(ctx, 1.0);
1784
1785 r700->PA_SC_LINE_CNTL.u32All = 0;
1786 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1787 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1788
1789 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1790 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1791 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1792 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1793 ctx->Polygon.OffsetUnits);
1794 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1795 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1796 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1797
1798 /* CB */
1799 r700BlendColor(ctx, ctx->Color.BlendColor);
1800
1801 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1802 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1803 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1804 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1805 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1806 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1807 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1808
1809 /* Disable color compares */
1810 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1811 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1812 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1813 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1814 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1815 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1816
1817 /* Zero out source */
1818 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1819
1820 /* Put a compare color in for error checking */
1821 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1822
1823 /* Set up color compare mask */
1824 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1825
1826 /* screen/window/view */
1827 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask);
1828
1829 context->radeon.hw.all_dirty = GL_TRUE;
1830
1831 }
1832
1833 void r700InitStateFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
1834 {
1835 functions->UpdateState = r700InvalidateState;
1836 functions->AlphaFunc = r700AlphaFunc;
1837 functions->BlendColor = r700BlendColor;
1838 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1839 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1840 functions->Enable = r700Enable;
1841 functions->ColorMask = r700ColorMask;
1842 functions->DepthFunc = r700DepthFunc;
1843 functions->DepthMask = r700DepthMask;
1844 functions->CullFace = r700CullFace;
1845 functions->Fogfv = r700Fogfv;
1846 functions->FrontFace = r700FrontFace;
1847 functions->ShadeModel = r700ShadeModel;
1848 functions->LogicOpcode = r700LogicOpcode;
1849
1850 /* ARB_point_parameters */
1851 functions->PointParameterfv = r700PointParameter;
1852
1853 /* Stencil related */
1854 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1855 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1856 functions->StencilOpSeparate = r700StencilOpSeparate;
1857
1858 /* Viewport related */
1859 functions->Viewport = r700Viewport;
1860 functions->DepthRange = r700DepthRange;
1861 functions->PointSize = r700PointSize;
1862 functions->LineWidth = r700LineWidth;
1863 functions->LineStipple = r700LineStipple;
1864
1865 functions->PolygonOffset = r700PolygonOffset;
1866 functions->PolygonMode = r700PolygonMode;
1867
1868 functions->RenderMode = r700RenderMode;
1869
1870 functions->ClipPlane = r700ClipPlane;
1871
1872 functions->Scissor = radeonScissor;
1873
1874 functions->DrawBuffer = radeonDrawBuffer;
1875 functions->ReadBuffer = radeonReadBuffer;
1876
1877 functions->CopyPixels = _mesa_meta_CopyPixels;
1878 functions->DrawPixels = _mesa_meta_DrawPixels;
1879 if (radeon->radeonScreen->kernel_mm)
1880 functions->ReadPixels = radeonReadPixels;
1881 }
1882