2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
49 #include "main/texformat.h"
51 #include "r600_context.h"
53 #include "r700_state.h"
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
59 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
);
60 static void r700UpdatePolygonMode(GLcontext
* ctx
);
61 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
);
62 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
);
64 void r700UpdateShaders(GLcontext
* ctx
)
66 context_t
*context
= R700_CONTEXT(ctx
);
68 /* should only happenen once, just after context is created */
69 /* TODO: shouldn't we fallback to sw here? */
70 if (!ctx
->FragmentProgram
._Current
) {
71 _mesa_fprintf(stderr
, "No ctx->FragmentProgram._Current!!\n");
75 r700SelectFragmentShader(ctx
);
77 r700SelectVertexShader(ctx
);
78 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
);
79 context
->radeon
.NewGLState
= 0;
83 * To correctly position primitives:
85 void r700UpdateViewportOffset(GLcontext
* ctx
) //------------------
87 context_t
*context
= R700_CONTEXT(ctx
);
88 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
89 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
90 GLfloat xoffset
= (GLfloat
) dPriv
->x
;
91 GLfloat yoffset
= (GLfloat
) dPriv
->y
+ dPriv
->h
;
92 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
95 GLfloat tx
= v
[MAT_TX
] + xoffset
;
96 GLfloat ty
= (-v
[MAT_TY
]) + yoffset
;
98 if (r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
!= tx
||
99 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
!= ty
) {
100 /* Note: this should also modify whatever data the context reset
103 R600_STATECHANGE(context
, vpt
);
104 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
105 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
108 radeonUpdateScissor(ctx
);
111 void r700UpdateStateParameters(GLcontext
* ctx
, GLuint new_state
) //--------------------
113 struct r700_fragment_program
*fp
=
114 (struct r700_fragment_program
*)ctx
->FragmentProgram
._Current
;
115 struct gl_program_parameter_list
*paramList
;
117 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
)))
120 if (!ctx
->FragmentProgram
._Current
|| !fp
)
123 paramList
= ctx
->FragmentProgram
._Current
->Base
.Parameters
;
128 _mesa_load_state_parameters(ctx
, paramList
);
133 * Called by Mesa after an internal state update.
135 static void r700InvalidateState(GLcontext
* ctx
, GLuint new_state
) //-------------------
137 context_t
*context
= R700_CONTEXT(ctx
);
139 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
141 _swrast_InvalidateState(ctx
, new_state
);
142 _swsetup_InvalidateState(ctx
, new_state
);
143 _vbo_InvalidateState(ctx
, new_state
);
144 _tnl_InvalidateState(ctx
, new_state
);
145 _ae_invalidate_state(ctx
, new_state
);
147 if (new_state
& _NEW_BUFFERS
) {
148 _mesa_update_framebuffer(ctx
);
149 /* this updates the DrawBuffer's Width/Height if it's a FBO */
150 _mesa_update_draw_buffer_bounds(ctx
);
152 R600_STATECHANGE(context
, cb_target
);
153 R600_STATECHANGE(context
, db_target
);
156 if (new_state
& (_NEW_LIGHT
)) {
157 R600_STATECHANGE(context
, su
);
158 if (ctx
->Light
.ProvokingVertex
== GL_LAST_VERTEX_CONVENTION
)
159 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
161 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
164 r700UpdateStateParameters(ctx
, new_state
);
166 R600_STATECHANGE(context
, cl
);
167 R600_STATECHANGE(context
, spi
);
169 if(GL_TRUE
== r700
->bEnablePerspective
)
171 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
172 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
173 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
175 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
177 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
178 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
182 /* For orthogonal case. */
183 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
184 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
186 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
188 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
189 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
192 context
->radeon
.NewGLState
|= new_state
;
195 static void r700SetDepthState(GLcontext
* ctx
)
197 context_t
*context
= R700_CONTEXT(ctx
);
198 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
200 R600_STATECHANGE(context
, db
);
204 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
207 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
211 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
214 switch (ctx
->Depth
.Func
)
217 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
218 ZFUNC_shift
, ZFUNC_mask
);
221 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
222 ZFUNC_shift
, ZFUNC_mask
);
225 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
226 ZFUNC_shift
, ZFUNC_mask
);
229 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
230 ZFUNC_shift
, ZFUNC_mask
);
233 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
234 ZFUNC_shift
, ZFUNC_mask
);
237 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
238 ZFUNC_shift
, ZFUNC_mask
);
241 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
242 ZFUNC_shift
, ZFUNC_mask
);
245 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
246 ZFUNC_shift
, ZFUNC_mask
);
249 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
250 ZFUNC_shift
, ZFUNC_mask
);
256 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
257 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
261 static void r700SetAlphaState(GLcontext
* ctx
)
263 context_t
*context
= R700_CONTEXT(ctx
);
264 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
265 uint32_t alpha_func
= REF_ALWAYS
;
266 GLboolean really_enabled
= ctx
->Color
.AlphaEnabled
;
268 R600_STATECHANGE(context
, sx
);
270 switch (ctx
->Color
.AlphaFunc
) {
272 alpha_func
= REF_NEVER
;
275 alpha_func
= REF_LESS
;
278 alpha_func
= REF_EQUAL
;
281 alpha_func
= REF_LEQUAL
;
284 alpha_func
= REF_GREATER
;
287 alpha_func
= REF_NOTEQUAL
;
290 alpha_func
= REF_GEQUAL
;
293 /*alpha_func = REF_ALWAYS; */
294 really_enabled
= GL_FALSE
;
298 if (really_enabled
) {
299 SETfield(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, alpha_func
,
300 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
301 SETbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
302 r700
->SX_ALPHA_REF
.f32All
= ctx
->Color
.AlphaRef
;
304 CLEARbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
309 static void r700AlphaFunc(GLcontext
* ctx
, GLenum func
, GLfloat ref
) //---------------
313 r700SetAlphaState(ctx
);
317 static void r700BlendColor(GLcontext
* ctx
, const GLfloat cf
[4]) //----------------
319 context_t
*context
= R700_CONTEXT(ctx
);
320 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
322 R600_STATECHANGE(context
, blnd_clr
);
324 r700
->CB_BLEND_RED
.f32All
= cf
[0];
325 r700
->CB_BLEND_GREEN
.f32All
= cf
[1];
326 r700
->CB_BLEND_BLUE
.f32All
= cf
[2];
327 r700
->CB_BLEND_ALPHA
.f32All
= cf
[3];
330 static int blend_factor(GLenum factor
, GLboolean is_src
)
340 return BLEND_DST_COLOR
;
342 case GL_ONE_MINUS_DST_COLOR
:
343 return BLEND_ONE_MINUS_DST_COLOR
;
346 return BLEND_SRC_COLOR
;
348 case GL_ONE_MINUS_SRC_COLOR
:
349 return BLEND_ONE_MINUS_SRC_COLOR
;
352 return BLEND_SRC_ALPHA
;
354 case GL_ONE_MINUS_SRC_ALPHA
:
355 return BLEND_ONE_MINUS_SRC_ALPHA
;
358 return BLEND_DST_ALPHA
;
360 case GL_ONE_MINUS_DST_ALPHA
:
361 return BLEND_ONE_MINUS_DST_ALPHA
;
363 case GL_SRC_ALPHA_SATURATE
:
364 return (is_src
) ? BLEND_SRC_ALPHA_SATURATE
: BLEND_ZERO
;
366 case GL_CONSTANT_COLOR
:
367 return BLEND_CONSTANT_COLOR
;
369 case GL_ONE_MINUS_CONSTANT_COLOR
:
370 return BLEND_ONE_MINUS_CONSTANT_COLOR
;
372 case GL_CONSTANT_ALPHA
:
373 return BLEND_CONSTANT_ALPHA
;
375 case GL_ONE_MINUS_CONSTANT_ALPHA
:
376 return BLEND_ONE_MINUS_CONSTANT_ALPHA
;
379 fprintf(stderr
, "unknown blend factor %x\n", factor
);
380 return (is_src
) ? BLEND_ONE
: BLEND_ZERO
;
385 static void r700SetBlendState(GLcontext
* ctx
)
387 context_t
*context
= R700_CONTEXT(ctx
);
388 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
390 uint32_t blend_reg
= 0, eqn
, eqnA
;
392 R600_STATECHANGE(context
, blnd
);
394 if (RGBA_LOGICOP_ENABLED(ctx
) || !ctx
->Color
.BlendEnabled
) {
396 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
398 BLEND_ZERO
, COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
400 COMB_DST_PLUS_SRC
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
402 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
404 BLEND_ZERO
, ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
406 COMB_DST_PLUS_SRC
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
407 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
408 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
410 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
415 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
416 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
418 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
419 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
421 switch (ctx
->Color
.BlendEquationRGB
) {
423 eqn
= COMB_DST_PLUS_SRC
;
425 case GL_FUNC_SUBTRACT
:
426 eqn
= COMB_SRC_MINUS_DST
;
428 case GL_FUNC_REVERSE_SUBTRACT
:
429 eqn
= COMB_DST_MINUS_SRC
;
432 eqn
= COMB_MIN_DST_SRC
;
435 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
438 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
441 eqn
= COMB_MAX_DST_SRC
;
444 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
447 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
452 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
453 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationRGB
);
457 eqn
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
460 blend_factor(ctx
->Color
.BlendSrcA
, GL_TRUE
),
461 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
463 blend_factor(ctx
->Color
.BlendDstA
, GL_FALSE
),
464 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
466 switch (ctx
->Color
.BlendEquationA
) {
468 eqnA
= COMB_DST_PLUS_SRC
;
470 case GL_FUNC_SUBTRACT
:
471 eqnA
= COMB_SRC_MINUS_DST
;
473 case GL_FUNC_REVERSE_SUBTRACT
:
474 eqnA
= COMB_DST_MINUS_SRC
;
477 eqnA
= COMB_MIN_DST_SRC
;
480 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
483 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
486 eqnA
= COMB_MAX_DST_SRC
;
489 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
492 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
496 "[%s:%u] Invalid A blend equation (0x%04x).\n",
497 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationA
);
502 eqnA
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
504 SETbit(blend_reg
, SEPARATE_ALPHA_BLEND_bit
);
506 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
507 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
509 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
510 SETbit(r700
->CB_COLOR_CONTROL
.u32All
, PER_MRT_BLEND_bit
);
512 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, (1 << id
),
513 TARGET_BLEND_ENABLE_shift
, TARGET_BLEND_ENABLE_mask
);
517 static void r700BlendEquationSeparate(GLcontext
* ctx
,
518 GLenum modeRGB
, GLenum modeA
) //-----------------
520 r700SetBlendState(ctx
);
523 static void r700BlendFuncSeparate(GLcontext
* ctx
,
524 GLenum sfactorRGB
, GLenum dfactorRGB
,
525 GLenum sfactorA
, GLenum dfactorA
) //------------------------
527 r700SetBlendState(ctx
);
531 * Translate LogicOp enums into hardware representation.
533 static GLuint
translate_logicop(GLenum logicop
)
542 case GL_COPY_INVERTED
:
562 case GL_AND_INVERTED
:
569 fprintf(stderr
, "unknown blend logic operation %x\n", logicop
);
575 * Used internally to update the r300->hw hardware state to match the
576 * current OpenGL state.
578 static void r700SetLogicOpState(GLcontext
*ctx
)
580 context_t
*context
= R700_CONTEXT(ctx
);
581 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
583 R600_STATECHANGE(context
, blnd
);
585 if (RGBA_LOGICOP_ENABLED(ctx
))
586 SETfield(r700
->CB_COLOR_CONTROL
.u32All
,
587 translate_logicop(ctx
->Color
.LogicOp
), ROP3_shift
, ROP3_mask
);
589 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, 0xCC, ROP3_shift
, ROP3_mask
);
593 * Called by Mesa when an application program changes the LogicOp state
596 static void r700LogicOpcode(GLcontext
*ctx
, GLenum logicop
)
598 if (RGBA_LOGICOP_ENABLED(ctx
))
599 r700SetLogicOpState(ctx
);
602 static void r700UpdateCulling(GLcontext
* ctx
)
604 context_t
*context
= R700_CONTEXT(ctx
);
605 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
607 R600_STATECHANGE(context
, su
);
609 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
610 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
611 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
613 if (ctx
->Polygon
.CullFlag
)
615 switch (ctx
->Polygon
.CullFaceMode
)
618 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
619 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
622 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
623 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
625 case GL_FRONT_AND_BACK
:
626 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
627 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
630 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
631 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
636 switch (ctx
->Polygon
.FrontFace
)
639 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
642 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
645 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
650 static void r700UpdateLineStipple(GLcontext
* ctx
)
652 context_t
*context
= R700_CONTEXT(ctx
);
653 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
655 R600_STATECHANGE(context
, sc
);
657 if (ctx
->Line
.StippleFlag
)
659 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
663 CLEARbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
667 static void r700Enable(GLcontext
* ctx
, GLenum cap
, GLboolean state
) //------------------
669 context_t
*context
= R700_CONTEXT(ctx
);
681 r700SetAlphaState(ctx
);
683 case GL_COLOR_LOGIC_OP
:
684 r700SetLogicOpState(ctx
);
685 /* fall-through, because logic op overrides blending */
687 r700SetBlendState(ctx
);
695 r700SetClipPlaneState(ctx
, cap
, state
);
698 r700SetDepthState(ctx
);
700 case GL_STENCIL_TEST
:
701 r700SetStencilState(ctx
, state
);
704 r700UpdateCulling(ctx
);
706 case GL_POLYGON_OFFSET_POINT
:
707 case GL_POLYGON_OFFSET_LINE
:
708 case GL_POLYGON_OFFSET_FILL
:
709 r700SetPolygonOffsetState(ctx
, state
);
711 case GL_SCISSOR_TEST
:
712 radeon_firevertices(&context
->radeon
);
713 context
->radeon
.state
.scissor
.enabled
= state
;
714 radeonUpdateScissor(ctx
);
716 case GL_LINE_STIPPLE
:
717 r700UpdateLineStipple(ctx
);
726 * Handle glColorMask()
728 static void r700ColorMask(GLcontext
* ctx
,
729 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //------------------
731 context_t
*context
= R700_CONTEXT(ctx
);
732 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
733 unsigned int mask
= ((r
? 1 : 0) |
738 if (mask
!= r700
->CB_TARGET_MASK
.u32All
) {
739 R600_STATECHANGE(context
, cb
);
740 SETfield(r700
->CB_TARGET_MASK
.u32All
, mask
, TARGET0_ENABLE_shift
, TARGET0_ENABLE_mask
);
745 * Change the depth testing function.
747 * \note Mesa already filters redundant calls to this function.
749 static void r700DepthFunc(GLcontext
* ctx
, GLenum func
) //--------------------
751 r700SetDepthState(ctx
);
755 * Enable/Disable depth writing.
757 * \note Mesa already filters redundant calls to this function.
759 static void r700DepthMask(GLcontext
* ctx
, GLboolean mask
) //------------------
761 r700SetDepthState(ctx
);
765 * Change the culling mode.
767 * \note Mesa already filters redundant calls to this function.
769 static void r700CullFace(GLcontext
* ctx
, GLenum mode
) //-----------------
771 r700UpdateCulling(ctx
);
774 /* =============================================================
777 static void r700Fogfv(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //--------------
782 * Change the polygon orientation.
784 * \note Mesa already filters redundant calls to this function.
786 static void r700FrontFace(GLcontext
* ctx
, GLenum mode
) //------------------
788 r700UpdateCulling(ctx
);
789 r700UpdatePolygonMode(ctx
);
792 static void r700ShadeModel(GLcontext
* ctx
, GLenum mode
) //--------------------
794 context_t
*context
= R700_CONTEXT(ctx
);
795 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
797 R600_STATECHANGE(context
, spi
);
799 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
802 SETbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
805 CLEARbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
812 /* =============================================================
815 static void r700PointSize(GLcontext
* ctx
, GLfloat size
)
817 context_t
*context
= R700_CONTEXT(ctx
);
818 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
820 R600_STATECHANGE(context
, su
);
822 /* We need to clamp to user defined range here, because
823 * the HW clamping happens only for per vertex point size. */
824 size
= CLAMP(size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
826 /* same size limits for AA, non-AA points */
827 size
= CLAMP(size
, ctx
->Const
.MinPointSize
, ctx
->Const
.MaxPointSize
);
829 /* format is 12.4 fixed point */
830 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 8.0),
831 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
832 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 8.0),
833 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
837 static void r700PointParameter(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //---------------
839 context_t
*context
= R700_CONTEXT(ctx
);
840 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
842 R600_STATECHANGE(context
, su
);
844 /* format is 12.4 fixed point */
846 case GL_POINT_SIZE_MIN
:
847 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MinSize
* 8.0),
848 MIN_SIZE_shift
, MIN_SIZE_mask
);
850 case GL_POINT_SIZE_MAX
:
851 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MaxSize
* 8.0),
852 MAX_SIZE_shift
, MAX_SIZE_mask
);
854 case GL_POINT_DISTANCE_ATTENUATION
:
856 case GL_POINT_FADE_THRESHOLD_SIZE
:
863 static int translate_stencil_func(int func
)
886 static int translate_stencil_op(int op
)
894 return STENCIL_REPLACE
;
896 return STENCIL_INCR_CLAMP
;
898 return STENCIL_DECR_CLAMP
;
899 case GL_INCR_WRAP_EXT
:
900 return STENCIL_INCR_WRAP
;
901 case GL_DECR_WRAP_EXT
:
902 return STENCIL_DECR_WRAP
;
904 return STENCIL_INVERT
;
906 WARN_ONCE("Do not know how to translate stencil op");
912 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
)
914 context_t
*context
= R700_CONTEXT(ctx
);
915 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
916 GLboolean hw_stencil
= GL_FALSE
;
918 if (ctx
->DrawBuffer
) {
919 struct radeon_renderbuffer
*rrbStencil
920 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
921 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
925 R600_STATECHANGE(context
, db
);
927 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
928 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, BACKFACE_ENABLE_bit
);
930 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
934 static void r700StencilFuncSeparate(GLcontext
* ctx
, GLenum face
,
935 GLenum func
, GLint ref
, GLuint mask
) //---------------------
937 context_t
*context
= R700_CONTEXT(ctx
);
938 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
939 const unsigned back
= ctx
->Stencil
._BackFace
;
941 R600_STATECHANGE(context
, stencil
);
942 R600_STATECHANGE(context
, db
);
945 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.Ref
[0],
946 STENCILREF_shift
, STENCILREF_mask
);
947 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.ValueMask
[0],
948 STENCILMASK_shift
, STENCILMASK_mask
);
950 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[0]),
951 STENCILFUNC_shift
, STENCILFUNC_mask
);
954 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.Ref
[back
],
955 STENCILREF_BF_shift
, STENCILREF_BF_mask
);
956 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.ValueMask
[back
],
957 STENCILMASK_BF_shift
, STENCILMASK_BF_mask
);
959 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[back
]),
960 STENCILFUNC_BF_shift
, STENCILFUNC_BF_mask
);
964 static void r700StencilMaskSeparate(GLcontext
* ctx
, GLenum face
, GLuint mask
) //--------------
966 context_t
*context
= R700_CONTEXT(ctx
);
967 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
968 const unsigned back
= ctx
->Stencil
._BackFace
;
970 R600_STATECHANGE(context
, stencil
);
973 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.WriteMask
[0],
974 STENCILWRITEMASK_shift
, STENCILWRITEMASK_mask
);
977 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.WriteMask
[back
],
978 STENCILWRITEMASK_BF_shift
, STENCILWRITEMASK_BF_mask
);
982 static void r700StencilOpSeparate(GLcontext
* ctx
, GLenum face
,
983 GLenum fail
, GLenum zfail
, GLenum zpass
) //--------------------
985 context_t
*context
= R700_CONTEXT(ctx
);
986 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
987 const unsigned back
= ctx
->Stencil
._BackFace
;
989 R600_STATECHANGE(context
, db
);
991 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[0]),
992 STENCILFAIL_shift
, STENCILFAIL_mask
);
993 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]),
994 STENCILZFAIL_shift
, STENCILZFAIL_mask
);
995 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]),
996 STENCILZPASS_shift
, STENCILZPASS_mask
);
998 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]),
999 STENCILFAIL_BF_shift
, STENCILFAIL_BF_mask
);
1000 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]),
1001 STENCILZFAIL_BF_shift
, STENCILZFAIL_BF_mask
);
1002 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]),
1003 STENCILZPASS_BF_shift
, STENCILZPASS_BF_mask
);
1006 static void r700UpdateWindow(GLcontext
* ctx
, int id
) //--------------------
1008 context_t
*context
= R700_CONTEXT(ctx
);
1009 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1010 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
1011 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
1012 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
1013 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1014 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1015 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
1016 GLfloat y_scale
, y_bias
;
1018 if (render_to_fbo
) {
1026 GLfloat sx
= v
[MAT_SX
];
1027 GLfloat tx
= v
[MAT_TX
] + xoffset
;
1028 GLfloat sy
= v
[MAT_SY
] * y_scale
;
1029 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
1030 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
1031 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
1033 R600_STATECHANGE(context
, vpt
);
1035 r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
1036 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
1038 r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
1039 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
1041 r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
1042 r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
1044 r700
->viewport
[id
].enabled
= GL_TRUE
;
1046 r700SetScissor(context
);
1050 static void r700Viewport(GLcontext
* ctx
,
1054 GLsizei height
) //--------------------
1056 r700UpdateWindow(ctx
, 0);
1058 radeon_viewport(ctx
, x
, y
, width
, height
);
1061 static void r700DepthRange(GLcontext
* ctx
, GLclampd nearval
, GLclampd farval
) //-------------
1063 r700UpdateWindow(ctx
, 0);
1066 static void r700LineWidth(GLcontext
* ctx
, GLfloat widthf
) //---------------
1068 context_t
*context
= R700_CONTEXT(ctx
);
1069 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1070 uint32_t lineWidth
= (uint32_t)((widthf
* 0.5) * (1 << 4));
1072 R600_STATECHANGE(context
, su
);
1074 if (lineWidth
> 0xFFFF)
1076 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
,(uint16_t)lineWidth
,
1077 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1080 static void r700LineStipple(GLcontext
*ctx
, GLint factor
, GLushort pattern
)
1082 context_t
*context
= R700_CONTEXT(ctx
);
1083 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1085 R600_STATECHANGE(context
, sc
);
1087 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, pattern
, LINE_PATTERN_shift
, LINE_PATTERN_mask
);
1088 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, (factor
-1), REPEAT_COUNT_shift
, REPEAT_COUNT_mask
);
1089 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, 1, AUTO_RESET_CNTL_shift
, AUTO_RESET_CNTL_mask
);
1092 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
)
1094 context_t
*context
= R700_CONTEXT(ctx
);
1095 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1097 R600_STATECHANGE(context
, su
);
1100 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1101 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1102 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1104 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1105 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1106 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1110 static void r700PolygonOffset(GLcontext
* ctx
, GLfloat factor
, GLfloat units
) //--------------
1112 context_t
*context
= R700_CONTEXT(ctx
);
1113 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1114 GLfloat constant
= units
;
1117 R600_STATECHANGE(context
, poly
);
1119 switch (ctx
->Visual
.depthBits
) {
1131 SETfield(r700
->PA_SU_POLY_OFFSET_DB_FMT_CNTL
.u32All
, depth
,
1132 POLY_OFFSET_NEG_NUM_DB_BITS_shift
, POLY_OFFSET_NEG_NUM_DB_BITS_mask
);
1133 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1134 r700
->PA_SU_POLY_OFFSET_FRONT_SCALE
.f32All
= factor
;
1135 r700
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.f32All
= constant
;
1136 r700
->PA_SU_POLY_OFFSET_BACK_SCALE
.f32All
= factor
;
1137 r700
->PA_SU_POLY_OFFSET_BACK_OFFSET
.f32All
= constant
;
1140 static void r700UpdatePolygonMode(GLcontext
* ctx
)
1142 context_t
*context
= R700_CONTEXT(ctx
);
1143 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1145 R600_STATECHANGE(context
, su
);
1147 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DISABLE_POLY_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1149 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1150 if (ctx
->Polygon
.FrontMode
!= GL_FILL
||
1151 ctx
->Polygon
.BackMode
!= GL_FILL
) {
1154 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1155 * correctly by selecting the correct front and back face
1157 if (ctx
->Polygon
.FrontFace
== GL_CCW
) {
1158 f
= ctx
->Polygon
.FrontMode
;
1159 b
= ctx
->Polygon
.BackMode
;
1161 f
= ctx
->Polygon
.BackMode
;
1162 b
= ctx
->Polygon
.FrontMode
;
1165 /* Enable polygon mode */
1166 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DUAL_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1170 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1171 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1174 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1175 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1178 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1179 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1185 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1186 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1189 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1190 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1193 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1194 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1200 static void r700PolygonMode(GLcontext
* ctx
, GLenum face
, GLenum mode
) //------------------
1205 r700UpdatePolygonMode(ctx
);
1208 static void r700RenderMode(GLcontext
* ctx
, GLenum mode
) //---------------------
1212 static void r700ClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1214 context_t
*context
= R700_CONTEXT(ctx
);
1215 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1219 p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1220 ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1222 R600_STATECHANGE(context
, ucp
);
1224 r700
->ucp
[p
].PA_CL_UCP_0_X
.u32All
= ip
[0];
1225 r700
->ucp
[p
].PA_CL_UCP_0_Y
.u32All
= ip
[1];
1226 r700
->ucp
[p
].PA_CL_UCP_0_Z
.u32All
= ip
[2];
1227 r700
->ucp
[p
].PA_CL_UCP_0_W
.u32All
= ip
[3];
1230 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
)
1232 context_t
*context
= R700_CONTEXT(ctx
);
1233 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1236 p
= cap
- GL_CLIP_PLANE0
;
1238 R600_STATECHANGE(context
, cl
);
1241 r700
->PA_CL_CLIP_CNTL
.u32All
|= (UCP_ENA_0_bit
<< p
);
1242 r700
->ucp
[p
].enabled
= GL_TRUE
;
1243 r700ClipPlane(ctx
, cap
, NULL
);
1245 r700
->PA_CL_CLIP_CNTL
.u32All
&= ~(UCP_ENA_0_bit
<< p
);
1246 r700
->ucp
[p
].enabled
= GL_FALSE
;
1250 void r700SetScissor(context_t
*context
) //---------------
1252 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1253 unsigned x1
, y1
, x2
, y2
;
1255 struct radeon_renderbuffer
*rrb
;
1257 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1258 if (!rrb
|| !rrb
->bo
) {
1261 if (context
->radeon
.state
.scissor
.enabled
) {
1262 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
1263 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
1264 x2
= context
->radeon
.state
.scissor
.rect
.x2
;
1265 y2
= context
->radeon
.state
.scissor
.rect
.y2
;
1266 /* r600 has exclusive BR scissors */
1267 if (context
->radeon
.radeonScreen
->kernel_mm
) {
1272 if (context
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
1275 x2
= rrb
->base
.Width
;
1276 y2
= rrb
->base
.Height
;
1280 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
1281 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
1285 R600_STATECHANGE(context
, scissor
);
1288 SETbit(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1289 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, x1
,
1290 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask
);
1291 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, y1
,
1292 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask
);
1294 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, x2
,
1295 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
1296 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, y2
,
1297 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
1300 SETbit(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1301 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
1302 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
1303 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
1304 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
1306 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
1307 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
1308 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
1309 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
1312 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
1313 PA_SC_CLIPRECT_0_TL__TL_X_shift
, PA_SC_CLIPRECT_0_TL__TL_X_mask
);
1314 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
1315 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
1316 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
1317 PA_SC_CLIPRECT_0_BR__BR_X_shift
, PA_SC_CLIPRECT_0_BR__BR_X_mask
);
1318 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
1319 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
1321 r700
->PA_SC_CLIPRECT_1_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1322 r700
->PA_SC_CLIPRECT_1_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1323 r700
->PA_SC_CLIPRECT_2_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1324 r700
->PA_SC_CLIPRECT_2_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1325 r700
->PA_SC_CLIPRECT_3_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1326 r700
->PA_SC_CLIPRECT_3_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1328 /* more....2d clip */
1329 SETbit(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1330 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
1331 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
1332 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
1333 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
1334 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
1335 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
1336 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
1337 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
1339 SETbit(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1340 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
1341 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
1342 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
1343 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
1344 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
1345 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
1346 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
1347 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
1349 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.u32All
= 0;
1350 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.u32All
= 0x3F800000;
1351 r700
->viewport
[id
].enabled
= GL_TRUE
;
1354 static void r700InitSQConfig(GLcontext
* ctx
)
1356 context_t
*context
= R700_CONTEXT(ctx
);
1357 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1371 int num_ps_stack_entries
;
1372 int num_vs_stack_entries
;
1373 int num_gs_stack_entries
;
1374 int num_es_stack_entries
;
1376 R600_STATECHANGE(context
, sq
);
1383 switch (context
->radeon
.radeonScreen
->chip_family
) {
1384 case CHIP_FAMILY_R600
:
1390 num_ps_threads
= 136;
1391 num_vs_threads
= 48;
1394 num_ps_stack_entries
= 128;
1395 num_vs_stack_entries
= 128;
1396 num_gs_stack_entries
= 0;
1397 num_es_stack_entries
= 0;
1399 case CHIP_FAMILY_RV630
:
1400 case CHIP_FAMILY_RV635
:
1406 num_ps_threads
= 144;
1407 num_vs_threads
= 40;
1410 num_ps_stack_entries
= 40;
1411 num_vs_stack_entries
= 40;
1412 num_gs_stack_entries
= 32;
1413 num_es_stack_entries
= 16;
1415 case CHIP_FAMILY_RV610
:
1416 case CHIP_FAMILY_RV620
:
1417 case CHIP_FAMILY_RS780
:
1418 case CHIP_FAMILY_RS880
:
1425 num_ps_threads
= 136;
1426 num_vs_threads
= 48;
1429 num_ps_stack_entries
= 40;
1430 num_vs_stack_entries
= 40;
1431 num_gs_stack_entries
= 32;
1432 num_es_stack_entries
= 16;
1434 case CHIP_FAMILY_RV670
:
1440 num_ps_threads
= 136;
1441 num_vs_threads
= 48;
1444 num_ps_stack_entries
= 40;
1445 num_vs_stack_entries
= 40;
1446 num_gs_stack_entries
= 32;
1447 num_es_stack_entries
= 16;
1449 case CHIP_FAMILY_RV770
:
1455 num_ps_threads
= 188;
1456 num_vs_threads
= 60;
1459 num_ps_stack_entries
= 256;
1460 num_vs_stack_entries
= 256;
1461 num_gs_stack_entries
= 0;
1462 num_es_stack_entries
= 0;
1464 case CHIP_FAMILY_RV730
:
1465 case CHIP_FAMILY_RV740
:
1471 num_ps_threads
= 188;
1472 num_vs_threads
= 60;
1475 num_ps_stack_entries
= 128;
1476 num_vs_stack_entries
= 128;
1477 num_gs_stack_entries
= 0;
1478 num_es_stack_entries
= 0;
1480 case CHIP_FAMILY_RV710
:
1486 num_ps_threads
= 144;
1487 num_vs_threads
= 48;
1490 num_ps_stack_entries
= 128;
1491 num_vs_stack_entries
= 128;
1492 num_gs_stack_entries
= 0;
1493 num_es_stack_entries
= 0;
1497 r700
->sq_config
.SQ_CONFIG
.u32All
= 0;
1498 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1499 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1500 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1501 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
1502 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1503 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1505 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1506 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
1507 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, ALU_INST_PREFER_VECTOR_bit
);
1508 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1509 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1510 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1511 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1513 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
1514 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1515 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1516 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_temp_gprs
,
1517 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1519 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
1520 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1521 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1523 r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
1524 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_ps_threads
,
1525 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1526 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_vs_threads
,
1527 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1528 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_gs_threads
,
1529 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1530 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_es_threads
,
1531 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1533 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
1534 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_ps_stack_entries
,
1535 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1536 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_vs_stack_entries
,
1537 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1539 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
1540 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_gs_stack_entries
,
1541 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1542 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_es_stack_entries
,
1543 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1548 * Calculate initial hardware state and register state functions.
1549 * Assumes that the command buffer and state atoms have been
1550 * initialized already.
1552 void r700InitState(GLcontext
* ctx
) //-------------------
1554 context_t
*context
= R700_CONTEXT(ctx
);
1555 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1558 radeon_firevertices(&context
->radeon
);
1560 r700
->TA_CNTL_AUX
.u32All
= 0;
1561 SETfield(r700
->TA_CNTL_AUX
.u32All
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1562 r700
->VC_ENHANCE
.u32All
= 0;
1563 r700
->DB_WATERMARKS
.u32All
= 0;
1564 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1565 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1566 SETfield(r700
->DB_WATERMARKS
.u32All
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1567 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1568 r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1569 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1570 SETfield(r700
->TA_CNTL_AUX
.u32All
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1571 r700
->DB_DEBUG
.u32All
= 0x82000000;
1572 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1574 SETfield(r700
->TA_CNTL_AUX
.u32All
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1575 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1576 SETbit(r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
, VS_PC_LIMIT_ENABLE_bit
);
1579 /* Turn off vgt reuse */
1580 r700
->VGT_REUSE_OFF
.u32All
= 0;
1581 SETbit(r700
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1583 /* Specify offsetting and clamp values for vertices */
1584 r700
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1585 r700
->VGT_MIN_VTX_INDX
.u32All
= 0;
1586 r700
->VGT_INDX_OFFSET
.u32All
= 0;
1588 /* default shader connections. */
1589 r700
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1590 r700
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1591 r700
->SPI_VS_OUT_ID_2
.u32All
= 0x0b0a0908;
1592 r700
->SPI_VS_OUT_ID_3
.u32All
= 0x0f0e0d0c;
1594 r700
->SPI_THREAD_GROUPING
.u32All
= 0;
1595 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
1596 SETfield(r700
->SPI_THREAD_GROUPING
.u32All
, 1, PS_GROUPING_shift
, PS_GROUPING_mask
);
1598 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1599 r700
->PA_SC_CLIPRECT_RULE
.u32All
= 0;
1600 SETfield(r700
->PA_SC_CLIPRECT_RULE
.u32All
, CLIP_RULE_mask
, CLIP_RULE_shift
, CLIP_RULE_mask
);
1602 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1603 r700
->PA_SC_EDGERULE
.u32All
= 0;
1605 r700
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1607 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1608 r700
->PA_SC_MODE_CNTL
.u32All
= 0;
1609 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, WALK_ORDER_ENABLE_bit
);
1610 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1612 r700
->PA_SC_MODE_CNTL
.u32All
= 0x00500000;
1613 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_REZ_ENABLE_bit
);
1614 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1617 /* Do scale XY and Z by 1/W0. */
1618 r700
->bEnablePerspective
= GL_TRUE
;
1619 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1620 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1621 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1623 /* Enable viewport scaling for all three axis */
1624 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1625 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1626 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1627 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1628 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1629 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1631 /* GL uses last vtx for flat shading components */
1632 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
1634 /* Set up vertex control */
1635 r700
->PA_SU_VTX_CNTL
.u32All
= 0;
1636 CLEARfield(r700
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1637 SETbit(r700
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1638 SETfield(r700
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1639 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1641 /* to 1.0 = no guard band */
1642 r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; /* 1.0 */
1643 r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000;
1644 r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000;
1645 r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000;
1647 /* Enable all samples for multi-sample anti-aliasing */
1648 r700
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1650 r700
->PA_SC_AA_CONFIG
.u32All
= 0;
1652 r700
->SX_MISC
.u32All
= 0;
1654 r700InitSQConfig(ctx
);
1657 ctx
->Color
.ColorMask
[RCOMP
],
1658 ctx
->Color
.ColorMask
[GCOMP
],
1659 ctx
->Color
.ColorMask
[BCOMP
],
1660 ctx
->Color
.ColorMask
[ACOMP
]);
1662 r700Enable(ctx
, GL_DEPTH_TEST
, ctx
->Depth
.Test
);
1663 r700DepthMask(ctx
, ctx
->Depth
.Mask
);
1664 r700DepthFunc(ctx
, ctx
->Depth
.Func
);
1665 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, DUAL_EXPORT_ENABLE_bit
);
1667 r700
->DB_DEPTH_CLEAR
.u32All
= 0x3F800000;
1669 r700
->DB_RENDER_CONTROL
.u32All
= 0;
1670 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, STENCIL_COMPRESS_DISABLE_bit
);
1671 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, DEPTH_COMPRESS_DISABLE_bit
);
1672 r700
->DB_RENDER_OVERRIDE
.u32All
= 0;
1673 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1674 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_SHADER_Z_ORDER_bit
);
1675 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
1676 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
1677 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
1678 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, NOOP_CULL_DISABLE_bit
);
1680 r700
->DB_ALPHA_TO_MASK
.u32All
= 0;
1681 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET0_shift
, ALPHA_TO_MASK_OFFSET0_mask
);
1682 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET1_shift
, ALPHA_TO_MASK_OFFSET1_mask
);
1683 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET2_shift
, ALPHA_TO_MASK_OFFSET2_mask
);
1684 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET3_shift
, ALPHA_TO_MASK_OFFSET3_mask
);
1687 r700Enable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
._Enabled
);
1688 r700StencilMaskSeparate(ctx
, 0, ctx
->Stencil
.WriteMask
[0]);
1689 r700StencilFuncSeparate(ctx
, 0, ctx
->Stencil
.Function
[0],
1690 ctx
->Stencil
.Ref
[0], ctx
->Stencil
.ValueMask
[0]);
1691 r700StencilOpSeparate(ctx
, 0, ctx
->Stencil
.FailFunc
[0],
1692 ctx
->Stencil
.ZFailFunc
[0],
1693 ctx
->Stencil
.ZPassFunc
[0]);
1695 r700UpdateCulling(ctx
);
1697 r700SetBlendState(ctx
);
1698 r700SetLogicOpState(ctx
);
1700 r700AlphaFunc(ctx
, ctx
->Color
.AlphaFunc
, ctx
->Color
.AlphaRef
);
1701 r700Enable(ctx
, GL_ALPHA_TEST
, ctx
->Color
.AlphaEnabled
);
1703 r700PointSize(ctx
, 1.0);
1705 CLEARfield(r700
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1706 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1708 r700LineWidth(ctx
, 1.0);
1710 r700
->PA_SC_LINE_CNTL
.u32All
= 0;
1711 CLEARbit(r700
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1712 SETbit(r700
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1714 r700ShadeModel(ctx
, ctx
->Light
.ShadeModel
);
1715 r700PolygonMode(ctx
, GL_FRONT
, ctx
->Polygon
.FrontMode
);
1716 r700PolygonMode(ctx
, GL_BACK
, ctx
->Polygon
.BackMode
);
1717 r700PolygonOffset(ctx
, ctx
->Polygon
.OffsetFactor
,
1718 ctx
->Polygon
.OffsetUnits
);
1719 r700Enable(ctx
, GL_POLYGON_OFFSET_POINT
, ctx
->Polygon
.OffsetPoint
);
1720 r700Enable(ctx
, GL_POLYGON_OFFSET_LINE
, ctx
->Polygon
.OffsetLine
);
1721 r700Enable(ctx
, GL_POLYGON_OFFSET_FILL
, ctx
->Polygon
.OffsetFill
);
1724 r700BlendColor(ctx
, ctx
->Color
.BlendColor
);
1726 r700
->CB_CLEAR_RED_R6XX
.f32All
= 1.0; //r6xx only
1727 r700
->CB_CLEAR_GREEN_R6XX
.f32All
= 0.0; //r6xx only
1728 r700
->CB_CLEAR_BLUE_R6XX
.f32All
= 1.0; //r6xx only
1729 r700
->CB_CLEAR_ALPHA_R6XX
.f32All
= 1.0; //r6xx only
1730 r700
->CB_FOG_RED_R6XX
.u32All
= 0; //r6xx only
1731 r700
->CB_FOG_GREEN_R6XX
.u32All
= 0; //r6xx only
1732 r700
->CB_FOG_BLUE_R6XX
.u32All
= 0; //r6xx only
1734 /* Disable color compares */
1735 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1736 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1737 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1738 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1739 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1740 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1742 /* Zero out source */
1743 r700
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1745 /* Put a compare color in for error checking */
1746 r700
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1748 /* Set up color compare mask */
1749 r700
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1751 /* screen/window/view */
1752 SETfield(r700
->CB_SHADER_MASK
.u32All
, 0xF, (4 * id
), OUTPUT0_ENABLE_mask
);
1754 context
->radeon
.hw
.all_dirty
= GL_TRUE
;
1758 void r700InitStateFuncs(struct dd_function_table
*functions
) //-----------------
1760 functions
->UpdateState
= r700InvalidateState
;
1761 functions
->AlphaFunc
= r700AlphaFunc
;
1762 functions
->BlendColor
= r700BlendColor
;
1763 functions
->BlendEquationSeparate
= r700BlendEquationSeparate
;
1764 functions
->BlendFuncSeparate
= r700BlendFuncSeparate
;
1765 functions
->Enable
= r700Enable
;
1766 functions
->ColorMask
= r700ColorMask
;
1767 functions
->DepthFunc
= r700DepthFunc
;
1768 functions
->DepthMask
= r700DepthMask
;
1769 functions
->CullFace
= r700CullFace
;
1770 functions
->Fogfv
= r700Fogfv
;
1771 functions
->FrontFace
= r700FrontFace
;
1772 functions
->ShadeModel
= r700ShadeModel
;
1773 functions
->LogicOpcode
= r700LogicOpcode
;
1775 /* ARB_point_parameters */
1776 functions
->PointParameterfv
= r700PointParameter
;
1778 /* Stencil related */
1779 functions
->StencilFuncSeparate
= r700StencilFuncSeparate
;
1780 functions
->StencilMaskSeparate
= r700StencilMaskSeparate
;
1781 functions
->StencilOpSeparate
= r700StencilOpSeparate
;
1783 /* Viewport related */
1784 functions
->Viewport
= r700Viewport
;
1785 functions
->DepthRange
= r700DepthRange
;
1786 functions
->PointSize
= r700PointSize
;
1787 functions
->LineWidth
= r700LineWidth
;
1788 functions
->LineStipple
= r700LineStipple
;
1790 functions
->PolygonOffset
= r700PolygonOffset
;
1791 functions
->PolygonMode
= r700PolygonMode
;
1793 functions
->RenderMode
= r700RenderMode
;
1795 functions
->ClipPlane
= r700ClipPlane
;
1797 functions
->Scissor
= radeonScissor
;
1799 functions
->DrawBuffer
= radeonDrawBuffer
;
1800 functions
->ReadBuffer
= radeonReadBuffer
;