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drivers: don't include texformat.h
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49
50 #include "r600_context.h"
51
52 #include "r700_state.h"
53
54 #include "r700_fragprog.h"
55 #include "r700_vertprog.h"
56
57
58 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
59 static void r700UpdatePolygonMode(GLcontext * ctx);
60 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
61 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
62
63 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
64 {
65 context_t *context = R700_CONTEXT(ctx);
66 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
67 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
68 int i;
69
70 /* should only happenen once, just after context is created */
71 /* TODO: shouldn't we fallback to sw here? */
72 if (!ctx->FragmentProgram._Current) {
73 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
74 return;
75 }
76
77 r700SelectFragmentShader(ctx);
78
79 if (context->radeon.NewGLState) {
80 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
81 /* mat states from state var not array for sw */
82 dummy_attrib[i].stride = 0;
83 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
84 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
85 }
86
87 _tnl_UpdateFixedFunctionProgram(ctx);
88
89 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
90 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
91 }
92 }
93
94 r700SelectVertexShader(ctx, 1);
95 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
96 context->radeon.NewGLState = 0;
97 }
98
99 void r700UpdateShaders2(GLcontext * ctx)
100 {
101 context_t *context = R700_CONTEXT(ctx);
102
103 /* should only happenen once, just after context is created */
104 /* TODO: shouldn't we fallback to sw here? */
105 if (!ctx->FragmentProgram._Current) {
106 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
107 return;
108 }
109
110 r700SelectFragmentShader(ctx);
111
112 r700SelectVertexShader(ctx, 2);
113 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
114 context->radeon.NewGLState = 0;
115 }
116
117 /*
118 * To correctly position primitives:
119 */
120 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
121 {
122 context_t *context = R700_CONTEXT(ctx);
123 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
124 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
125 GLfloat xoffset = (GLfloat) dPriv->x;
126 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
127 const GLfloat *v = ctx->Viewport._WindowMap.m;
128 int id = 0;
129
130 GLfloat tx = v[MAT_TX] + xoffset;
131 GLfloat ty = (-v[MAT_TY]) + yoffset;
132
133 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
134 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
135 /* Note: this should also modify whatever data the context reset
136 * code uses...
137 */
138 R600_STATECHANGE(context, vpt);
139 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
140 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
141 }
142
143 radeonUpdateScissor(ctx);
144 }
145
146 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
147 {
148 struct r700_fragment_program *fp =
149 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
150 struct gl_program_parameter_list *paramList;
151
152 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
153 return;
154
155 if (!ctx->FragmentProgram._Current || !fp)
156 return;
157
158 paramList = ctx->FragmentProgram._Current->Base.Parameters;
159
160 if (!paramList)
161 return;
162
163 _mesa_load_state_parameters(ctx, paramList);
164
165 }
166
167 /**
168 * Called by Mesa after an internal state update.
169 */
170 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
171 {
172 context_t *context = R700_CONTEXT(ctx);
173
174 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
175
176 _swrast_InvalidateState(ctx, new_state);
177 _swsetup_InvalidateState(ctx, new_state);
178 _vbo_InvalidateState(ctx, new_state);
179 _tnl_InvalidateState(ctx, new_state);
180 _ae_invalidate_state(ctx, new_state);
181
182 if (new_state & _NEW_BUFFERS) {
183 _mesa_update_framebuffer(ctx);
184 /* this updates the DrawBuffer's Width/Height if it's a FBO */
185 _mesa_update_draw_buffer_bounds(ctx);
186
187 R600_STATECHANGE(context, cb_target);
188 R600_STATECHANGE(context, db_target);
189 }
190
191 if (new_state & (_NEW_LIGHT)) {
192 R600_STATECHANGE(context, su);
193 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
194 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
195 else
196 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
197 }
198
199 r700UpdateStateParameters(ctx, new_state);
200
201 R600_STATECHANGE(context, cl);
202 R600_STATECHANGE(context, spi);
203
204 if(GL_TRUE == r700->bEnablePerspective)
205 {
206 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
207 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
208 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
209
210 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
211
212 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
213 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
214 }
215 else
216 {
217 /* For orthogonal case. */
218 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
219 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
220
221 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
222
223 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
224 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
225 }
226
227 context->radeon.NewGLState |= new_state;
228 }
229
230 static void r700SetDepthState(GLcontext * ctx)
231 {
232 context_t *context = R700_CONTEXT(ctx);
233 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
234
235 R600_STATECHANGE(context, db);
236
237 if (ctx->Depth.Test)
238 {
239 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
240 if (ctx->Depth.Mask)
241 {
242 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
243 }
244 else
245 {
246 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
247 }
248
249 switch (ctx->Depth.Func)
250 {
251 case GL_NEVER:
252 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
253 ZFUNC_shift, ZFUNC_mask);
254 break;
255 case GL_LESS:
256 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
257 ZFUNC_shift, ZFUNC_mask);
258 break;
259 case GL_EQUAL:
260 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
261 ZFUNC_shift, ZFUNC_mask);
262 break;
263 case GL_LEQUAL:
264 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
265 ZFUNC_shift, ZFUNC_mask);
266 break;
267 case GL_GREATER:
268 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
269 ZFUNC_shift, ZFUNC_mask);
270 break;
271 case GL_NOTEQUAL:
272 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
273 ZFUNC_shift, ZFUNC_mask);
274 break;
275 case GL_GEQUAL:
276 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
277 ZFUNC_shift, ZFUNC_mask);
278 break;
279 case GL_ALWAYS:
280 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
281 ZFUNC_shift, ZFUNC_mask);
282 break;
283 default:
284 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
285 ZFUNC_shift, ZFUNC_mask);
286 break;
287 }
288 }
289 else
290 {
291 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
292 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
293 }
294 }
295
296 static void r700SetAlphaState(GLcontext * ctx)
297 {
298 context_t *context = R700_CONTEXT(ctx);
299 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
300 uint32_t alpha_func = REF_ALWAYS;
301 GLboolean really_enabled = ctx->Color.AlphaEnabled;
302
303 R600_STATECHANGE(context, sx);
304
305 switch (ctx->Color.AlphaFunc) {
306 case GL_NEVER:
307 alpha_func = REF_NEVER;
308 break;
309 case GL_LESS:
310 alpha_func = REF_LESS;
311 break;
312 case GL_EQUAL:
313 alpha_func = REF_EQUAL;
314 break;
315 case GL_LEQUAL:
316 alpha_func = REF_LEQUAL;
317 break;
318 case GL_GREATER:
319 alpha_func = REF_GREATER;
320 break;
321 case GL_NOTEQUAL:
322 alpha_func = REF_NOTEQUAL;
323 break;
324 case GL_GEQUAL:
325 alpha_func = REF_GEQUAL;
326 break;
327 case GL_ALWAYS:
328 /*alpha_func = REF_ALWAYS; */
329 really_enabled = GL_FALSE;
330 break;
331 }
332
333 if (really_enabled) {
334 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
335 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
336 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
337 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
338 } else {
339 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
340 }
341
342 }
343
344 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
345 {
346 (void)func;
347 (void)ref;
348 r700SetAlphaState(ctx);
349 }
350
351
352 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
353 {
354 context_t *context = R700_CONTEXT(ctx);
355 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
356
357 R600_STATECHANGE(context, blnd_clr);
358
359 r700->CB_BLEND_RED.f32All = cf[0];
360 r700->CB_BLEND_GREEN.f32All = cf[1];
361 r700->CB_BLEND_BLUE.f32All = cf[2];
362 r700->CB_BLEND_ALPHA.f32All = cf[3];
363 }
364
365 static int blend_factor(GLenum factor, GLboolean is_src)
366 {
367 switch (factor) {
368 case GL_ZERO:
369 return BLEND_ZERO;
370 break;
371 case GL_ONE:
372 return BLEND_ONE;
373 break;
374 case GL_DST_COLOR:
375 return BLEND_DST_COLOR;
376 break;
377 case GL_ONE_MINUS_DST_COLOR:
378 return BLEND_ONE_MINUS_DST_COLOR;
379 break;
380 case GL_SRC_COLOR:
381 return BLEND_SRC_COLOR;
382 break;
383 case GL_ONE_MINUS_SRC_COLOR:
384 return BLEND_ONE_MINUS_SRC_COLOR;
385 break;
386 case GL_SRC_ALPHA:
387 return BLEND_SRC_ALPHA;
388 break;
389 case GL_ONE_MINUS_SRC_ALPHA:
390 return BLEND_ONE_MINUS_SRC_ALPHA;
391 break;
392 case GL_DST_ALPHA:
393 return BLEND_DST_ALPHA;
394 break;
395 case GL_ONE_MINUS_DST_ALPHA:
396 return BLEND_ONE_MINUS_DST_ALPHA;
397 break;
398 case GL_SRC_ALPHA_SATURATE:
399 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
400 break;
401 case GL_CONSTANT_COLOR:
402 return BLEND_CONSTANT_COLOR;
403 break;
404 case GL_ONE_MINUS_CONSTANT_COLOR:
405 return BLEND_ONE_MINUS_CONSTANT_COLOR;
406 break;
407 case GL_CONSTANT_ALPHA:
408 return BLEND_CONSTANT_ALPHA;
409 break;
410 case GL_ONE_MINUS_CONSTANT_ALPHA:
411 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
412 break;
413 default:
414 fprintf(stderr, "unknown blend factor %x\n", factor);
415 return (is_src) ? BLEND_ONE : BLEND_ZERO;
416 break;
417 }
418 }
419
420 static void r700SetBlendState(GLcontext * ctx)
421 {
422 context_t *context = R700_CONTEXT(ctx);
423 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
424 int id = 0;
425 uint32_t blend_reg = 0, eqn, eqnA;
426
427 R600_STATECHANGE(context, blnd);
428
429 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
430 SETfield(blend_reg,
431 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
432 SETfield(blend_reg,
433 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
434 SETfield(blend_reg,
435 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
436 SETfield(blend_reg,
437 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
438 SETfield(blend_reg,
439 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
440 SETfield(blend_reg,
441 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
442 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
443 r700->CB_BLEND_CONTROL.u32All = blend_reg;
444 else
445 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
446 return;
447 }
448
449 SETfield(blend_reg,
450 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
451 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
452 SETfield(blend_reg,
453 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
454 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
455
456 switch (ctx->Color.BlendEquationRGB) {
457 case GL_FUNC_ADD:
458 eqn = COMB_DST_PLUS_SRC;
459 break;
460 case GL_FUNC_SUBTRACT:
461 eqn = COMB_SRC_MINUS_DST;
462 break;
463 case GL_FUNC_REVERSE_SUBTRACT:
464 eqn = COMB_DST_MINUS_SRC;
465 break;
466 case GL_MIN:
467 eqn = COMB_MIN_DST_SRC;
468 SETfield(blend_reg,
469 BLEND_ONE,
470 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
471 SETfield(blend_reg,
472 BLEND_ONE,
473 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
474 break;
475 case GL_MAX:
476 eqn = COMB_MAX_DST_SRC;
477 SETfield(blend_reg,
478 BLEND_ONE,
479 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
480 SETfield(blend_reg,
481 BLEND_ONE,
482 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
483 break;
484
485 default:
486 fprintf(stderr,
487 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
488 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
489 return;
490 }
491 SETfield(blend_reg,
492 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
493
494 SETfield(blend_reg,
495 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
496 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
497 SETfield(blend_reg,
498 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
499 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
500
501 switch (ctx->Color.BlendEquationA) {
502 case GL_FUNC_ADD:
503 eqnA = COMB_DST_PLUS_SRC;
504 break;
505 case GL_FUNC_SUBTRACT:
506 eqnA = COMB_SRC_MINUS_DST;
507 break;
508 case GL_FUNC_REVERSE_SUBTRACT:
509 eqnA = COMB_DST_MINUS_SRC;
510 break;
511 case GL_MIN:
512 eqnA = COMB_MIN_DST_SRC;
513 SETfield(blend_reg,
514 BLEND_ONE,
515 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
516 SETfield(blend_reg,
517 BLEND_ONE,
518 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
519 break;
520 case GL_MAX:
521 eqnA = COMB_MAX_DST_SRC;
522 SETfield(blend_reg,
523 BLEND_ONE,
524 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
525 SETfield(blend_reg,
526 BLEND_ONE,
527 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
528 break;
529 default:
530 fprintf(stderr,
531 "[%s:%u] Invalid A blend equation (0x%04x).\n",
532 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
533 return;
534 }
535
536 SETfield(blend_reg,
537 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
538
539 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
540
541 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
542 r700->CB_BLEND_CONTROL.u32All = blend_reg;
543 else {
544 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
545 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
546 }
547 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
548 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
549
550 }
551
552 static void r700BlendEquationSeparate(GLcontext * ctx,
553 GLenum modeRGB, GLenum modeA) //-----------------
554 {
555 r700SetBlendState(ctx);
556 }
557
558 static void r700BlendFuncSeparate(GLcontext * ctx,
559 GLenum sfactorRGB, GLenum dfactorRGB,
560 GLenum sfactorA, GLenum dfactorA) //------------------------
561 {
562 r700SetBlendState(ctx);
563 }
564
565 /**
566 * Translate LogicOp enums into hardware representation.
567 */
568 static GLuint translate_logicop(GLenum logicop)
569 {
570 switch (logicop) {
571 case GL_CLEAR:
572 return 0x00;
573 case GL_SET:
574 return 0xff;
575 case GL_COPY:
576 return 0xcc;
577 case GL_COPY_INVERTED:
578 return 0x33;
579 case GL_NOOP:
580 return 0xaa;
581 case GL_INVERT:
582 return 0x55;
583 case GL_AND:
584 return 0x88;
585 case GL_NAND:
586 return 0x77;
587 case GL_OR:
588 return 0xee;
589 case GL_NOR:
590 return 0x11;
591 case GL_XOR:
592 return 0x66;
593 case GL_EQUIV:
594 return 0xaa;
595 case GL_AND_REVERSE:
596 return 0x44;
597 case GL_AND_INVERTED:
598 return 0x22;
599 case GL_OR_REVERSE:
600 return 0xdd;
601 case GL_OR_INVERTED:
602 return 0xbb;
603 default:
604 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
605 return 0xcc;
606 }
607 }
608
609 /**
610 * Used internally to update the r300->hw hardware state to match the
611 * current OpenGL state.
612 */
613 static void r700SetLogicOpState(GLcontext *ctx)
614 {
615 context_t *context = R700_CONTEXT(ctx);
616 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
617
618 R600_STATECHANGE(context, blnd);
619
620 if (RGBA_LOGICOP_ENABLED(ctx))
621 SETfield(r700->CB_COLOR_CONTROL.u32All,
622 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
623 else
624 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
625 }
626
627 /**
628 * Called by Mesa when an application program changes the LogicOp state
629 * via glLogicOp.
630 */
631 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
632 {
633 if (RGBA_LOGICOP_ENABLED(ctx))
634 r700SetLogicOpState(ctx);
635 }
636
637 static void r700UpdateCulling(GLcontext * ctx)
638 {
639 context_t *context = R700_CONTEXT(ctx);
640 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
641
642 R600_STATECHANGE(context, su);
643
644 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
645 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
646 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
647
648 if (ctx->Polygon.CullFlag)
649 {
650 switch (ctx->Polygon.CullFaceMode)
651 {
652 case GL_FRONT:
653 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
654 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
655 break;
656 case GL_BACK:
657 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
658 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
659 break;
660 case GL_FRONT_AND_BACK:
661 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
662 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
663 break;
664 default:
665 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
666 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
667 break;
668 }
669 }
670
671 switch (ctx->Polygon.FrontFace)
672 {
673 case GL_CW:
674 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
675 break;
676 case GL_CCW:
677 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
678 break;
679 default:
680 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
681 break;
682 }
683 }
684
685 static void r700UpdateLineStipple(GLcontext * ctx)
686 {
687 context_t *context = R700_CONTEXT(ctx);
688 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
689
690 R600_STATECHANGE(context, sc);
691
692 if (ctx->Line.StippleFlag)
693 {
694 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
695 }
696 else
697 {
698 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
699 }
700 }
701
702 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
703 {
704 context_t *context = R700_CONTEXT(ctx);
705
706 switch (cap) {
707 case GL_TEXTURE_1D:
708 case GL_TEXTURE_2D:
709 case GL_TEXTURE_3D:
710 /* empty */
711 break;
712 case GL_FOG:
713 /* empty */
714 break;
715 case GL_ALPHA_TEST:
716 r700SetAlphaState(ctx);
717 break;
718 case GL_COLOR_LOGIC_OP:
719 r700SetLogicOpState(ctx);
720 /* fall-through, because logic op overrides blending */
721 case GL_BLEND:
722 r700SetBlendState(ctx);
723 break;
724 case GL_CLIP_PLANE0:
725 case GL_CLIP_PLANE1:
726 case GL_CLIP_PLANE2:
727 case GL_CLIP_PLANE3:
728 case GL_CLIP_PLANE4:
729 case GL_CLIP_PLANE5:
730 r700SetClipPlaneState(ctx, cap, state);
731 break;
732 case GL_DEPTH_TEST:
733 r700SetDepthState(ctx);
734 break;
735 case GL_STENCIL_TEST:
736 r700SetStencilState(ctx, state);
737 break;
738 case GL_CULL_FACE:
739 r700UpdateCulling(ctx);
740 break;
741 case GL_POLYGON_OFFSET_POINT:
742 case GL_POLYGON_OFFSET_LINE:
743 case GL_POLYGON_OFFSET_FILL:
744 r700SetPolygonOffsetState(ctx, state);
745 break;
746 case GL_SCISSOR_TEST:
747 radeon_firevertices(&context->radeon);
748 context->radeon.state.scissor.enabled = state;
749 radeonUpdateScissor(ctx);
750 break;
751 case GL_LINE_STIPPLE:
752 r700UpdateLineStipple(ctx);
753 break;
754 default:
755 break;
756 }
757
758 }
759
760 /**
761 * Handle glColorMask()
762 */
763 static void r700ColorMask(GLcontext * ctx,
764 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
765 {
766 context_t *context = R700_CONTEXT(ctx);
767 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
768 unsigned int mask = ((r ? 1 : 0) |
769 (g ? 2 : 0) |
770 (b ? 4 : 0) |
771 (a ? 8 : 0));
772
773 if (mask != r700->CB_SHADER_MASK.u32All) {
774 R600_STATECHANGE(context, cb);
775 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
776 }
777 }
778
779 /**
780 * Change the depth testing function.
781 *
782 * \note Mesa already filters redundant calls to this function.
783 */
784 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
785 {
786 r700SetDepthState(ctx);
787 }
788
789 /**
790 * Enable/Disable depth writing.
791 *
792 * \note Mesa already filters redundant calls to this function.
793 */
794 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
795 {
796 r700SetDepthState(ctx);
797 }
798
799 /**
800 * Change the culling mode.
801 *
802 * \note Mesa already filters redundant calls to this function.
803 */
804 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
805 {
806 r700UpdateCulling(ctx);
807 }
808
809 /* =============================================================
810 * Fog
811 */
812 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
813 {
814 }
815
816 /**
817 * Change the polygon orientation.
818 *
819 * \note Mesa already filters redundant calls to this function.
820 */
821 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
822 {
823 r700UpdateCulling(ctx);
824 r700UpdatePolygonMode(ctx);
825 }
826
827 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
828 {
829 context_t *context = R700_CONTEXT(ctx);
830 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
831
832 R600_STATECHANGE(context, spi);
833
834 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
835 switch (mode) {
836 case GL_FLAT:
837 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
838 break;
839 case GL_SMOOTH:
840 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
841 break;
842 default:
843 return;
844 }
845 }
846
847 /* =============================================================
848 * Point state
849 */
850 static void r700PointSize(GLcontext * ctx, GLfloat size)
851 {
852 context_t *context = R700_CONTEXT(ctx);
853 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
854
855 R600_STATECHANGE(context, su);
856
857 /* We need to clamp to user defined range here, because
858 * the HW clamping happens only for per vertex point size. */
859 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
860
861 /* same size limits for AA, non-AA points */
862 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
863
864 /* format is 12.4 fixed point */
865 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
866 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
867 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
868 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
869
870 }
871
872 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
873 {
874 context_t *context = R700_CONTEXT(ctx);
875 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
876
877 R600_STATECHANGE(context, su);
878
879 /* format is 12.4 fixed point */
880 switch (pname) {
881 case GL_POINT_SIZE_MIN:
882 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
883 MIN_SIZE_shift, MIN_SIZE_mask);
884 break;
885 case GL_POINT_SIZE_MAX:
886 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
887 MAX_SIZE_shift, MAX_SIZE_mask);
888 break;
889 case GL_POINT_DISTANCE_ATTENUATION:
890 break;
891 case GL_POINT_FADE_THRESHOLD_SIZE:
892 break;
893 default:
894 break;
895 }
896 }
897
898 static int translate_stencil_func(int func)
899 {
900 switch (func) {
901 case GL_NEVER:
902 return REF_NEVER;
903 case GL_LESS:
904 return REF_LESS;
905 case GL_EQUAL:
906 return REF_EQUAL;
907 case GL_LEQUAL:
908 return REF_LEQUAL;
909 case GL_GREATER:
910 return REF_GREATER;
911 case GL_NOTEQUAL:
912 return REF_NOTEQUAL;
913 case GL_GEQUAL:
914 return REF_GEQUAL;
915 case GL_ALWAYS:
916 return REF_ALWAYS;
917 }
918 return 0;
919 }
920
921 static int translate_stencil_op(int op)
922 {
923 switch (op) {
924 case GL_KEEP:
925 return STENCIL_KEEP;
926 case GL_ZERO:
927 return STENCIL_ZERO;
928 case GL_REPLACE:
929 return STENCIL_REPLACE;
930 case GL_INCR:
931 return STENCIL_INCR_CLAMP;
932 case GL_DECR:
933 return STENCIL_DECR_CLAMP;
934 case GL_INCR_WRAP_EXT:
935 return STENCIL_INCR_WRAP;
936 case GL_DECR_WRAP_EXT:
937 return STENCIL_DECR_WRAP;
938 case GL_INVERT:
939 return STENCIL_INVERT;
940 default:
941 WARN_ONCE("Do not know how to translate stencil op");
942 return STENCIL_KEEP;
943 }
944 return 0;
945 }
946
947 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
948 {
949 context_t *context = R700_CONTEXT(ctx);
950 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
951 GLboolean hw_stencil = GL_FALSE;
952
953 if (ctx->DrawBuffer) {
954 struct radeon_renderbuffer *rrbStencil
955 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
956 hw_stencil = (rrbStencil && rrbStencil->bo);
957 }
958
959 if (hw_stencil) {
960 R600_STATECHANGE(context, db);
961 if (state) {
962 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
963 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
964 } else
965 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
966 }
967 }
968
969 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
970 GLenum func, GLint ref, GLuint mask) //---------------------
971 {
972 context_t *context = R700_CONTEXT(ctx);
973 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
974 const unsigned back = ctx->Stencil._BackFace;
975
976 R600_STATECHANGE(context, stencil);
977 R600_STATECHANGE(context, db);
978
979 //front
980 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
981 STENCILREF_shift, STENCILREF_mask);
982 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
983 STENCILMASK_shift, STENCILMASK_mask);
984
985 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
986 STENCILFUNC_shift, STENCILFUNC_mask);
987
988 //back
989 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
990 STENCILREF_BF_shift, STENCILREF_BF_mask);
991 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
992 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
993
994 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
995 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
996
997 }
998
999 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1000 {
1001 context_t *context = R700_CONTEXT(ctx);
1002 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1003 const unsigned back = ctx->Stencil._BackFace;
1004
1005 R600_STATECHANGE(context, stencil);
1006
1007 // front
1008 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1009 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1010
1011 // back
1012 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1013 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1014
1015 }
1016
1017 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1018 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1019 {
1020 context_t *context = R700_CONTEXT(ctx);
1021 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1022 const unsigned back = ctx->Stencil._BackFace;
1023
1024 R600_STATECHANGE(context, db);
1025
1026 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1027 STENCILFAIL_shift, STENCILFAIL_mask);
1028 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1029 STENCILZFAIL_shift, STENCILZFAIL_mask);
1030 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1031 STENCILZPASS_shift, STENCILZPASS_mask);
1032
1033 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1034 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1035 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1036 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1037 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1038 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1039 }
1040
1041 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1042 {
1043 context_t *context = R700_CONTEXT(ctx);
1044 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1045 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1046 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1047 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1048 const GLfloat *v = ctx->Viewport._WindowMap.m;
1049 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1050 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1051 GLfloat y_scale, y_bias;
1052
1053 if (render_to_fbo) {
1054 y_scale = 1.0;
1055 y_bias = 0;
1056 } else {
1057 y_scale = -1.0;
1058 y_bias = yoffset;
1059 }
1060
1061 GLfloat sx = v[MAT_SX];
1062 GLfloat tx = v[MAT_TX] + xoffset;
1063 GLfloat sy = v[MAT_SY] * y_scale;
1064 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1065 GLfloat sz = v[MAT_SZ] * depthScale;
1066 GLfloat tz = v[MAT_TZ] * depthScale;
1067
1068 R600_STATECHANGE(context, vpt);
1069
1070 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1071 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1072
1073 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1074 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1075
1076 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1077 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1078
1079 r700->viewport[id].enabled = GL_TRUE;
1080
1081 r700SetScissor(context);
1082 }
1083
1084
1085 static void r700Viewport(GLcontext * ctx,
1086 GLint x,
1087 GLint y,
1088 GLsizei width,
1089 GLsizei height) //--------------------
1090 {
1091 r700UpdateWindow(ctx, 0);
1092
1093 radeon_viewport(ctx, x, y, width, height);
1094 }
1095
1096 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1097 {
1098 r700UpdateWindow(ctx, 0);
1099 }
1100
1101 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1102 {
1103 context_t *context = R700_CONTEXT(ctx);
1104 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1105 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1106
1107 R600_STATECHANGE(context, su);
1108
1109 if (lineWidth > 0xFFFF)
1110 lineWidth = 0xFFFF;
1111 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1112 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1113 }
1114
1115 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1116 {
1117 context_t *context = R700_CONTEXT(ctx);
1118 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1119
1120 R600_STATECHANGE(context, sc);
1121
1122 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1123 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1124 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1125 }
1126
1127 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1128 {
1129 context_t *context = R700_CONTEXT(ctx);
1130 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1131
1132 R600_STATECHANGE(context, su);
1133
1134 if (state) {
1135 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1136 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1137 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1138 } else {
1139 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1140 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1141 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1142 }
1143 }
1144
1145 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1146 {
1147 context_t *context = R700_CONTEXT(ctx);
1148 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1149 GLfloat constant = units;
1150 GLchar depth = 0;
1151
1152 R600_STATECHANGE(context, poly);
1153
1154 switch (ctx->Visual.depthBits) {
1155 case 16:
1156 constant *= 4.0;
1157 depth = -16;
1158 break;
1159 case 24:
1160 constant *= 2.0;
1161 depth = -24;
1162 break;
1163 }
1164
1165 factor *= 12.0;
1166 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1167 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1168 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1169 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1170 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1171 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1172 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1173 }
1174
1175 static void r700UpdatePolygonMode(GLcontext * ctx)
1176 {
1177 context_t *context = R700_CONTEXT(ctx);
1178 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1179
1180 R600_STATECHANGE(context, su);
1181
1182 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1183
1184 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1185 if (ctx->Polygon.FrontMode != GL_FILL ||
1186 ctx->Polygon.BackMode != GL_FILL) {
1187 GLenum f, b;
1188
1189 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1190 * correctly by selecting the correct front and back face
1191 */
1192 if (ctx->Polygon.FrontFace == GL_CCW) {
1193 f = ctx->Polygon.FrontMode;
1194 b = ctx->Polygon.BackMode;
1195 } else {
1196 f = ctx->Polygon.BackMode;
1197 b = ctx->Polygon.FrontMode;
1198 }
1199
1200 /* Enable polygon mode */
1201 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1202
1203 switch (f) {
1204 case GL_LINE:
1205 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1206 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1207 break;
1208 case GL_POINT:
1209 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1210 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1211 break;
1212 case GL_FILL:
1213 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1214 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1215 break;
1216 }
1217
1218 switch (b) {
1219 case GL_LINE:
1220 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1221 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1222 break;
1223 case GL_POINT:
1224 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1225 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1226 break;
1227 case GL_FILL:
1228 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1229 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1230 break;
1231 }
1232 }
1233 }
1234
1235 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1236 {
1237 (void)face;
1238 (void)mode;
1239
1240 r700UpdatePolygonMode(ctx);
1241 }
1242
1243 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1244 {
1245 }
1246
1247 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1248 {
1249 context_t *context = R700_CONTEXT(ctx);
1250 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1251 GLint p;
1252 GLint *ip;
1253
1254 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1255 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1256
1257 R600_STATECHANGE(context, ucp);
1258
1259 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1260 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1261 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1262 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1263 }
1264
1265 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1266 {
1267 context_t *context = R700_CONTEXT(ctx);
1268 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1269 GLuint p;
1270
1271 p = cap - GL_CLIP_PLANE0;
1272
1273 R600_STATECHANGE(context, cl);
1274
1275 if (state) {
1276 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1277 r700->ucp[p].enabled = GL_TRUE;
1278 r700ClipPlane(ctx, cap, NULL);
1279 } else {
1280 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1281 r700->ucp[p].enabled = GL_FALSE;
1282 }
1283 }
1284
1285 void r700SetScissor(context_t *context) //---------------
1286 {
1287 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1288 unsigned x1, y1, x2, y2;
1289 int id = 0;
1290 struct radeon_renderbuffer *rrb;
1291
1292 rrb = radeon_get_colorbuffer(&context->radeon);
1293 if (!rrb || !rrb->bo) {
1294 return;
1295 }
1296 if (context->radeon.state.scissor.enabled) {
1297 /* r600 has exclusive scissors */
1298 x1 = context->radeon.state.scissor.rect.x1;
1299 y1 = context->radeon.state.scissor.rect.y1;
1300 x2 = context->radeon.state.scissor.rect.x2 + 1;
1301 y2 = context->radeon.state.scissor.rect.y2 + 1;
1302 } else {
1303 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1304 x1 = 0;
1305 y1 = 0;
1306 x2 = rrb->base.Width;
1307 y2 = rrb->base.Height;
1308 } else {
1309 x1 = rrb->dPriv->x;
1310 y1 = rrb->dPriv->y;
1311 x2 = rrb->dPriv->x + rrb->dPriv->w;
1312 y2 = rrb->dPriv->y + rrb->dPriv->h;
1313 }
1314 }
1315
1316 R600_STATECHANGE(context, scissor);
1317
1318 /* screen */
1319 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1320 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1321 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1322 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1323 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1324
1325 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1326 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1327 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1328 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1329
1330 /* window */
1331 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1332 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1333 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1334 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1335 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1336
1337 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1338 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1339 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1340 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1341
1342
1343 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1344 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1345 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1346 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1347 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1348 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1349 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1350 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1351
1352 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1353 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1354 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1355 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1356 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1357 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1358
1359 /* more....2d clip */
1360 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1361 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1362 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1363 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1364 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1365 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1366 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1367 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1368 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1369
1370 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1371 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1372 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1373 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1374 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1375 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1376 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1377 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1378 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1379
1380 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1381 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1382 r700->viewport[id].enabled = GL_TRUE;
1383 }
1384
1385 static void r700InitSQConfig(GLcontext * ctx)
1386 {
1387 context_t *context = R700_CONTEXT(ctx);
1388 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1389 int ps_prio;
1390 int vs_prio;
1391 int gs_prio;
1392 int es_prio;
1393 int num_ps_gprs;
1394 int num_vs_gprs;
1395 int num_gs_gprs;
1396 int num_es_gprs;
1397 int num_temp_gprs;
1398 int num_ps_threads;
1399 int num_vs_threads;
1400 int num_gs_threads;
1401 int num_es_threads;
1402 int num_ps_stack_entries;
1403 int num_vs_stack_entries;
1404 int num_gs_stack_entries;
1405 int num_es_stack_entries;
1406
1407 R600_STATECHANGE(context, sq);
1408
1409 // SQ
1410 ps_prio = 0;
1411 vs_prio = 1;
1412 gs_prio = 2;
1413 es_prio = 3;
1414 switch (context->radeon.radeonScreen->chip_family) {
1415 case CHIP_FAMILY_R600:
1416 num_ps_gprs = 192;
1417 num_vs_gprs = 56;
1418 num_temp_gprs = 4;
1419 num_gs_gprs = 0;
1420 num_es_gprs = 0;
1421 num_ps_threads = 136;
1422 num_vs_threads = 48;
1423 num_gs_threads = 4;
1424 num_es_threads = 4;
1425 num_ps_stack_entries = 128;
1426 num_vs_stack_entries = 128;
1427 num_gs_stack_entries = 0;
1428 num_es_stack_entries = 0;
1429 break;
1430 case CHIP_FAMILY_RV630:
1431 case CHIP_FAMILY_RV635:
1432 num_ps_gprs = 84;
1433 num_vs_gprs = 36;
1434 num_temp_gprs = 4;
1435 num_gs_gprs = 0;
1436 num_es_gprs = 0;
1437 num_ps_threads = 144;
1438 num_vs_threads = 40;
1439 num_gs_threads = 4;
1440 num_es_threads = 4;
1441 num_ps_stack_entries = 40;
1442 num_vs_stack_entries = 40;
1443 num_gs_stack_entries = 32;
1444 num_es_stack_entries = 16;
1445 break;
1446 case CHIP_FAMILY_RV610:
1447 case CHIP_FAMILY_RV620:
1448 case CHIP_FAMILY_RS780:
1449 case CHIP_FAMILY_RS880:
1450 default:
1451 num_ps_gprs = 84;
1452 num_vs_gprs = 36;
1453 num_temp_gprs = 4;
1454 num_gs_gprs = 0;
1455 num_es_gprs = 0;
1456 num_ps_threads = 136;
1457 num_vs_threads = 48;
1458 num_gs_threads = 4;
1459 num_es_threads = 4;
1460 num_ps_stack_entries = 40;
1461 num_vs_stack_entries = 40;
1462 num_gs_stack_entries = 32;
1463 num_es_stack_entries = 16;
1464 break;
1465 case CHIP_FAMILY_RV670:
1466 num_ps_gprs = 144;
1467 num_vs_gprs = 40;
1468 num_temp_gprs = 4;
1469 num_gs_gprs = 0;
1470 num_es_gprs = 0;
1471 num_ps_threads = 136;
1472 num_vs_threads = 48;
1473 num_gs_threads = 4;
1474 num_es_threads = 4;
1475 num_ps_stack_entries = 40;
1476 num_vs_stack_entries = 40;
1477 num_gs_stack_entries = 32;
1478 num_es_stack_entries = 16;
1479 break;
1480 case CHIP_FAMILY_RV770:
1481 num_ps_gprs = 192;
1482 num_vs_gprs = 56;
1483 num_temp_gprs = 4;
1484 num_gs_gprs = 0;
1485 num_es_gprs = 0;
1486 num_ps_threads = 188;
1487 num_vs_threads = 60;
1488 num_gs_threads = 0;
1489 num_es_threads = 0;
1490 num_ps_stack_entries = 256;
1491 num_vs_stack_entries = 256;
1492 num_gs_stack_entries = 0;
1493 num_es_stack_entries = 0;
1494 break;
1495 case CHIP_FAMILY_RV730:
1496 case CHIP_FAMILY_RV740:
1497 num_ps_gprs = 84;
1498 num_vs_gprs = 36;
1499 num_temp_gprs = 4;
1500 num_gs_gprs = 0;
1501 num_es_gprs = 0;
1502 num_ps_threads = 188;
1503 num_vs_threads = 60;
1504 num_gs_threads = 0;
1505 num_es_threads = 0;
1506 num_ps_stack_entries = 128;
1507 num_vs_stack_entries = 128;
1508 num_gs_stack_entries = 0;
1509 num_es_stack_entries = 0;
1510 break;
1511 case CHIP_FAMILY_RV710:
1512 num_ps_gprs = 192;
1513 num_vs_gprs = 56;
1514 num_temp_gprs = 4;
1515 num_gs_gprs = 0;
1516 num_es_gprs = 0;
1517 num_ps_threads = 144;
1518 num_vs_threads = 48;
1519 num_gs_threads = 0;
1520 num_es_threads = 0;
1521 num_ps_stack_entries = 128;
1522 num_vs_stack_entries = 128;
1523 num_gs_stack_entries = 0;
1524 num_es_stack_entries = 0;
1525 break;
1526 }
1527
1528 r700->sq_config.SQ_CONFIG.u32All = 0;
1529 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1530 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1531 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1532 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1533 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1534 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1535 else
1536 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1537 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1538 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1539 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1540 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1541 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1542 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1543
1544 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1545 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1546 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1547 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1548 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1549
1550 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1551 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1552 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1553
1554 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1555 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1556 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1557 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1558 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1559 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1560 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1561 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1562 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1563
1564 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1565 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1566 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1567 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1568 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1569
1570 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1571 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1572 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1573 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1574 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1575
1576 }
1577
1578 /**
1579 * Calculate initial hardware state and register state functions.
1580 * Assumes that the command buffer and state atoms have been
1581 * initialized already.
1582 */
1583 void r700InitState(GLcontext * ctx) //-------------------
1584 {
1585 context_t *context = R700_CONTEXT(ctx);
1586 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1587 int id = 0;
1588
1589 radeon_firevertices(&context->radeon);
1590
1591 r700->TA_CNTL_AUX.u32All = 0;
1592 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1593 r700->VC_ENHANCE.u32All = 0;
1594 r700->DB_WATERMARKS.u32All = 0;
1595 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1596 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1597 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1598 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1599 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1600 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1601 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1602 r700->DB_DEBUG.u32All = 0x82000000;
1603 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1604 } else {
1605 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1606 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1607 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1608 }
1609
1610 /* Turn off vgt reuse */
1611 r700->VGT_REUSE_OFF.u32All = 0;
1612 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1613
1614 /* Specify offsetting and clamp values for vertices */
1615 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1616 r700->VGT_MIN_VTX_INDX.u32All = 0;
1617 r700->VGT_INDX_OFFSET.u32All = 0;
1618
1619 /* default shader connections. */
1620 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1621 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1622 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1623 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1624
1625 r700->SPI_THREAD_GROUPING.u32All = 0;
1626 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1627 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1628
1629 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1630 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1631 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1632
1633 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1634 r700->PA_SC_EDGERULE.u32All = 0;
1635 else
1636 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1637
1638 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1639 r700->PA_SC_MODE_CNTL.u32All = 0;
1640 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1641 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1642 } else {
1643 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1644 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1645 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1646 }
1647
1648 /* Do scale XY and Z by 1/W0. */
1649 r700->bEnablePerspective = GL_TRUE;
1650 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1651 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1652 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1653
1654 /* Enable viewport scaling for all three axis */
1655 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1656 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1657 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1658 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1659 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1660 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1661
1662 /* GL uses last vtx for flat shading components */
1663 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1664
1665 /* Set up vertex control */
1666 r700->PA_SU_VTX_CNTL.u32All = 0;
1667 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1668 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1669 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1670 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1671
1672 /* to 1.0 = no guard band */
1673 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1674 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1675 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1676 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1677
1678 /* Enable all samples for multi-sample anti-aliasing */
1679 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1680 /* Turn off AA */
1681 r700->PA_SC_AA_CONFIG.u32All = 0;
1682
1683 r700->SX_MISC.u32All = 0;
1684
1685 r700InitSQConfig(ctx);
1686
1687 r700ColorMask(ctx,
1688 ctx->Color.ColorMask[RCOMP],
1689 ctx->Color.ColorMask[GCOMP],
1690 ctx->Color.ColorMask[BCOMP],
1691 ctx->Color.ColorMask[ACOMP]);
1692
1693 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1694 r700DepthMask(ctx, ctx->Depth.Mask);
1695 r700DepthFunc(ctx, ctx->Depth.Func);
1696 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1697
1698 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1699
1700 r700->DB_RENDER_CONTROL.u32All = 0;
1701 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1702 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1703 r700->DB_RENDER_OVERRIDE.u32All = 0;
1704 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1705 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1706 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1707 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1708 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1709
1710 r700->DB_ALPHA_TO_MASK.u32All = 0;
1711 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1712 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1713 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1714 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1715
1716 /* stencil */
1717 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1718 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1719 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1720 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1721 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1722 ctx->Stencil.ZFailFunc[0],
1723 ctx->Stencil.ZPassFunc[0]);
1724
1725 r700UpdateCulling(ctx);
1726
1727 r700SetBlendState(ctx);
1728 r700SetLogicOpState(ctx);
1729
1730 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1731 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1732
1733 r700PointSize(ctx, 1.0);
1734
1735 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1736 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1737
1738 r700LineWidth(ctx, 1.0);
1739
1740 r700->PA_SC_LINE_CNTL.u32All = 0;
1741 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1742 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1743
1744 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1745 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1746 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1747 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1748 ctx->Polygon.OffsetUnits);
1749 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1750 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1751 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1752
1753 /* CB */
1754 r700BlendColor(ctx, ctx->Color.BlendColor);
1755
1756 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1757 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1758 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1759 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1760 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1761 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1762 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1763
1764 /* Disable color compares */
1765 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1766 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1767 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1768 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1769 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1770 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1771
1772 /* Zero out source */
1773 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1774
1775 /* Put a compare color in for error checking */
1776 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1777
1778 /* Set up color compare mask */
1779 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1780
1781 /* screen/window/view */
1782 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1783
1784 context->radeon.hw.all_dirty = GL_TRUE;
1785
1786 }
1787
1788 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1789 {
1790 functions->UpdateState = r700InvalidateState;
1791 functions->AlphaFunc = r700AlphaFunc;
1792 functions->BlendColor = r700BlendColor;
1793 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1794 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1795 functions->Enable = r700Enable;
1796 functions->ColorMask = r700ColorMask;
1797 functions->DepthFunc = r700DepthFunc;
1798 functions->DepthMask = r700DepthMask;
1799 functions->CullFace = r700CullFace;
1800 functions->Fogfv = r700Fogfv;
1801 functions->FrontFace = r700FrontFace;
1802 functions->ShadeModel = r700ShadeModel;
1803 functions->LogicOpcode = r700LogicOpcode;
1804
1805 /* ARB_point_parameters */
1806 functions->PointParameterfv = r700PointParameter;
1807
1808 /* Stencil related */
1809 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1810 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1811 functions->StencilOpSeparate = r700StencilOpSeparate;
1812
1813 /* Viewport related */
1814 functions->Viewport = r700Viewport;
1815 functions->DepthRange = r700DepthRange;
1816 functions->PointSize = r700PointSize;
1817 functions->LineWidth = r700LineWidth;
1818 functions->LineStipple = r700LineStipple;
1819
1820 functions->PolygonOffset = r700PolygonOffset;
1821 functions->PolygonMode = r700PolygonMode;
1822
1823 functions->RenderMode = r700RenderMode;
1824
1825 functions->ClipPlane = r700ClipPlane;
1826
1827 functions->Scissor = radeonScissor;
1828
1829 functions->DrawBuffer = radeonDrawBuffer;
1830 functions->ReadBuffer = radeonReadBuffer;
1831
1832 }
1833