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Merge branch 'mesa_7_6_branch'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63
64 void r700UpdateShaders(GLcontext * ctx)
65 {
66 context_t *context = R700_CONTEXT(ctx);
67
68 /* should only happenen once, just after context is created */
69 /* TODO: shouldn't we fallback to sw here? */
70 if (!ctx->FragmentProgram._Current) {
71 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
72 return;
73 }
74
75 r700SelectFragmentShader(ctx);
76
77 r700SelectVertexShader(ctx);
78 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
79 context->radeon.NewGLState = 0;
80 }
81
82 /*
83 * To correctly position primitives:
84 */
85 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
86 {
87 context_t *context = R700_CONTEXT(ctx);
88 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
89 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
90 GLfloat xoffset = (GLfloat) dPriv->x;
91 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
92 const GLfloat *v = ctx->Viewport._WindowMap.m;
93 int id = 0;
94
95 GLfloat tx = v[MAT_TX] + xoffset;
96 GLfloat ty = (-v[MAT_TY]) + yoffset;
97
98 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
99 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
100 /* Note: this should also modify whatever data the context reset
101 * code uses...
102 */
103 R600_STATECHANGE(context, vpt);
104 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
105 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
106 }
107
108 radeonUpdateScissor(ctx);
109 }
110
111 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
112 {
113 struct r700_fragment_program *fp =
114 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
115 struct gl_program_parameter_list *paramList;
116
117 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
118 return;
119
120 if (!ctx->FragmentProgram._Current || !fp)
121 return;
122
123 paramList = ctx->FragmentProgram._Current->Base.Parameters;
124
125 if (!paramList)
126 return;
127
128 _mesa_load_state_parameters(ctx, paramList);
129
130 }
131
132 /**
133 * Called by Mesa after an internal state update.
134 */
135 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
136 {
137 context_t *context = R700_CONTEXT(ctx);
138
139 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
140
141 _swrast_InvalidateState(ctx, new_state);
142 _swsetup_InvalidateState(ctx, new_state);
143 _vbo_InvalidateState(ctx, new_state);
144 _tnl_InvalidateState(ctx, new_state);
145 _ae_invalidate_state(ctx, new_state);
146
147 if (new_state & _NEW_BUFFERS) {
148 _mesa_update_framebuffer(ctx);
149 /* this updates the DrawBuffer's Width/Height if it's a FBO */
150 _mesa_update_draw_buffer_bounds(ctx);
151
152 R600_STATECHANGE(context, cb_target);
153 R600_STATECHANGE(context, db_target);
154 }
155
156 if (new_state & (_NEW_LIGHT)) {
157 R600_STATECHANGE(context, su);
158 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
159 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
160 else
161 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
162 }
163
164 r700UpdateStateParameters(ctx, new_state);
165
166 R600_STATECHANGE(context, cl);
167 R600_STATECHANGE(context, spi);
168
169 if(GL_TRUE == r700->bEnablePerspective)
170 {
171 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
172 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
173 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
174
175 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
176
177 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
178 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
179 }
180 else
181 {
182 /* For orthogonal case. */
183 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
184 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
185
186 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
187
188 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
189 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
190 }
191
192 context->radeon.NewGLState |= new_state;
193 }
194
195 static void r700SetDepthState(GLcontext * ctx)
196 {
197 context_t *context = R700_CONTEXT(ctx);
198 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
199
200 R600_STATECHANGE(context, db);
201
202 if (ctx->Depth.Test)
203 {
204 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
205 if (ctx->Depth.Mask)
206 {
207 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
208 }
209 else
210 {
211 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
212 }
213
214 switch (ctx->Depth.Func)
215 {
216 case GL_NEVER:
217 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
218 ZFUNC_shift, ZFUNC_mask);
219 break;
220 case GL_LESS:
221 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
222 ZFUNC_shift, ZFUNC_mask);
223 break;
224 case GL_EQUAL:
225 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
226 ZFUNC_shift, ZFUNC_mask);
227 break;
228 case GL_LEQUAL:
229 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
230 ZFUNC_shift, ZFUNC_mask);
231 break;
232 case GL_GREATER:
233 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
234 ZFUNC_shift, ZFUNC_mask);
235 break;
236 case GL_NOTEQUAL:
237 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
238 ZFUNC_shift, ZFUNC_mask);
239 break;
240 case GL_GEQUAL:
241 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
242 ZFUNC_shift, ZFUNC_mask);
243 break;
244 case GL_ALWAYS:
245 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
246 ZFUNC_shift, ZFUNC_mask);
247 break;
248 default:
249 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
250 ZFUNC_shift, ZFUNC_mask);
251 break;
252 }
253 }
254 else
255 {
256 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
257 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
258 }
259 }
260
261 static void r700SetAlphaState(GLcontext * ctx)
262 {
263 context_t *context = R700_CONTEXT(ctx);
264 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
265 uint32_t alpha_func = REF_ALWAYS;
266 GLboolean really_enabled = ctx->Color.AlphaEnabled;
267
268 R600_STATECHANGE(context, sx);
269
270 switch (ctx->Color.AlphaFunc) {
271 case GL_NEVER:
272 alpha_func = REF_NEVER;
273 break;
274 case GL_LESS:
275 alpha_func = REF_LESS;
276 break;
277 case GL_EQUAL:
278 alpha_func = REF_EQUAL;
279 break;
280 case GL_LEQUAL:
281 alpha_func = REF_LEQUAL;
282 break;
283 case GL_GREATER:
284 alpha_func = REF_GREATER;
285 break;
286 case GL_NOTEQUAL:
287 alpha_func = REF_NOTEQUAL;
288 break;
289 case GL_GEQUAL:
290 alpha_func = REF_GEQUAL;
291 break;
292 case GL_ALWAYS:
293 /*alpha_func = REF_ALWAYS; */
294 really_enabled = GL_FALSE;
295 break;
296 }
297
298 if (really_enabled) {
299 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
300 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
301 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
302 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
303 } else {
304 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
305 }
306
307 }
308
309 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
310 {
311 (void)func;
312 (void)ref;
313 r700SetAlphaState(ctx);
314 }
315
316
317 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
318 {
319 context_t *context = R700_CONTEXT(ctx);
320 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
321
322 R600_STATECHANGE(context, blnd_clr);
323
324 r700->CB_BLEND_RED.f32All = cf[0];
325 r700->CB_BLEND_GREEN.f32All = cf[1];
326 r700->CB_BLEND_BLUE.f32All = cf[2];
327 r700->CB_BLEND_ALPHA.f32All = cf[3];
328 }
329
330 static int blend_factor(GLenum factor, GLboolean is_src)
331 {
332 switch (factor) {
333 case GL_ZERO:
334 return BLEND_ZERO;
335 break;
336 case GL_ONE:
337 return BLEND_ONE;
338 break;
339 case GL_DST_COLOR:
340 return BLEND_DST_COLOR;
341 break;
342 case GL_ONE_MINUS_DST_COLOR:
343 return BLEND_ONE_MINUS_DST_COLOR;
344 break;
345 case GL_SRC_COLOR:
346 return BLEND_SRC_COLOR;
347 break;
348 case GL_ONE_MINUS_SRC_COLOR:
349 return BLEND_ONE_MINUS_SRC_COLOR;
350 break;
351 case GL_SRC_ALPHA:
352 return BLEND_SRC_ALPHA;
353 break;
354 case GL_ONE_MINUS_SRC_ALPHA:
355 return BLEND_ONE_MINUS_SRC_ALPHA;
356 break;
357 case GL_DST_ALPHA:
358 return BLEND_DST_ALPHA;
359 break;
360 case GL_ONE_MINUS_DST_ALPHA:
361 return BLEND_ONE_MINUS_DST_ALPHA;
362 break;
363 case GL_SRC_ALPHA_SATURATE:
364 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
365 break;
366 case GL_CONSTANT_COLOR:
367 return BLEND_CONSTANT_COLOR;
368 break;
369 case GL_ONE_MINUS_CONSTANT_COLOR:
370 return BLEND_ONE_MINUS_CONSTANT_COLOR;
371 break;
372 case GL_CONSTANT_ALPHA:
373 return BLEND_CONSTANT_ALPHA;
374 break;
375 case GL_ONE_MINUS_CONSTANT_ALPHA:
376 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
377 break;
378 default:
379 fprintf(stderr, "unknown blend factor %x\n", factor);
380 return (is_src) ? BLEND_ONE : BLEND_ZERO;
381 break;
382 }
383 }
384
385 static void r700SetBlendState(GLcontext * ctx)
386 {
387 context_t *context = R700_CONTEXT(ctx);
388 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
389 int id = 0;
390 uint32_t blend_reg = 0, eqn, eqnA;
391
392 R600_STATECHANGE(context, blnd);
393
394 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
395 SETfield(blend_reg,
396 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
397 SETfield(blend_reg,
398 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
399 SETfield(blend_reg,
400 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
401 SETfield(blend_reg,
402 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
403 SETfield(blend_reg,
404 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
405 SETfield(blend_reg,
406 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
407 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
408 r700->CB_BLEND_CONTROL.u32All = blend_reg;
409 else
410 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
411 return;
412 }
413
414 SETfield(blend_reg,
415 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
416 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
417 SETfield(blend_reg,
418 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
419 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
420
421 switch (ctx->Color.BlendEquationRGB) {
422 case GL_FUNC_ADD:
423 eqn = COMB_DST_PLUS_SRC;
424 break;
425 case GL_FUNC_SUBTRACT:
426 eqn = COMB_SRC_MINUS_DST;
427 break;
428 case GL_FUNC_REVERSE_SUBTRACT:
429 eqn = COMB_DST_MINUS_SRC;
430 break;
431 case GL_MIN:
432 eqn = COMB_MIN_DST_SRC;
433 SETfield(blend_reg,
434 BLEND_ONE,
435 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
436 SETfield(blend_reg,
437 BLEND_ONE,
438 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
439 break;
440 case GL_MAX:
441 eqn = COMB_MAX_DST_SRC;
442 SETfield(blend_reg,
443 BLEND_ONE,
444 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
445 SETfield(blend_reg,
446 BLEND_ONE,
447 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
448 break;
449
450 default:
451 fprintf(stderr,
452 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
453 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
454 return;
455 }
456 SETfield(blend_reg,
457 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
458
459 SETfield(blend_reg,
460 blend_factor(ctx->Color.BlendSrcA, GL_TRUE),
461 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
462 SETfield(blend_reg,
463 blend_factor(ctx->Color.BlendDstA, GL_FALSE),
464 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
465
466 switch (ctx->Color.BlendEquationA) {
467 case GL_FUNC_ADD:
468 eqnA = COMB_DST_PLUS_SRC;
469 break;
470 case GL_FUNC_SUBTRACT:
471 eqnA = COMB_SRC_MINUS_DST;
472 break;
473 case GL_FUNC_REVERSE_SUBTRACT:
474 eqnA = COMB_DST_MINUS_SRC;
475 break;
476 case GL_MIN:
477 eqnA = COMB_MIN_DST_SRC;
478 SETfield(blend_reg,
479 BLEND_ONE,
480 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
481 SETfield(blend_reg,
482 BLEND_ONE,
483 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
484 break;
485 case GL_MAX:
486 eqnA = COMB_MAX_DST_SRC;
487 SETfield(blend_reg,
488 BLEND_ONE,
489 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
490 SETfield(blend_reg,
491 BLEND_ONE,
492 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
493 break;
494 default:
495 fprintf(stderr,
496 "[%s:%u] Invalid A blend equation (0x%04x).\n",
497 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
498 return;
499 }
500
501 SETfield(blend_reg,
502 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
503
504 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
505
506 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
507 r700->CB_BLEND_CONTROL.u32All = blend_reg;
508 else {
509 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
510 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
511 }
512 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
513 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
514
515 }
516
517 static void r700BlendEquationSeparate(GLcontext * ctx,
518 GLenum modeRGB, GLenum modeA) //-----------------
519 {
520 r700SetBlendState(ctx);
521 }
522
523 static void r700BlendFuncSeparate(GLcontext * ctx,
524 GLenum sfactorRGB, GLenum dfactorRGB,
525 GLenum sfactorA, GLenum dfactorA) //------------------------
526 {
527 r700SetBlendState(ctx);
528 }
529
530 /**
531 * Translate LogicOp enums into hardware representation.
532 */
533 static GLuint translate_logicop(GLenum logicop)
534 {
535 switch (logicop) {
536 case GL_CLEAR:
537 return 0x00;
538 case GL_SET:
539 return 0xff;
540 case GL_COPY:
541 return 0xcc;
542 case GL_COPY_INVERTED:
543 return 0x33;
544 case GL_NOOP:
545 return 0xaa;
546 case GL_INVERT:
547 return 0x55;
548 case GL_AND:
549 return 0x88;
550 case GL_NAND:
551 return 0x77;
552 case GL_OR:
553 return 0xee;
554 case GL_NOR:
555 return 0x11;
556 case GL_XOR:
557 return 0x66;
558 case GL_EQUIV:
559 return 0xaa;
560 case GL_AND_REVERSE:
561 return 0x44;
562 case GL_AND_INVERTED:
563 return 0x22;
564 case GL_OR_REVERSE:
565 return 0xdd;
566 case GL_OR_INVERTED:
567 return 0xbb;
568 default:
569 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
570 return 0xcc;
571 }
572 }
573
574 /**
575 * Used internally to update the r300->hw hardware state to match the
576 * current OpenGL state.
577 */
578 static void r700SetLogicOpState(GLcontext *ctx)
579 {
580 context_t *context = R700_CONTEXT(ctx);
581 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
582
583 R600_STATECHANGE(context, blnd);
584
585 if (RGBA_LOGICOP_ENABLED(ctx))
586 SETfield(r700->CB_COLOR_CONTROL.u32All,
587 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
588 else
589 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
590 }
591
592 /**
593 * Called by Mesa when an application program changes the LogicOp state
594 * via glLogicOp.
595 */
596 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
597 {
598 if (RGBA_LOGICOP_ENABLED(ctx))
599 r700SetLogicOpState(ctx);
600 }
601
602 static void r700UpdateCulling(GLcontext * ctx)
603 {
604 context_t *context = R700_CONTEXT(ctx);
605 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
606
607 R600_STATECHANGE(context, su);
608
609 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
610 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
611 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
612
613 if (ctx->Polygon.CullFlag)
614 {
615 switch (ctx->Polygon.CullFaceMode)
616 {
617 case GL_FRONT:
618 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
619 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
620 break;
621 case GL_BACK:
622 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
623 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
624 break;
625 case GL_FRONT_AND_BACK:
626 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
627 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
628 break;
629 default:
630 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
631 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
632 break;
633 }
634 }
635
636 switch (ctx->Polygon.FrontFace)
637 {
638 case GL_CW:
639 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
640 break;
641 case GL_CCW:
642 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
643 break;
644 default:
645 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
646 break;
647 }
648 }
649
650 static void r700UpdateLineStipple(GLcontext * ctx)
651 {
652 context_t *context = R700_CONTEXT(ctx);
653 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
654
655 R600_STATECHANGE(context, sc);
656
657 if (ctx->Line.StippleFlag)
658 {
659 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
660 }
661 else
662 {
663 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
664 }
665 }
666
667 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
668 {
669 context_t *context = R700_CONTEXT(ctx);
670
671 switch (cap) {
672 case GL_TEXTURE_1D:
673 case GL_TEXTURE_2D:
674 case GL_TEXTURE_3D:
675 /* empty */
676 break;
677 case GL_FOG:
678 /* empty */
679 break;
680 case GL_ALPHA_TEST:
681 r700SetAlphaState(ctx);
682 break;
683 case GL_COLOR_LOGIC_OP:
684 r700SetLogicOpState(ctx);
685 /* fall-through, because logic op overrides blending */
686 case GL_BLEND:
687 r700SetBlendState(ctx);
688 break;
689 case GL_CLIP_PLANE0:
690 case GL_CLIP_PLANE1:
691 case GL_CLIP_PLANE2:
692 case GL_CLIP_PLANE3:
693 case GL_CLIP_PLANE4:
694 case GL_CLIP_PLANE5:
695 r700SetClipPlaneState(ctx, cap, state);
696 break;
697 case GL_DEPTH_TEST:
698 r700SetDepthState(ctx);
699 break;
700 case GL_STENCIL_TEST:
701 r700SetStencilState(ctx, state);
702 break;
703 case GL_CULL_FACE:
704 r700UpdateCulling(ctx);
705 break;
706 case GL_POLYGON_OFFSET_POINT:
707 case GL_POLYGON_OFFSET_LINE:
708 case GL_POLYGON_OFFSET_FILL:
709 r700SetPolygonOffsetState(ctx, state);
710 break;
711 case GL_SCISSOR_TEST:
712 radeon_firevertices(&context->radeon);
713 context->radeon.state.scissor.enabled = state;
714 radeonUpdateScissor(ctx);
715 break;
716 case GL_LINE_STIPPLE:
717 r700UpdateLineStipple(ctx);
718 break;
719 default:
720 break;
721 }
722
723 }
724
725 /**
726 * Handle glColorMask()
727 */
728 static void r700ColorMask(GLcontext * ctx,
729 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
730 {
731 context_t *context = R700_CONTEXT(ctx);
732 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
733 unsigned int mask = ((r ? 1 : 0) |
734 (g ? 2 : 0) |
735 (b ? 4 : 0) |
736 (a ? 8 : 0));
737
738 if (mask != r700->CB_TARGET_MASK.u32All) {
739 R600_STATECHANGE(context, cb);
740 SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
741 }
742 }
743
744 /**
745 * Change the depth testing function.
746 *
747 * \note Mesa already filters redundant calls to this function.
748 */
749 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
750 {
751 r700SetDepthState(ctx);
752 }
753
754 /**
755 * Enable/Disable depth writing.
756 *
757 * \note Mesa already filters redundant calls to this function.
758 */
759 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
760 {
761 r700SetDepthState(ctx);
762 }
763
764 /**
765 * Change the culling mode.
766 *
767 * \note Mesa already filters redundant calls to this function.
768 */
769 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
770 {
771 r700UpdateCulling(ctx);
772 }
773
774 /* =============================================================
775 * Fog
776 */
777 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
778 {
779 }
780
781 /**
782 * Change the polygon orientation.
783 *
784 * \note Mesa already filters redundant calls to this function.
785 */
786 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
787 {
788 r700UpdateCulling(ctx);
789 r700UpdatePolygonMode(ctx);
790 }
791
792 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
793 {
794 context_t *context = R700_CONTEXT(ctx);
795 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
796
797 R600_STATECHANGE(context, spi);
798
799 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
800 switch (mode) {
801 case GL_FLAT:
802 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
803 break;
804 case GL_SMOOTH:
805 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
806 break;
807 default:
808 return;
809 }
810 }
811
812 /* =============================================================
813 * Point state
814 */
815 static void r700PointSize(GLcontext * ctx, GLfloat size)
816 {
817 context_t *context = R700_CONTEXT(ctx);
818 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
819
820 R600_STATECHANGE(context, su);
821
822 /* We need to clamp to user defined range here, because
823 * the HW clamping happens only for per vertex point size. */
824 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
825
826 /* same size limits for AA, non-AA points */
827 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
828
829 /* format is 12.4 fixed point */
830 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
831 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
832 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
833 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
834
835 }
836
837 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
838 {
839 context_t *context = R700_CONTEXT(ctx);
840 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
841
842 R600_STATECHANGE(context, su);
843
844 /* format is 12.4 fixed point */
845 switch (pname) {
846 case GL_POINT_SIZE_MIN:
847 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
848 MIN_SIZE_shift, MIN_SIZE_mask);
849 break;
850 case GL_POINT_SIZE_MAX:
851 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
852 MAX_SIZE_shift, MAX_SIZE_mask);
853 break;
854 case GL_POINT_DISTANCE_ATTENUATION:
855 break;
856 case GL_POINT_FADE_THRESHOLD_SIZE:
857 break;
858 default:
859 break;
860 }
861 }
862
863 static int translate_stencil_func(int func)
864 {
865 switch (func) {
866 case GL_NEVER:
867 return REF_NEVER;
868 case GL_LESS:
869 return REF_LESS;
870 case GL_EQUAL:
871 return REF_EQUAL;
872 case GL_LEQUAL:
873 return REF_LEQUAL;
874 case GL_GREATER:
875 return REF_GREATER;
876 case GL_NOTEQUAL:
877 return REF_NOTEQUAL;
878 case GL_GEQUAL:
879 return REF_GEQUAL;
880 case GL_ALWAYS:
881 return REF_ALWAYS;
882 }
883 return 0;
884 }
885
886 static int translate_stencil_op(int op)
887 {
888 switch (op) {
889 case GL_KEEP:
890 return STENCIL_KEEP;
891 case GL_ZERO:
892 return STENCIL_ZERO;
893 case GL_REPLACE:
894 return STENCIL_REPLACE;
895 case GL_INCR:
896 return STENCIL_INCR_CLAMP;
897 case GL_DECR:
898 return STENCIL_DECR_CLAMP;
899 case GL_INCR_WRAP_EXT:
900 return STENCIL_INCR_WRAP;
901 case GL_DECR_WRAP_EXT:
902 return STENCIL_DECR_WRAP;
903 case GL_INVERT:
904 return STENCIL_INVERT;
905 default:
906 WARN_ONCE("Do not know how to translate stencil op");
907 return STENCIL_KEEP;
908 }
909 return 0;
910 }
911
912 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
913 {
914 context_t *context = R700_CONTEXT(ctx);
915 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
916 GLboolean hw_stencil = GL_FALSE;
917
918 if (ctx->DrawBuffer) {
919 struct radeon_renderbuffer *rrbStencil
920 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
921 hw_stencil = (rrbStencil && rrbStencil->bo);
922 }
923
924 if (hw_stencil) {
925 R600_STATECHANGE(context, db);
926 if (state) {
927 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
928 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
929 } else
930 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
931 }
932 }
933
934 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
935 GLenum func, GLint ref, GLuint mask) //---------------------
936 {
937 context_t *context = R700_CONTEXT(ctx);
938 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
939 const unsigned back = ctx->Stencil._BackFace;
940
941 R600_STATECHANGE(context, stencil);
942 R600_STATECHANGE(context, db);
943
944 //front
945 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
946 STENCILREF_shift, STENCILREF_mask);
947 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
948 STENCILMASK_shift, STENCILMASK_mask);
949
950 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
951 STENCILFUNC_shift, STENCILFUNC_mask);
952
953 //back
954 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
955 STENCILREF_BF_shift, STENCILREF_BF_mask);
956 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
957 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
958
959 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
960 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
961
962 }
963
964 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
965 {
966 context_t *context = R700_CONTEXT(ctx);
967 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
968 const unsigned back = ctx->Stencil._BackFace;
969
970 R600_STATECHANGE(context, stencil);
971
972 // front
973 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
974 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
975
976 // back
977 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
978 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
979
980 }
981
982 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
983 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
984 {
985 context_t *context = R700_CONTEXT(ctx);
986 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
987 const unsigned back = ctx->Stencil._BackFace;
988
989 R600_STATECHANGE(context, db);
990
991 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
992 STENCILFAIL_shift, STENCILFAIL_mask);
993 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
994 STENCILZFAIL_shift, STENCILZFAIL_mask);
995 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
996 STENCILZPASS_shift, STENCILZPASS_mask);
997
998 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
999 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1000 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1001 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1002 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1003 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1004 }
1005
1006 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1007 {
1008 context_t *context = R700_CONTEXT(ctx);
1009 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1010 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1011 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1012 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1013 const GLfloat *v = ctx->Viewport._WindowMap.m;
1014 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1015 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1016 GLfloat y_scale, y_bias;
1017
1018 if (render_to_fbo) {
1019 y_scale = 1.0;
1020 y_bias = 0;
1021 } else {
1022 y_scale = -1.0;
1023 y_bias = yoffset;
1024 }
1025
1026 GLfloat sx = v[MAT_SX];
1027 GLfloat tx = v[MAT_TX] + xoffset;
1028 GLfloat sy = v[MAT_SY] * y_scale;
1029 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1030 GLfloat sz = v[MAT_SZ] * depthScale;
1031 GLfloat tz = v[MAT_TZ] * depthScale;
1032
1033 R600_STATECHANGE(context, vpt);
1034
1035 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1036 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1037
1038 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1039 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1040
1041 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1042 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1043
1044 r700->viewport[id].enabled = GL_TRUE;
1045
1046 r700SetScissor(context);
1047 }
1048
1049
1050 static void r700Viewport(GLcontext * ctx,
1051 GLint x,
1052 GLint y,
1053 GLsizei width,
1054 GLsizei height) //--------------------
1055 {
1056 r700UpdateWindow(ctx, 0);
1057
1058 radeon_viewport(ctx, x, y, width, height);
1059 }
1060
1061 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1062 {
1063 r700UpdateWindow(ctx, 0);
1064 }
1065
1066 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1067 {
1068 context_t *context = R700_CONTEXT(ctx);
1069 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1070 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1071
1072 R600_STATECHANGE(context, su);
1073
1074 if (lineWidth > 0xFFFF)
1075 lineWidth = 0xFFFF;
1076 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1077 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1078 }
1079
1080 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1081 {
1082 context_t *context = R700_CONTEXT(ctx);
1083 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1084
1085 R600_STATECHANGE(context, sc);
1086
1087 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1088 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1089 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1090 }
1091
1092 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1093 {
1094 context_t *context = R700_CONTEXT(ctx);
1095 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1096
1097 R600_STATECHANGE(context, su);
1098
1099 if (state) {
1100 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1101 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1102 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1103 } else {
1104 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1105 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1106 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1107 }
1108 }
1109
1110 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1111 {
1112 context_t *context = R700_CONTEXT(ctx);
1113 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1114 GLfloat constant = units;
1115 GLchar depth = 0;
1116
1117 R600_STATECHANGE(context, poly);
1118
1119 switch (ctx->Visual.depthBits) {
1120 case 16:
1121 constant *= 4.0;
1122 depth = -16;
1123 break;
1124 case 24:
1125 constant *= 2.0;
1126 depth = -24;
1127 break;
1128 }
1129
1130 factor *= 12.0;
1131 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1132 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1133 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1134 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1135 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1136 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1137 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1138 }
1139
1140 static void r700UpdatePolygonMode(GLcontext * ctx)
1141 {
1142 context_t *context = R700_CONTEXT(ctx);
1143 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1144
1145 R600_STATECHANGE(context, su);
1146
1147 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1148
1149 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1150 if (ctx->Polygon.FrontMode != GL_FILL ||
1151 ctx->Polygon.BackMode != GL_FILL) {
1152 GLenum f, b;
1153
1154 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1155 * correctly by selecting the correct front and back face
1156 */
1157 if (ctx->Polygon.FrontFace == GL_CCW) {
1158 f = ctx->Polygon.FrontMode;
1159 b = ctx->Polygon.BackMode;
1160 } else {
1161 f = ctx->Polygon.BackMode;
1162 b = ctx->Polygon.FrontMode;
1163 }
1164
1165 /* Enable polygon mode */
1166 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1167
1168 switch (f) {
1169 case GL_LINE:
1170 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1171 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1172 break;
1173 case GL_POINT:
1174 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1175 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1176 break;
1177 case GL_FILL:
1178 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1179 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1180 break;
1181 }
1182
1183 switch (b) {
1184 case GL_LINE:
1185 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1186 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1187 break;
1188 case GL_POINT:
1189 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1190 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1191 break;
1192 case GL_FILL:
1193 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1194 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1195 break;
1196 }
1197 }
1198 }
1199
1200 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1201 {
1202 (void)face;
1203 (void)mode;
1204
1205 r700UpdatePolygonMode(ctx);
1206 }
1207
1208 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1209 {
1210 }
1211
1212 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1213 {
1214 context_t *context = R700_CONTEXT(ctx);
1215 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1216 GLint p;
1217 GLint *ip;
1218
1219 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1220 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1221
1222 R600_STATECHANGE(context, ucp);
1223
1224 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1225 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1226 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1227 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1228 }
1229
1230 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1231 {
1232 context_t *context = R700_CONTEXT(ctx);
1233 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1234 GLuint p;
1235
1236 p = cap - GL_CLIP_PLANE0;
1237
1238 R600_STATECHANGE(context, cl);
1239
1240 if (state) {
1241 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1242 r700->ucp[p].enabled = GL_TRUE;
1243 r700ClipPlane(ctx, cap, NULL);
1244 } else {
1245 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1246 r700->ucp[p].enabled = GL_FALSE;
1247 }
1248 }
1249
1250 void r700SetScissor(context_t *context) //---------------
1251 {
1252 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1253 unsigned x1, y1, x2, y2;
1254 int id = 0;
1255 struct radeon_renderbuffer *rrb;
1256
1257 rrb = radeon_get_colorbuffer(&context->radeon);
1258 if (!rrb || !rrb->bo) {
1259 return;
1260 }
1261 if (context->radeon.state.scissor.enabled) {
1262 x1 = context->radeon.state.scissor.rect.x1;
1263 y1 = context->radeon.state.scissor.rect.y1;
1264 x2 = context->radeon.state.scissor.rect.x2;
1265 y2 = context->radeon.state.scissor.rect.y2;
1266 /* r600 has exclusive BR scissors */
1267 if (context->radeon.radeonScreen->kernel_mm) {
1268 x2++;
1269 y2++;
1270 }
1271 } else {
1272 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1273 x1 = 0;
1274 y1 = 0;
1275 x2 = rrb->base.Width;
1276 y2 = rrb->base.Height;
1277 } else {
1278 x1 = rrb->dPriv->x;
1279 y1 = rrb->dPriv->y;
1280 x2 = rrb->dPriv->x + rrb->dPriv->w;
1281 y2 = rrb->dPriv->y + rrb->dPriv->h;
1282 }
1283 }
1284
1285 R600_STATECHANGE(context, scissor);
1286
1287 /* screen */
1288 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1289 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1290 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1291 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1292 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1293
1294 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1295 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1296 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1297 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1298
1299 /* window */
1300 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1301 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1302 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1303 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1304 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1305
1306 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1307 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1308 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1309 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1310
1311
1312 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1313 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1314 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1315 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1316 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1317 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1318 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1319 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1320
1321 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1322 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1323 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1324 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1325 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1326 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1327
1328 /* more....2d clip */
1329 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1330 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1331 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1332 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1333 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1334 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1335 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1336 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1337 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1338
1339 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1340 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1341 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1342 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1343 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1344 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1345 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1346 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1347 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1348
1349 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1350 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1351 r700->viewport[id].enabled = GL_TRUE;
1352 }
1353
1354 static void r700InitSQConfig(GLcontext * ctx)
1355 {
1356 context_t *context = R700_CONTEXT(ctx);
1357 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1358 int ps_prio;
1359 int vs_prio;
1360 int gs_prio;
1361 int es_prio;
1362 int num_ps_gprs;
1363 int num_vs_gprs;
1364 int num_gs_gprs;
1365 int num_es_gprs;
1366 int num_temp_gprs;
1367 int num_ps_threads;
1368 int num_vs_threads;
1369 int num_gs_threads;
1370 int num_es_threads;
1371 int num_ps_stack_entries;
1372 int num_vs_stack_entries;
1373 int num_gs_stack_entries;
1374 int num_es_stack_entries;
1375
1376 R600_STATECHANGE(context, sq);
1377
1378 // SQ
1379 ps_prio = 0;
1380 vs_prio = 1;
1381 gs_prio = 2;
1382 es_prio = 3;
1383 switch (context->radeon.radeonScreen->chip_family) {
1384 case CHIP_FAMILY_R600:
1385 num_ps_gprs = 192;
1386 num_vs_gprs = 56;
1387 num_temp_gprs = 4;
1388 num_gs_gprs = 0;
1389 num_es_gprs = 0;
1390 num_ps_threads = 136;
1391 num_vs_threads = 48;
1392 num_gs_threads = 4;
1393 num_es_threads = 4;
1394 num_ps_stack_entries = 128;
1395 num_vs_stack_entries = 128;
1396 num_gs_stack_entries = 0;
1397 num_es_stack_entries = 0;
1398 break;
1399 case CHIP_FAMILY_RV630:
1400 case CHIP_FAMILY_RV635:
1401 num_ps_gprs = 84;
1402 num_vs_gprs = 36;
1403 num_temp_gprs = 4;
1404 num_gs_gprs = 0;
1405 num_es_gprs = 0;
1406 num_ps_threads = 144;
1407 num_vs_threads = 40;
1408 num_gs_threads = 4;
1409 num_es_threads = 4;
1410 num_ps_stack_entries = 40;
1411 num_vs_stack_entries = 40;
1412 num_gs_stack_entries = 32;
1413 num_es_stack_entries = 16;
1414 break;
1415 case CHIP_FAMILY_RV610:
1416 case CHIP_FAMILY_RV620:
1417 case CHIP_FAMILY_RS780:
1418 case CHIP_FAMILY_RS880:
1419 default:
1420 num_ps_gprs = 84;
1421 num_vs_gprs = 36;
1422 num_temp_gprs = 4;
1423 num_gs_gprs = 0;
1424 num_es_gprs = 0;
1425 num_ps_threads = 136;
1426 num_vs_threads = 48;
1427 num_gs_threads = 4;
1428 num_es_threads = 4;
1429 num_ps_stack_entries = 40;
1430 num_vs_stack_entries = 40;
1431 num_gs_stack_entries = 32;
1432 num_es_stack_entries = 16;
1433 break;
1434 case CHIP_FAMILY_RV670:
1435 num_ps_gprs = 144;
1436 num_vs_gprs = 40;
1437 num_temp_gprs = 4;
1438 num_gs_gprs = 0;
1439 num_es_gprs = 0;
1440 num_ps_threads = 136;
1441 num_vs_threads = 48;
1442 num_gs_threads = 4;
1443 num_es_threads = 4;
1444 num_ps_stack_entries = 40;
1445 num_vs_stack_entries = 40;
1446 num_gs_stack_entries = 32;
1447 num_es_stack_entries = 16;
1448 break;
1449 case CHIP_FAMILY_RV770:
1450 num_ps_gprs = 192;
1451 num_vs_gprs = 56;
1452 num_temp_gprs = 4;
1453 num_gs_gprs = 0;
1454 num_es_gprs = 0;
1455 num_ps_threads = 188;
1456 num_vs_threads = 60;
1457 num_gs_threads = 0;
1458 num_es_threads = 0;
1459 num_ps_stack_entries = 256;
1460 num_vs_stack_entries = 256;
1461 num_gs_stack_entries = 0;
1462 num_es_stack_entries = 0;
1463 break;
1464 case CHIP_FAMILY_RV730:
1465 case CHIP_FAMILY_RV740:
1466 num_ps_gprs = 84;
1467 num_vs_gprs = 36;
1468 num_temp_gprs = 4;
1469 num_gs_gprs = 0;
1470 num_es_gprs = 0;
1471 num_ps_threads = 188;
1472 num_vs_threads = 60;
1473 num_gs_threads = 0;
1474 num_es_threads = 0;
1475 num_ps_stack_entries = 128;
1476 num_vs_stack_entries = 128;
1477 num_gs_stack_entries = 0;
1478 num_es_stack_entries = 0;
1479 break;
1480 case CHIP_FAMILY_RV710:
1481 num_ps_gprs = 192;
1482 num_vs_gprs = 56;
1483 num_temp_gprs = 4;
1484 num_gs_gprs = 0;
1485 num_es_gprs = 0;
1486 num_ps_threads = 144;
1487 num_vs_threads = 48;
1488 num_gs_threads = 0;
1489 num_es_threads = 0;
1490 num_ps_stack_entries = 128;
1491 num_vs_stack_entries = 128;
1492 num_gs_stack_entries = 0;
1493 num_es_stack_entries = 0;
1494 break;
1495 }
1496
1497 r700->sq_config.SQ_CONFIG.u32All = 0;
1498 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1499 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1500 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1501 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1502 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1503 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1504 else
1505 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1506 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1507 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1508 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1509 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1510 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1511 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1512
1513 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1514 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1515 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1516 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1517 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1518
1519 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1520 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1521 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1522
1523 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1524 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1525 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1526 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1527 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1528 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1529 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1530 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1531 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1532
1533 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1534 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1535 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1536 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1537 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1538
1539 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1540 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1541 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1542 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1543 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1544
1545 }
1546
1547 /**
1548 * Calculate initial hardware state and register state functions.
1549 * Assumes that the command buffer and state atoms have been
1550 * initialized already.
1551 */
1552 void r700InitState(GLcontext * ctx) //-------------------
1553 {
1554 context_t *context = R700_CONTEXT(ctx);
1555 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1556 int id = 0;
1557
1558 radeon_firevertices(&context->radeon);
1559
1560 r700->TA_CNTL_AUX.u32All = 0;
1561 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1562 r700->VC_ENHANCE.u32All = 0;
1563 r700->DB_WATERMARKS.u32All = 0;
1564 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1565 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1566 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1567 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1568 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1569 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1570 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1571 r700->DB_DEBUG.u32All = 0x82000000;
1572 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1573 } else {
1574 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1575 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1576 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1577 }
1578
1579 /* Turn off vgt reuse */
1580 r700->VGT_REUSE_OFF.u32All = 0;
1581 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1582
1583 /* Specify offsetting and clamp values for vertices */
1584 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1585 r700->VGT_MIN_VTX_INDX.u32All = 0;
1586 r700->VGT_INDX_OFFSET.u32All = 0;
1587
1588 /* default shader connections. */
1589 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1590 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1591 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1592 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1593
1594 r700->SPI_THREAD_GROUPING.u32All = 0;
1595 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1596 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1597
1598 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1599 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1600 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1601
1602 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1603 r700->PA_SC_EDGERULE.u32All = 0;
1604 else
1605 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1606
1607 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1608 r700->PA_SC_MODE_CNTL.u32All = 0;
1609 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1610 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1611 } else {
1612 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1613 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1614 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1615 }
1616
1617 /* Do scale XY and Z by 1/W0. */
1618 r700->bEnablePerspective = GL_TRUE;
1619 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1620 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1621 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1622
1623 /* Enable viewport scaling for all three axis */
1624 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1625 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1626 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1627 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1628 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1629 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1630
1631 /* GL uses last vtx for flat shading components */
1632 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1633
1634 /* Set up vertex control */
1635 r700->PA_SU_VTX_CNTL.u32All = 0;
1636 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1637 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1638 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1639 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1640
1641 /* to 1.0 = no guard band */
1642 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1643 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1644 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1645 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1646
1647 /* Enable all samples for multi-sample anti-aliasing */
1648 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1649 /* Turn off AA */
1650 r700->PA_SC_AA_CONFIG.u32All = 0;
1651
1652 r700->SX_MISC.u32All = 0;
1653
1654 r700InitSQConfig(ctx);
1655
1656 r700ColorMask(ctx,
1657 ctx->Color.ColorMask[RCOMP],
1658 ctx->Color.ColorMask[GCOMP],
1659 ctx->Color.ColorMask[BCOMP],
1660 ctx->Color.ColorMask[ACOMP]);
1661
1662 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1663 r700DepthMask(ctx, ctx->Depth.Mask);
1664 r700DepthFunc(ctx, ctx->Depth.Func);
1665 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1666
1667 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1668
1669 r700->DB_RENDER_CONTROL.u32All = 0;
1670 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1671 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1672 r700->DB_RENDER_OVERRIDE.u32All = 0;
1673 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1674 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1675 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1676 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1677 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1678
1679 r700->DB_ALPHA_TO_MASK.u32All = 0;
1680 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1681 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1682 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1683 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1684
1685 /* stencil */
1686 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1687 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1688 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1689 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1690 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1691 ctx->Stencil.ZFailFunc[0],
1692 ctx->Stencil.ZPassFunc[0]);
1693
1694 r700UpdateCulling(ctx);
1695
1696 r700SetBlendState(ctx);
1697 r700SetLogicOpState(ctx);
1698
1699 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1700 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1701
1702 r700PointSize(ctx, 1.0);
1703
1704 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1705 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1706
1707 r700LineWidth(ctx, 1.0);
1708
1709 r700->PA_SC_LINE_CNTL.u32All = 0;
1710 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1711 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1712
1713 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1714 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1715 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1716 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1717 ctx->Polygon.OffsetUnits);
1718 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1719 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1720 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1721
1722 /* CB */
1723 r700BlendColor(ctx, ctx->Color.BlendColor);
1724
1725 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1726 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1727 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1728 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1729 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1730 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1731 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1732
1733 /* Disable color compares */
1734 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1735 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1736 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1737 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1738 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1739 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1740
1741 /* Zero out source */
1742 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1743
1744 /* Put a compare color in for error checking */
1745 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1746
1747 /* Set up color compare mask */
1748 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1749
1750 /* screen/window/view */
1751 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask);
1752
1753 context->radeon.hw.all_dirty = GL_TRUE;
1754
1755 }
1756
1757 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1758 {
1759 functions->UpdateState = r700InvalidateState;
1760 functions->AlphaFunc = r700AlphaFunc;
1761 functions->BlendColor = r700BlendColor;
1762 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1763 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1764 functions->Enable = r700Enable;
1765 functions->ColorMask = r700ColorMask;
1766 functions->DepthFunc = r700DepthFunc;
1767 functions->DepthMask = r700DepthMask;
1768 functions->CullFace = r700CullFace;
1769 functions->Fogfv = r700Fogfv;
1770 functions->FrontFace = r700FrontFace;
1771 functions->ShadeModel = r700ShadeModel;
1772 functions->LogicOpcode = r700LogicOpcode;
1773
1774 /* ARB_point_parameters */
1775 functions->PointParameterfv = r700PointParameter;
1776
1777 /* Stencil related */
1778 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1779 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1780 functions->StencilOpSeparate = r700StencilOpSeparate;
1781
1782 /* Viewport related */
1783 functions->Viewport = r700Viewport;
1784 functions->DepthRange = r700DepthRange;
1785 functions->PointSize = r700PointSize;
1786 functions->LineWidth = r700LineWidth;
1787 functions->LineStipple = r700LineStipple;
1788
1789 functions->PolygonOffset = r700PolygonOffset;
1790 functions->PolygonMode = r700PolygonMode;
1791
1792 functions->RenderMode = r700RenderMode;
1793
1794 functions->ClipPlane = r700ClipPlane;
1795
1796 functions->Scissor = radeonScissor;
1797
1798 functions->DrawBuffer = radeonDrawBuffer;
1799 functions->ReadBuffer = radeonReadBuffer;
1800
1801 }
1802