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r600: user correct alpha blend factor
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63
64 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
65 {
66 context_t *context = R700_CONTEXT(ctx);
67 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
68 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
69 int i;
70
71 /* should only happenen once, just after context is created */
72 /* TODO: shouldn't we fallback to sw here? */
73 if (!ctx->FragmentProgram._Current) {
74 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
75 return;
76 }
77
78 r700SelectFragmentShader(ctx);
79
80 if (context->radeon.NewGLState) {
81 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
82 /* mat states from state var not array for sw */
83 dummy_attrib[i].stride = 0;
84 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
85 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
86 }
87
88 _tnl_UpdateFixedFunctionProgram(ctx);
89
90 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
91 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
92 }
93 }
94
95 r700SelectVertexShader(ctx);
96 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
97 context->radeon.NewGLState = 0;
98 }
99
100 /*
101 * To correctly position primitives:
102 */
103 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
104 {
105 context_t *context = R700_CONTEXT(ctx);
106 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
107 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
108 GLfloat xoffset = (GLfloat) dPriv->x;
109 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
110 const GLfloat *v = ctx->Viewport._WindowMap.m;
111 int id = 0;
112
113 GLfloat tx = v[MAT_TX] + xoffset;
114 GLfloat ty = (-v[MAT_TY]) + yoffset;
115
116 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
117 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
118 /* Note: this should also modify whatever data the context reset
119 * code uses...
120 */
121 R600_STATECHANGE(context, vpt);
122 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
123 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
124 }
125
126 radeonUpdateScissor(ctx);
127 }
128
129 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
130 {
131 struct r700_fragment_program *fp =
132 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
133 struct gl_program_parameter_list *paramList;
134
135 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
136 return;
137
138 if (!ctx->FragmentProgram._Current || !fp)
139 return;
140
141 paramList = ctx->FragmentProgram._Current->Base.Parameters;
142
143 if (!paramList)
144 return;
145
146 _mesa_load_state_parameters(ctx, paramList);
147
148 }
149
150 /**
151 * Called by Mesa after an internal state update.
152 */
153 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
154 {
155 context_t *context = R700_CONTEXT(ctx);
156
157 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
158
159 _swrast_InvalidateState(ctx, new_state);
160 _swsetup_InvalidateState(ctx, new_state);
161 _vbo_InvalidateState(ctx, new_state);
162 _tnl_InvalidateState(ctx, new_state);
163 _ae_invalidate_state(ctx, new_state);
164
165 if (new_state & _NEW_BUFFERS) {
166 _mesa_update_framebuffer(ctx);
167 /* this updates the DrawBuffer's Width/Height if it's a FBO */
168 _mesa_update_draw_buffer_bounds(ctx);
169
170 R600_STATECHANGE(context, cb_target);
171 R600_STATECHANGE(context, db_target);
172 }
173
174 r700UpdateStateParameters(ctx, new_state);
175
176 R600_STATECHANGE(context, cl);
177 R600_STATECHANGE(context, spi);
178
179 if(GL_TRUE == r700->bEnablePerspective)
180 {
181 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
182 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
183 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
184
185 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
186
187 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
188 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
189 }
190 else
191 {
192 /* For orthogonal case. */
193 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
194 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
195
196 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
197
198 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
199 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
200 }
201
202 context->radeon.NewGLState |= new_state;
203 }
204
205 static void r700SetDepthState(GLcontext * ctx)
206 {
207 context_t *context = R700_CONTEXT(ctx);
208 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
209
210 R600_STATECHANGE(context, db);
211
212 if (ctx->Depth.Test)
213 {
214 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
215 if (ctx->Depth.Mask)
216 {
217 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
218 }
219 else
220 {
221 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
222 }
223
224 switch (ctx->Depth.Func)
225 {
226 case GL_NEVER:
227 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
228 ZFUNC_shift, ZFUNC_mask);
229 break;
230 case GL_LESS:
231 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
232 ZFUNC_shift, ZFUNC_mask);
233 break;
234 case GL_EQUAL:
235 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
236 ZFUNC_shift, ZFUNC_mask);
237 break;
238 case GL_LEQUAL:
239 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
240 ZFUNC_shift, ZFUNC_mask);
241 break;
242 case GL_GREATER:
243 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
244 ZFUNC_shift, ZFUNC_mask);
245 break;
246 case GL_NOTEQUAL:
247 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
248 ZFUNC_shift, ZFUNC_mask);
249 break;
250 case GL_GEQUAL:
251 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
252 ZFUNC_shift, ZFUNC_mask);
253 break;
254 case GL_ALWAYS:
255 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
256 ZFUNC_shift, ZFUNC_mask);
257 break;
258 default:
259 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
260 ZFUNC_shift, ZFUNC_mask);
261 break;
262 }
263 }
264 else
265 {
266 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
267 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
268 }
269 }
270
271 static void r700SetAlphaState(GLcontext * ctx)
272 {
273 context_t *context = R700_CONTEXT(ctx);
274 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
275 uint32_t alpha_func = REF_ALWAYS;
276 GLboolean really_enabled = ctx->Color.AlphaEnabled;
277
278 R600_STATECHANGE(context, sx);
279
280 switch (ctx->Color.AlphaFunc) {
281 case GL_NEVER:
282 alpha_func = REF_NEVER;
283 break;
284 case GL_LESS:
285 alpha_func = REF_LESS;
286 break;
287 case GL_EQUAL:
288 alpha_func = REF_EQUAL;
289 break;
290 case GL_LEQUAL:
291 alpha_func = REF_LEQUAL;
292 break;
293 case GL_GREATER:
294 alpha_func = REF_GREATER;
295 break;
296 case GL_NOTEQUAL:
297 alpha_func = REF_NOTEQUAL;
298 break;
299 case GL_GEQUAL:
300 alpha_func = REF_GEQUAL;
301 break;
302 case GL_ALWAYS:
303 /*alpha_func = REF_ALWAYS; */
304 really_enabled = GL_FALSE;
305 break;
306 }
307
308 if (really_enabled) {
309 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
310 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
311 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
312 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
313 } else {
314 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
315 }
316
317 }
318
319 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
320 {
321 (void)func;
322 (void)ref;
323 r700SetAlphaState(ctx);
324 }
325
326
327 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
328 {
329 context_t *context = R700_CONTEXT(ctx);
330 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
331
332 R600_STATECHANGE(context, blnd_clr);
333
334 r700->CB_BLEND_RED.f32All = cf[0];
335 r700->CB_BLEND_GREEN.f32All = cf[1];
336 r700->CB_BLEND_BLUE.f32All = cf[2];
337 r700->CB_BLEND_ALPHA.f32All = cf[3];
338 }
339
340 static int blend_factor(GLenum factor, GLboolean is_src)
341 {
342 switch (factor) {
343 case GL_ZERO:
344 return BLEND_ZERO;
345 break;
346 case GL_ONE:
347 return BLEND_ONE;
348 break;
349 case GL_DST_COLOR:
350 return BLEND_DST_COLOR;
351 break;
352 case GL_ONE_MINUS_DST_COLOR:
353 return BLEND_ONE_MINUS_DST_COLOR;
354 break;
355 case GL_SRC_COLOR:
356 return BLEND_SRC_COLOR;
357 break;
358 case GL_ONE_MINUS_SRC_COLOR:
359 return BLEND_ONE_MINUS_SRC_COLOR;
360 break;
361 case GL_SRC_ALPHA:
362 return BLEND_SRC_ALPHA;
363 break;
364 case GL_ONE_MINUS_SRC_ALPHA:
365 return BLEND_ONE_MINUS_SRC_ALPHA;
366 break;
367 case GL_DST_ALPHA:
368 return BLEND_DST_ALPHA;
369 break;
370 case GL_ONE_MINUS_DST_ALPHA:
371 return BLEND_ONE_MINUS_DST_ALPHA;
372 break;
373 case GL_SRC_ALPHA_SATURATE:
374 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
375 break;
376 case GL_CONSTANT_COLOR:
377 return BLEND_CONSTANT_COLOR;
378 break;
379 case GL_ONE_MINUS_CONSTANT_COLOR:
380 return BLEND_ONE_MINUS_CONSTANT_COLOR;
381 break;
382 case GL_CONSTANT_ALPHA:
383 return BLEND_CONSTANT_ALPHA;
384 break;
385 case GL_ONE_MINUS_CONSTANT_ALPHA:
386 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
387 break;
388 default:
389 fprintf(stderr, "unknown blend factor %x\n", factor);
390 return (is_src) ? BLEND_ONE : BLEND_ZERO;
391 break;
392 }
393 }
394
395 static void r700SetBlendState(GLcontext * ctx)
396 {
397 context_t *context = R700_CONTEXT(ctx);
398 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
399 int id = 0;
400 uint32_t blend_reg = 0, eqn, eqnA;
401
402 R600_STATECHANGE(context, blnd);
403
404 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
405 SETfield(blend_reg,
406 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
407 SETfield(blend_reg,
408 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
409 SETfield(blend_reg,
410 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
411 SETfield(blend_reg,
412 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
413 SETfield(blend_reg,
414 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
415 SETfield(blend_reg,
416 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
417 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
418 r700->CB_BLEND_CONTROL.u32All = blend_reg;
419 else
420 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
421 return;
422 }
423
424 SETfield(blend_reg,
425 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
426 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
427 SETfield(blend_reg,
428 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
429 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
430
431 switch (ctx->Color.BlendEquationRGB) {
432 case GL_FUNC_ADD:
433 eqn = COMB_DST_PLUS_SRC;
434 break;
435 case GL_FUNC_SUBTRACT:
436 eqn = COMB_SRC_MINUS_DST;
437 break;
438 case GL_FUNC_REVERSE_SUBTRACT:
439 eqn = COMB_DST_MINUS_SRC;
440 break;
441 case GL_MIN:
442 eqn = COMB_MIN_DST_SRC;
443 SETfield(blend_reg,
444 BLEND_ONE,
445 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
446 SETfield(blend_reg,
447 BLEND_ONE,
448 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
449 break;
450 case GL_MAX:
451 eqn = COMB_MAX_DST_SRC;
452 SETfield(blend_reg,
453 BLEND_ONE,
454 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
455 SETfield(blend_reg,
456 BLEND_ONE,
457 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
458 break;
459
460 default:
461 fprintf(stderr,
462 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
463 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
464 return;
465 }
466 SETfield(blend_reg,
467 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
468
469 SETfield(blend_reg,
470 blend_factor(ctx->Color.BlendSrcA, GL_TRUE),
471 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
472 SETfield(blend_reg,
473 blend_factor(ctx->Color.BlendDstA, GL_FALSE),
474 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
475
476 switch (ctx->Color.BlendEquationA) {
477 case GL_FUNC_ADD:
478 eqnA = COMB_DST_PLUS_SRC;
479 break;
480 case GL_FUNC_SUBTRACT:
481 eqnA = COMB_SRC_MINUS_DST;
482 break;
483 case GL_FUNC_REVERSE_SUBTRACT:
484 eqnA = COMB_DST_MINUS_SRC;
485 break;
486 case GL_MIN:
487 eqnA = COMB_MIN_DST_SRC;
488 SETfield(blend_reg,
489 BLEND_ONE,
490 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
491 SETfield(blend_reg,
492 BLEND_ONE,
493 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
494 break;
495 case GL_MAX:
496 eqnA = COMB_MAX_DST_SRC;
497 SETfield(blend_reg,
498 BLEND_ONE,
499 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
500 SETfield(blend_reg,
501 BLEND_ONE,
502 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
503 break;
504 default:
505 fprintf(stderr,
506 "[%s:%u] Invalid A blend equation (0x%04x).\n",
507 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
508 return;
509 }
510
511 SETfield(blend_reg,
512 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
513
514 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
515
516 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
517 r700->CB_BLEND_CONTROL.u32All = blend_reg;
518 else {
519 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
520 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
521 }
522 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
523 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
524
525 }
526
527 static void r700BlendEquationSeparate(GLcontext * ctx,
528 GLenum modeRGB, GLenum modeA) //-----------------
529 {
530 r700SetBlendState(ctx);
531 }
532
533 static void r700BlendFuncSeparate(GLcontext * ctx,
534 GLenum sfactorRGB, GLenum dfactorRGB,
535 GLenum sfactorA, GLenum dfactorA) //------------------------
536 {
537 r700SetBlendState(ctx);
538 }
539
540 /**
541 * Translate LogicOp enums into hardware representation.
542 */
543 static GLuint translate_logicop(GLenum logicop)
544 {
545 switch (logicop) {
546 case GL_CLEAR:
547 return 0x00;
548 case GL_SET:
549 return 0xff;
550 case GL_COPY:
551 return 0xcc;
552 case GL_COPY_INVERTED:
553 return 0x33;
554 case GL_NOOP:
555 return 0xaa;
556 case GL_INVERT:
557 return 0x55;
558 case GL_AND:
559 return 0x88;
560 case GL_NAND:
561 return 0x77;
562 case GL_OR:
563 return 0xee;
564 case GL_NOR:
565 return 0x11;
566 case GL_XOR:
567 return 0x66;
568 case GL_EQUIV:
569 return 0xaa;
570 case GL_AND_REVERSE:
571 return 0x44;
572 case GL_AND_INVERTED:
573 return 0x22;
574 case GL_OR_REVERSE:
575 return 0xdd;
576 case GL_OR_INVERTED:
577 return 0xbb;
578 default:
579 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
580 return 0xcc;
581 }
582 }
583
584 /**
585 * Used internally to update the r300->hw hardware state to match the
586 * current OpenGL state.
587 */
588 static void r700SetLogicOpState(GLcontext *ctx)
589 {
590 context_t *context = R700_CONTEXT(ctx);
591 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
592
593 R600_STATECHANGE(context, blnd);
594
595 if (RGBA_LOGICOP_ENABLED(ctx))
596 SETfield(r700->CB_COLOR_CONTROL.u32All,
597 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
598 else
599 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
600 }
601
602 /**
603 * Called by Mesa when an application program changes the LogicOp state
604 * via glLogicOp.
605 */
606 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
607 {
608 if (RGBA_LOGICOP_ENABLED(ctx))
609 r700SetLogicOpState(ctx);
610 }
611
612 static void r700UpdateCulling(GLcontext * ctx)
613 {
614 context_t *context = R700_CONTEXT(ctx);
615 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
616
617 R600_STATECHANGE(context, su);
618
619 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
620 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
621 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
622
623 if (ctx->Polygon.CullFlag)
624 {
625 switch (ctx->Polygon.CullFaceMode)
626 {
627 case GL_FRONT:
628 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
629 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
630 break;
631 case GL_BACK:
632 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
633 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
634 break;
635 case GL_FRONT_AND_BACK:
636 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
637 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
638 break;
639 default:
640 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
641 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
642 break;
643 }
644 }
645
646 switch (ctx->Polygon.FrontFace)
647 {
648 case GL_CW:
649 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
650 break;
651 case GL_CCW:
652 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
653 break;
654 default:
655 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
656 break;
657 }
658 }
659
660 static void r700UpdateLineStipple(GLcontext * ctx)
661 {
662 context_t *context = R700_CONTEXT(ctx);
663 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
664
665 R600_STATECHANGE(context, sc);
666
667 if (ctx->Line.StippleFlag)
668 {
669 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
670 }
671 else
672 {
673 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
674 }
675 }
676
677 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
678 {
679 context_t *context = R700_CONTEXT(ctx);
680
681 switch (cap) {
682 case GL_TEXTURE_1D:
683 case GL_TEXTURE_2D:
684 case GL_TEXTURE_3D:
685 /* empty */
686 break;
687 case GL_FOG:
688 /* empty */
689 break;
690 case GL_ALPHA_TEST:
691 r700SetAlphaState(ctx);
692 break;
693 case GL_COLOR_LOGIC_OP:
694 r700SetLogicOpState(ctx);
695 /* fall-through, because logic op overrides blending */
696 case GL_BLEND:
697 r700SetBlendState(ctx);
698 break;
699 case GL_CLIP_PLANE0:
700 case GL_CLIP_PLANE1:
701 case GL_CLIP_PLANE2:
702 case GL_CLIP_PLANE3:
703 case GL_CLIP_PLANE4:
704 case GL_CLIP_PLANE5:
705 r700SetClipPlaneState(ctx, cap, state);
706 break;
707 case GL_DEPTH_TEST:
708 r700SetDepthState(ctx);
709 break;
710 case GL_STENCIL_TEST:
711 r700SetStencilState(ctx, state);
712 break;
713 case GL_CULL_FACE:
714 r700UpdateCulling(ctx);
715 break;
716 case GL_POLYGON_OFFSET_POINT:
717 case GL_POLYGON_OFFSET_LINE:
718 case GL_POLYGON_OFFSET_FILL:
719 r700SetPolygonOffsetState(ctx, state);
720 break;
721 case GL_SCISSOR_TEST:
722 radeon_firevertices(&context->radeon);
723 context->radeon.state.scissor.enabled = state;
724 radeonUpdateScissor(ctx);
725 break;
726 case GL_LINE_STIPPLE:
727 r700UpdateLineStipple(ctx);
728 break;
729 default:
730 break;
731 }
732
733 }
734
735 /**
736 * Handle glColorMask()
737 */
738 static void r700ColorMask(GLcontext * ctx,
739 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
740 {
741 context_t *context = R700_CONTEXT(ctx);
742 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
743 unsigned int mask = ((r ? 1 : 0) |
744 (g ? 2 : 0) |
745 (b ? 4 : 0) |
746 (a ? 8 : 0));
747
748 if (mask != r700->CB_SHADER_MASK.u32All) {
749 R600_STATECHANGE(context, cb);
750 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
751 }
752 }
753
754 /**
755 * Change the depth testing function.
756 *
757 * \note Mesa already filters redundant calls to this function.
758 */
759 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
760 {
761 r700SetDepthState(ctx);
762 }
763
764 /**
765 * Enable/Disable depth writing.
766 *
767 * \note Mesa already filters redundant calls to this function.
768 */
769 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
770 {
771 r700SetDepthState(ctx);
772 }
773
774 /**
775 * Change the culling mode.
776 *
777 * \note Mesa already filters redundant calls to this function.
778 */
779 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
780 {
781 r700UpdateCulling(ctx);
782 }
783
784 /* =============================================================
785 * Fog
786 */
787 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
788 {
789 }
790
791 /**
792 * Change the polygon orientation.
793 *
794 * \note Mesa already filters redundant calls to this function.
795 */
796 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
797 {
798 r700UpdateCulling(ctx);
799 r700UpdatePolygonMode(ctx);
800 }
801
802 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
803 {
804 context_t *context = R700_CONTEXT(ctx);
805 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
806
807 R600_STATECHANGE(context, spi);
808
809 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
810 switch (mode) {
811 case GL_FLAT:
812 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
813 break;
814 case GL_SMOOTH:
815 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
816 break;
817 default:
818 return;
819 }
820 }
821
822 /* =============================================================
823 * Point state
824 */
825 static void r700PointSize(GLcontext * ctx, GLfloat size)
826 {
827 context_t *context = R700_CONTEXT(ctx);
828 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
829
830 R600_STATECHANGE(context, su);
831
832 /* We need to clamp to user defined range here, because
833 * the HW clamping happens only for per vertex point size. */
834 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
835
836 /* same size limits for AA, non-AA points */
837 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
838
839 /* format is 12.4 fixed point */
840 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
841 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
842 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
843 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
844
845 }
846
847 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
848 {
849 context_t *context = R700_CONTEXT(ctx);
850 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
851
852 R600_STATECHANGE(context, su);
853
854 /* format is 12.4 fixed point */
855 switch (pname) {
856 case GL_POINT_SIZE_MIN:
857 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
858 MIN_SIZE_shift, MIN_SIZE_mask);
859 break;
860 case GL_POINT_SIZE_MAX:
861 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
862 MAX_SIZE_shift, MAX_SIZE_mask);
863 break;
864 case GL_POINT_DISTANCE_ATTENUATION:
865 break;
866 case GL_POINT_FADE_THRESHOLD_SIZE:
867 break;
868 default:
869 break;
870 }
871 }
872
873 static int translate_stencil_func(int func)
874 {
875 switch (func) {
876 case GL_NEVER:
877 return REF_NEVER;
878 case GL_LESS:
879 return REF_LESS;
880 case GL_EQUAL:
881 return REF_EQUAL;
882 case GL_LEQUAL:
883 return REF_LEQUAL;
884 case GL_GREATER:
885 return REF_GREATER;
886 case GL_NOTEQUAL:
887 return REF_NOTEQUAL;
888 case GL_GEQUAL:
889 return REF_GEQUAL;
890 case GL_ALWAYS:
891 return REF_ALWAYS;
892 }
893 return 0;
894 }
895
896 static int translate_stencil_op(int op)
897 {
898 switch (op) {
899 case GL_KEEP:
900 return STENCIL_KEEP;
901 case GL_ZERO:
902 return STENCIL_ZERO;
903 case GL_REPLACE:
904 return STENCIL_REPLACE;
905 case GL_INCR:
906 return STENCIL_INCR_CLAMP;
907 case GL_DECR:
908 return STENCIL_DECR_CLAMP;
909 case GL_INCR_WRAP_EXT:
910 return STENCIL_INCR_WRAP;
911 case GL_DECR_WRAP_EXT:
912 return STENCIL_DECR_WRAP;
913 case GL_INVERT:
914 return STENCIL_INVERT;
915 default:
916 WARN_ONCE("Do not know how to translate stencil op");
917 return STENCIL_KEEP;
918 }
919 return 0;
920 }
921
922 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
923 {
924 context_t *context = R700_CONTEXT(ctx);
925 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
926 GLboolean hw_stencil = GL_FALSE;
927
928 if (ctx->DrawBuffer) {
929 struct radeon_renderbuffer *rrbStencil
930 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
931 hw_stencil = (rrbStencil && rrbStencil->bo);
932 }
933
934 if (hw_stencil) {
935 R600_STATECHANGE(context, db);
936 if (state) {
937 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
938 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
939 } else
940 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
941 }
942 }
943
944 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
945 GLenum func, GLint ref, GLuint mask) //---------------------
946 {
947 context_t *context = R700_CONTEXT(ctx);
948 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
949 const unsigned back = ctx->Stencil._BackFace;
950
951 R600_STATECHANGE(context, stencil);
952 R600_STATECHANGE(context, db);
953
954 //front
955 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
956 STENCILREF_shift, STENCILREF_mask);
957 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
958 STENCILMASK_shift, STENCILMASK_mask);
959
960 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
961 STENCILFUNC_shift, STENCILFUNC_mask);
962
963 //back
964 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
965 STENCILREF_BF_shift, STENCILREF_BF_mask);
966 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
967 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
968
969 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
970 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
971
972 }
973
974 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
975 {
976 context_t *context = R700_CONTEXT(ctx);
977 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
978 const unsigned back = ctx->Stencil._BackFace;
979
980 R600_STATECHANGE(context, stencil);
981
982 // front
983 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
984 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
985
986 // back
987 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
988 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
989
990 }
991
992 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
993 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
994 {
995 context_t *context = R700_CONTEXT(ctx);
996 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
997 const unsigned back = ctx->Stencil._BackFace;
998
999 R600_STATECHANGE(context, db);
1000
1001 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1002 STENCILFAIL_shift, STENCILFAIL_mask);
1003 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1004 STENCILZFAIL_shift, STENCILZFAIL_mask);
1005 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1006 STENCILZPASS_shift, STENCILZPASS_mask);
1007
1008 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1009 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1010 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1011 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1012 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1013 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1014 }
1015
1016 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1017 {
1018 context_t *context = R700_CONTEXT(ctx);
1019 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1020 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1021 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1022 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1023 const GLfloat *v = ctx->Viewport._WindowMap.m;
1024 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1025 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1026 GLfloat y_scale, y_bias;
1027
1028 if (render_to_fbo) {
1029 y_scale = 1.0;
1030 y_bias = 0;
1031 } else {
1032 y_scale = -1.0;
1033 y_bias = yoffset;
1034 }
1035
1036 GLfloat sx = v[MAT_SX];
1037 GLfloat tx = v[MAT_TX] + xoffset;
1038 GLfloat sy = v[MAT_SY] * y_scale;
1039 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1040 GLfloat sz = v[MAT_SZ] * depthScale;
1041 GLfloat tz = v[MAT_TZ] * depthScale;
1042
1043 R600_STATECHANGE(context, vpt);
1044
1045 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1046 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1047
1048 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1049 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1050
1051 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1052 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1053
1054 r700->viewport[id].enabled = GL_TRUE;
1055
1056 r700SetScissor(context);
1057 }
1058
1059
1060 static void r700Viewport(GLcontext * ctx,
1061 GLint x,
1062 GLint y,
1063 GLsizei width,
1064 GLsizei height) //--------------------
1065 {
1066 r700UpdateWindow(ctx, 0);
1067
1068 radeon_viewport(ctx, x, y, width, height);
1069 }
1070
1071 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1072 {
1073 r700UpdateWindow(ctx, 0);
1074 }
1075
1076 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1077 {
1078 context_t *context = R700_CONTEXT(ctx);
1079 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1080 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1081
1082 R600_STATECHANGE(context, su);
1083
1084 if (lineWidth > 0xFFFF)
1085 lineWidth = 0xFFFF;
1086 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1087 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1088 }
1089
1090 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1091 {
1092 context_t *context = R700_CONTEXT(ctx);
1093 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1094
1095 R600_STATECHANGE(context, sc);
1096
1097 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1098 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1099 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1100 }
1101
1102 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1103 {
1104 context_t *context = R700_CONTEXT(ctx);
1105 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1106
1107 R600_STATECHANGE(context, su);
1108
1109 if (state) {
1110 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1111 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1112 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1113 } else {
1114 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1115 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1116 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1117 }
1118 }
1119
1120 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1121 {
1122 context_t *context = R700_CONTEXT(ctx);
1123 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1124 GLfloat constant = units;
1125 GLchar depth = 0;
1126
1127 R600_STATECHANGE(context, poly);
1128
1129 switch (ctx->Visual.depthBits) {
1130 case 16:
1131 constant *= 4.0;
1132 depth = -16;
1133 break;
1134 case 24:
1135 constant *= 2.0;
1136 depth = -24;
1137 break;
1138 }
1139
1140 factor *= 12.0;
1141 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1142 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1143 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1144 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1145 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1146 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1147 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1148 }
1149
1150 static void r700UpdatePolygonMode(GLcontext * ctx)
1151 {
1152 context_t *context = R700_CONTEXT(ctx);
1153 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1154
1155 R600_STATECHANGE(context, su);
1156
1157 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1158
1159 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1160 if (ctx->Polygon.FrontMode != GL_FILL ||
1161 ctx->Polygon.BackMode != GL_FILL) {
1162 GLenum f, b;
1163
1164 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1165 * correctly by selecting the correct front and back face
1166 */
1167 if (ctx->Polygon.FrontFace == GL_CCW) {
1168 f = ctx->Polygon.FrontMode;
1169 b = ctx->Polygon.BackMode;
1170 } else {
1171 f = ctx->Polygon.BackMode;
1172 b = ctx->Polygon.FrontMode;
1173 }
1174
1175 /* Enable polygon mode */
1176 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1177
1178 switch (f) {
1179 case GL_LINE:
1180 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1181 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1182 break;
1183 case GL_POINT:
1184 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1185 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1186 break;
1187 case GL_FILL:
1188 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1189 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1190 break;
1191 }
1192
1193 switch (b) {
1194 case GL_LINE:
1195 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1196 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1197 break;
1198 case GL_POINT:
1199 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1200 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1201 break;
1202 case GL_FILL:
1203 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1204 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1205 break;
1206 }
1207 }
1208 }
1209
1210 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1211 {
1212 (void)face;
1213 (void)mode;
1214
1215 r700UpdatePolygonMode(ctx);
1216 }
1217
1218 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1219 {
1220 }
1221
1222 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1223 {
1224 context_t *context = R700_CONTEXT(ctx);
1225 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1226 GLint p;
1227 GLint *ip;
1228
1229 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1230 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1231
1232 R600_STATECHANGE(context, ucp);
1233
1234 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1235 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1236 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1237 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1238 }
1239
1240 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1241 {
1242 context_t *context = R700_CONTEXT(ctx);
1243 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1244 GLuint p;
1245
1246 p = cap - GL_CLIP_PLANE0;
1247
1248 R600_STATECHANGE(context, cl);
1249
1250 if (state) {
1251 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1252 r700->ucp[p].enabled = GL_TRUE;
1253 r700ClipPlane(ctx, cap, NULL);
1254 } else {
1255 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1256 r700->ucp[p].enabled = GL_FALSE;
1257 }
1258 }
1259
1260 void r700SetScissor(context_t *context) //---------------
1261 {
1262 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1263 unsigned x1, y1, x2, y2;
1264 int id = 0;
1265 struct radeon_renderbuffer *rrb;
1266
1267 rrb = radeon_get_colorbuffer(&context->radeon);
1268 if (!rrb || !rrb->bo) {
1269 return;
1270 }
1271 if (context->radeon.state.scissor.enabled) {
1272 x1 = context->radeon.state.scissor.rect.x1;
1273 y1 = context->radeon.state.scissor.rect.y1;
1274 x2 = context->radeon.state.scissor.rect.x2;
1275 y2 = context->radeon.state.scissor.rect.y2;
1276 /* r600 has exclusive BR scissors */
1277 if (context->radeon.radeonScreen->kernel_mm) {
1278 x2++;
1279 y2++;
1280 }
1281 } else {
1282 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1283 x1 = 0;
1284 y1 = 0;
1285 x2 = rrb->base.Width;
1286 y2 = rrb->base.Height;
1287 } else {
1288 x1 = rrb->dPriv->x;
1289 y1 = rrb->dPriv->y;
1290 x2 = rrb->dPriv->x + rrb->dPriv->w;
1291 y2 = rrb->dPriv->y + rrb->dPriv->h;
1292 }
1293 }
1294
1295 R600_STATECHANGE(context, scissor);
1296
1297 /* screen */
1298 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1299 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1300 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1301 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1302 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1303
1304 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1305 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1306 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1307 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1308
1309 /* window */
1310 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1311 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1312 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1313 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1314 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1315
1316 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1317 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1318 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1319 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1320
1321
1322 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1323 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1324 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1325 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1326 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1327 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1328 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1329 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1330
1331 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1332 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1333 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1334 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1335 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1336 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1337
1338 /* more....2d clip */
1339 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1340 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1341 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1342 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1343 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1344 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1345 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1346 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1347 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1348
1349 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1350 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1351 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1352 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1353 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1354 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1355 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1356 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1357 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1358
1359 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1360 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1361 r700->viewport[id].enabled = GL_TRUE;
1362 }
1363
1364 static void r700InitSQConfig(GLcontext * ctx)
1365 {
1366 context_t *context = R700_CONTEXT(ctx);
1367 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1368 int ps_prio;
1369 int vs_prio;
1370 int gs_prio;
1371 int es_prio;
1372 int num_ps_gprs;
1373 int num_vs_gprs;
1374 int num_gs_gprs;
1375 int num_es_gprs;
1376 int num_temp_gprs;
1377 int num_ps_threads;
1378 int num_vs_threads;
1379 int num_gs_threads;
1380 int num_es_threads;
1381 int num_ps_stack_entries;
1382 int num_vs_stack_entries;
1383 int num_gs_stack_entries;
1384 int num_es_stack_entries;
1385
1386 R600_STATECHANGE(context, sq);
1387
1388 // SQ
1389 ps_prio = 0;
1390 vs_prio = 1;
1391 gs_prio = 2;
1392 es_prio = 3;
1393 switch (context->radeon.radeonScreen->chip_family) {
1394 case CHIP_FAMILY_R600:
1395 num_ps_gprs = 192;
1396 num_vs_gprs = 56;
1397 num_temp_gprs = 4;
1398 num_gs_gprs = 0;
1399 num_es_gprs = 0;
1400 num_ps_threads = 136;
1401 num_vs_threads = 48;
1402 num_gs_threads = 4;
1403 num_es_threads = 4;
1404 num_ps_stack_entries = 128;
1405 num_vs_stack_entries = 128;
1406 num_gs_stack_entries = 0;
1407 num_es_stack_entries = 0;
1408 break;
1409 case CHIP_FAMILY_RV630:
1410 case CHIP_FAMILY_RV635:
1411 num_ps_gprs = 84;
1412 num_vs_gprs = 36;
1413 num_temp_gprs = 4;
1414 num_gs_gprs = 0;
1415 num_es_gprs = 0;
1416 num_ps_threads = 144;
1417 num_vs_threads = 40;
1418 num_gs_threads = 4;
1419 num_es_threads = 4;
1420 num_ps_stack_entries = 40;
1421 num_vs_stack_entries = 40;
1422 num_gs_stack_entries = 32;
1423 num_es_stack_entries = 16;
1424 break;
1425 case CHIP_FAMILY_RV610:
1426 case CHIP_FAMILY_RV620:
1427 case CHIP_FAMILY_RS780:
1428 case CHIP_FAMILY_RS880:
1429 default:
1430 num_ps_gprs = 84;
1431 num_vs_gprs = 36;
1432 num_temp_gprs = 4;
1433 num_gs_gprs = 0;
1434 num_es_gprs = 0;
1435 num_ps_threads = 136;
1436 num_vs_threads = 48;
1437 num_gs_threads = 4;
1438 num_es_threads = 4;
1439 num_ps_stack_entries = 40;
1440 num_vs_stack_entries = 40;
1441 num_gs_stack_entries = 32;
1442 num_es_stack_entries = 16;
1443 break;
1444 case CHIP_FAMILY_RV670:
1445 num_ps_gprs = 144;
1446 num_vs_gprs = 40;
1447 num_temp_gprs = 4;
1448 num_gs_gprs = 0;
1449 num_es_gprs = 0;
1450 num_ps_threads = 136;
1451 num_vs_threads = 48;
1452 num_gs_threads = 4;
1453 num_es_threads = 4;
1454 num_ps_stack_entries = 40;
1455 num_vs_stack_entries = 40;
1456 num_gs_stack_entries = 32;
1457 num_es_stack_entries = 16;
1458 break;
1459 case CHIP_FAMILY_RV770:
1460 num_ps_gprs = 192;
1461 num_vs_gprs = 56;
1462 num_temp_gprs = 4;
1463 num_gs_gprs = 0;
1464 num_es_gprs = 0;
1465 num_ps_threads = 188;
1466 num_vs_threads = 60;
1467 num_gs_threads = 0;
1468 num_es_threads = 0;
1469 num_ps_stack_entries = 256;
1470 num_vs_stack_entries = 256;
1471 num_gs_stack_entries = 0;
1472 num_es_stack_entries = 0;
1473 break;
1474 case CHIP_FAMILY_RV730:
1475 case CHIP_FAMILY_RV740:
1476 num_ps_gprs = 84;
1477 num_vs_gprs = 36;
1478 num_temp_gprs = 4;
1479 num_gs_gprs = 0;
1480 num_es_gprs = 0;
1481 num_ps_threads = 188;
1482 num_vs_threads = 60;
1483 num_gs_threads = 0;
1484 num_es_threads = 0;
1485 num_ps_stack_entries = 128;
1486 num_vs_stack_entries = 128;
1487 num_gs_stack_entries = 0;
1488 num_es_stack_entries = 0;
1489 break;
1490 case CHIP_FAMILY_RV710:
1491 num_ps_gprs = 192;
1492 num_vs_gprs = 56;
1493 num_temp_gprs = 4;
1494 num_gs_gprs = 0;
1495 num_es_gprs = 0;
1496 num_ps_threads = 144;
1497 num_vs_threads = 48;
1498 num_gs_threads = 0;
1499 num_es_threads = 0;
1500 num_ps_stack_entries = 128;
1501 num_vs_stack_entries = 128;
1502 num_gs_stack_entries = 0;
1503 num_es_stack_entries = 0;
1504 break;
1505 }
1506
1507 r700->sq_config.SQ_CONFIG.u32All = 0;
1508 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1509 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1510 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1511 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1512 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1513 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1514 else
1515 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1516 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1517 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1518 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1519 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1520 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1521 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1522
1523 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1524 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1525 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1526 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1527 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1528
1529 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1530 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1531 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1532
1533 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1534 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1535 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1536 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1537 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1538 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1539 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1540 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1541 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1542
1543 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1544 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1545 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1546 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1547 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1548
1549 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1550 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1551 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1552 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1553 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1554
1555 }
1556
1557 /**
1558 * Calculate initial hardware state and register state functions.
1559 * Assumes that the command buffer and state atoms have been
1560 * initialized already.
1561 */
1562 void r700InitState(GLcontext * ctx) //-------------------
1563 {
1564 context_t *context = R700_CONTEXT(ctx);
1565 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1566 int id = 0;
1567
1568 radeon_firevertices(&context->radeon);
1569
1570 r700->TA_CNTL_AUX.u32All = 0;
1571 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1572 r700->VC_ENHANCE.u32All = 0;
1573 r700->DB_WATERMARKS.u32All = 0;
1574 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1575 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1576 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1577 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1578 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1579 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1580 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1581 r700->DB_DEBUG.u32All = 0x82000000;
1582 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1583 } else {
1584 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1585 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1586 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1587 }
1588
1589 /* Turn off vgt reuse */
1590 r700->VGT_REUSE_OFF.u32All = 0;
1591 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1592
1593 /* Specify offsetting and clamp values for vertices */
1594 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1595 r700->VGT_MIN_VTX_INDX.u32All = 0;
1596 r700->VGT_INDX_OFFSET.u32All = 0;
1597
1598 /* default shader connections. */
1599 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1600 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1601 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1602 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1603
1604 r700->SPI_THREAD_GROUPING.u32All = 0;
1605 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1606 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1607
1608 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1609 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1610 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1611
1612 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1613 r700->PA_SC_EDGERULE.u32All = 0;
1614 else
1615 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1616
1617 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1618 r700->PA_SC_MODE_CNTL.u32All = 0;
1619 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1620 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1621 } else {
1622 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1623 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1624 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1625 }
1626
1627 /* Do scale XY and Z by 1/W0. */
1628 r700->bEnablePerspective = GL_TRUE;
1629 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1630 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1631 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1632
1633 /* Enable viewport scaling for all three axis */
1634 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1635 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1636 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1637 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1638 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1639 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1640
1641 /* GL uses last vtx for flat shading components */
1642 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1643
1644 /* Set up vertex control */
1645 r700->PA_SU_VTX_CNTL.u32All = 0;
1646 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1647 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1648 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1649 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1650
1651 /* to 1.0 = no guard band */
1652 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1653 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1654 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1655 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1656
1657 /* Enable all samples for multi-sample anti-aliasing */
1658 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1659 /* Turn off AA */
1660 r700->PA_SC_AA_CONFIG.u32All = 0;
1661
1662 r700->SX_MISC.u32All = 0;
1663
1664 r700InitSQConfig(ctx);
1665
1666 r700ColorMask(ctx,
1667 ctx->Color.ColorMask[RCOMP],
1668 ctx->Color.ColorMask[GCOMP],
1669 ctx->Color.ColorMask[BCOMP],
1670 ctx->Color.ColorMask[ACOMP]);
1671
1672 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1673 r700DepthMask(ctx, ctx->Depth.Mask);
1674 r700DepthFunc(ctx, ctx->Depth.Func);
1675 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1676
1677 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1678
1679 r700->DB_RENDER_CONTROL.u32All = 0;
1680 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1681 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1682 r700->DB_RENDER_OVERRIDE.u32All = 0;
1683 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1684 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1685 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1686 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1687 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1688
1689 r700->DB_ALPHA_TO_MASK.u32All = 0;
1690 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1691 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1692 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1693 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1694
1695 /* stencil */
1696 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1697 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1698 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1699 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1700 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1701 ctx->Stencil.ZFailFunc[0],
1702 ctx->Stencil.ZPassFunc[0]);
1703
1704 r700UpdateCulling(ctx);
1705
1706 r700SetBlendState(ctx);
1707 r700SetLogicOpState(ctx);
1708
1709 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1710 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1711
1712 r700PointSize(ctx, 1.0);
1713
1714 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1715 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1716
1717 r700LineWidth(ctx, 1.0);
1718
1719 r700->PA_SC_LINE_CNTL.u32All = 0;
1720 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1721 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1722
1723 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1724 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1725 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1726 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1727 ctx->Polygon.OffsetUnits);
1728 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1729 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1730 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1731
1732 /* CB */
1733 r700BlendColor(ctx, ctx->Color.BlendColor);
1734
1735 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1736 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1737 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1738 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1739 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1740 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1741 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1742
1743 /* Disable color compares */
1744 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1745 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1746 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1747 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1748 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1749 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1750
1751 /* Zero out source */
1752 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1753
1754 /* Put a compare color in for error checking */
1755 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1756
1757 /* Set up color compare mask */
1758 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1759
1760 /* screen/window/view */
1761 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1762
1763 context->radeon.hw.all_dirty = GL_TRUE;
1764
1765 }
1766
1767 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1768 {
1769 functions->UpdateState = r700InvalidateState;
1770 functions->AlphaFunc = r700AlphaFunc;
1771 functions->BlendColor = r700BlendColor;
1772 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1773 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1774 functions->Enable = r700Enable;
1775 functions->ColorMask = r700ColorMask;
1776 functions->DepthFunc = r700DepthFunc;
1777 functions->DepthMask = r700DepthMask;
1778 functions->CullFace = r700CullFace;
1779 functions->Fogfv = r700Fogfv;
1780 functions->FrontFace = r700FrontFace;
1781 functions->ShadeModel = r700ShadeModel;
1782 functions->LogicOpcode = r700LogicOpcode;
1783
1784 /* ARB_point_parameters */
1785 functions->PointParameterfv = r700PointParameter;
1786
1787 /* Stencil related */
1788 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1789 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1790 functions->StencilOpSeparate = r700StencilOpSeparate;
1791
1792 /* Viewport related */
1793 functions->Viewport = r700Viewport;
1794 functions->DepthRange = r700DepthRange;
1795 functions->PointSize = r700PointSize;
1796 functions->LineWidth = r700LineWidth;
1797 functions->LineStipple = r700LineStipple;
1798
1799 functions->PolygonOffset = r700PolygonOffset;
1800 functions->PolygonMode = r700PolygonMode;
1801
1802 functions->RenderMode = r700RenderMode;
1803
1804 functions->ClipPlane = r700ClipPlane;
1805
1806 functions->Scissor = radeonScissor;
1807
1808 functions->DrawBuffer = radeonDrawBuffer;
1809 functions->ReadBuffer = radeonReadBuffer;
1810
1811 }
1812