2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
49 #include "main/texformat.h"
51 #include "r600_context.h"
53 #include "r700_state.h"
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
59 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
);
60 static void r700UpdatePolygonMode(GLcontext
* ctx
);
61 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
);
62 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
);
64 void r700UpdateShaders (GLcontext
* ctx
) //----------------------------------
66 context_t
*context
= R700_CONTEXT(ctx
);
67 GLvector4f dummy_attrib
[_TNL_ATTRIB_MAX
];
68 GLvector4f
*temp_attrib
[_TNL_ATTRIB_MAX
];
71 /* should only happenen once, just after context is created */
72 /* TODO: shouldn't we fallback to sw here? */
73 if (!ctx
->FragmentProgram
._Current
) {
74 _mesa_fprintf(stderr
, "No ctx->FragmentProgram._Current!!\n");
78 r700SelectFragmentShader(ctx
);
80 if (context
->radeon
.NewGLState
) {
81 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++) {
82 /* mat states from state var not array for sw */
83 dummy_attrib
[i
].stride
= 0;
84 temp_attrib
[i
] = TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
];
85 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = &(dummy_attrib
[i
]);
88 _tnl_UpdateFixedFunctionProgram(ctx
);
90 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++) {
91 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = temp_attrib
[i
];
95 r700SelectVertexShader(ctx
, 1);
96 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
);
97 context
->radeon
.NewGLState
= 0;
100 void r700UpdateShaders2(GLcontext
* ctx
)
102 context_t
*context
= R700_CONTEXT(ctx
);
104 /* should only happenen once, just after context is created */
105 /* TODO: shouldn't we fallback to sw here? */
106 if (!ctx
->FragmentProgram
._Current
) {
107 _mesa_fprintf(stderr
, "No ctx->FragmentProgram._Current!!\n");
111 r700SelectFragmentShader(ctx
);
113 r700SelectVertexShader(ctx
, 2);
114 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
);
115 context
->radeon
.NewGLState
= 0;
119 * To correctly position primitives:
121 void r700UpdateViewportOffset(GLcontext
* ctx
) //------------------
123 context_t
*context
= R700_CONTEXT(ctx
);
124 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
125 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
126 GLfloat xoffset
= (GLfloat
) dPriv
->x
;
127 GLfloat yoffset
= (GLfloat
) dPriv
->y
+ dPriv
->h
;
128 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
131 GLfloat tx
= v
[MAT_TX
] + xoffset
;
132 GLfloat ty
= (-v
[MAT_TY
]) + yoffset
;
134 if (r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
!= tx
||
135 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
!= ty
) {
136 /* Note: this should also modify whatever data the context reset
139 R600_STATECHANGE(context
, vpt
);
140 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
141 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
144 radeonUpdateScissor(ctx
);
147 void r700UpdateStateParameters(GLcontext
* ctx
, GLuint new_state
) //--------------------
149 struct r700_fragment_program
*fp
=
150 (struct r700_fragment_program
*)ctx
->FragmentProgram
._Current
;
151 struct gl_program_parameter_list
*paramList
;
153 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
)))
156 if (!ctx
->FragmentProgram
._Current
|| !fp
)
159 paramList
= ctx
->FragmentProgram
._Current
->Base
.Parameters
;
164 _mesa_load_state_parameters(ctx
, paramList
);
169 * Called by Mesa after an internal state update.
171 static void r700InvalidateState(GLcontext
* ctx
, GLuint new_state
) //-------------------
173 context_t
*context
= R700_CONTEXT(ctx
);
175 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
177 _swrast_InvalidateState(ctx
, new_state
);
178 _swsetup_InvalidateState(ctx
, new_state
);
179 _vbo_InvalidateState(ctx
, new_state
);
180 _tnl_InvalidateState(ctx
, new_state
);
181 _ae_invalidate_state(ctx
, new_state
);
183 if (new_state
& _NEW_BUFFERS
) {
184 _mesa_update_framebuffer(ctx
);
185 /* this updates the DrawBuffer's Width/Height if it's a FBO */
186 _mesa_update_draw_buffer_bounds(ctx
);
188 R600_STATECHANGE(context
, cb_target
);
189 R600_STATECHANGE(context
, db_target
);
192 if (new_state
& (_NEW_LIGHT
)) {
193 R600_STATECHANGE(context
, su
);
194 if (ctx
->Light
.ProvokingVertex
== GL_LAST_VERTEX_CONVENTION
)
195 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
197 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
200 r700UpdateStateParameters(ctx
, new_state
);
202 R600_STATECHANGE(context
, cl
);
203 R600_STATECHANGE(context
, spi
);
205 if(GL_TRUE
== r700
->bEnablePerspective
)
207 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
208 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
209 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
211 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
213 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
214 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
218 /* For orthogonal case. */
219 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
220 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
222 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
224 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
225 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
228 context
->radeon
.NewGLState
|= new_state
;
231 static void r700SetDepthState(GLcontext
* ctx
)
233 context_t
*context
= R700_CONTEXT(ctx
);
234 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
236 R600_STATECHANGE(context
, db
);
240 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
243 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
247 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
250 switch (ctx
->Depth
.Func
)
253 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
254 ZFUNC_shift
, ZFUNC_mask
);
257 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
258 ZFUNC_shift
, ZFUNC_mask
);
261 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
262 ZFUNC_shift
, ZFUNC_mask
);
265 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
266 ZFUNC_shift
, ZFUNC_mask
);
269 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
270 ZFUNC_shift
, ZFUNC_mask
);
273 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
274 ZFUNC_shift
, ZFUNC_mask
);
277 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
278 ZFUNC_shift
, ZFUNC_mask
);
281 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
282 ZFUNC_shift
, ZFUNC_mask
);
285 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
286 ZFUNC_shift
, ZFUNC_mask
);
292 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
293 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
297 static void r700SetAlphaState(GLcontext
* ctx
)
299 context_t
*context
= R700_CONTEXT(ctx
);
300 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
301 uint32_t alpha_func
= REF_ALWAYS
;
302 GLboolean really_enabled
= ctx
->Color
.AlphaEnabled
;
304 R600_STATECHANGE(context
, sx
);
306 switch (ctx
->Color
.AlphaFunc
) {
308 alpha_func
= REF_NEVER
;
311 alpha_func
= REF_LESS
;
314 alpha_func
= REF_EQUAL
;
317 alpha_func
= REF_LEQUAL
;
320 alpha_func
= REF_GREATER
;
323 alpha_func
= REF_NOTEQUAL
;
326 alpha_func
= REF_GEQUAL
;
329 /*alpha_func = REF_ALWAYS; */
330 really_enabled
= GL_FALSE
;
334 if (really_enabled
) {
335 SETfield(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, alpha_func
,
336 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
337 SETbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
338 r700
->SX_ALPHA_REF
.f32All
= ctx
->Color
.AlphaRef
;
340 CLEARbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
345 static void r700AlphaFunc(GLcontext
* ctx
, GLenum func
, GLfloat ref
) //---------------
349 r700SetAlphaState(ctx
);
353 static void r700BlendColor(GLcontext
* ctx
, const GLfloat cf
[4]) //----------------
355 context_t
*context
= R700_CONTEXT(ctx
);
356 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
358 R600_STATECHANGE(context
, blnd_clr
);
360 r700
->CB_BLEND_RED
.f32All
= cf
[0];
361 r700
->CB_BLEND_GREEN
.f32All
= cf
[1];
362 r700
->CB_BLEND_BLUE
.f32All
= cf
[2];
363 r700
->CB_BLEND_ALPHA
.f32All
= cf
[3];
366 static int blend_factor(GLenum factor
, GLboolean is_src
)
376 return BLEND_DST_COLOR
;
378 case GL_ONE_MINUS_DST_COLOR
:
379 return BLEND_ONE_MINUS_DST_COLOR
;
382 return BLEND_SRC_COLOR
;
384 case GL_ONE_MINUS_SRC_COLOR
:
385 return BLEND_ONE_MINUS_SRC_COLOR
;
388 return BLEND_SRC_ALPHA
;
390 case GL_ONE_MINUS_SRC_ALPHA
:
391 return BLEND_ONE_MINUS_SRC_ALPHA
;
394 return BLEND_DST_ALPHA
;
396 case GL_ONE_MINUS_DST_ALPHA
:
397 return BLEND_ONE_MINUS_DST_ALPHA
;
399 case GL_SRC_ALPHA_SATURATE
:
400 return (is_src
) ? BLEND_SRC_ALPHA_SATURATE
: BLEND_ZERO
;
402 case GL_CONSTANT_COLOR
:
403 return BLEND_CONSTANT_COLOR
;
405 case GL_ONE_MINUS_CONSTANT_COLOR
:
406 return BLEND_ONE_MINUS_CONSTANT_COLOR
;
408 case GL_CONSTANT_ALPHA
:
409 return BLEND_CONSTANT_ALPHA
;
411 case GL_ONE_MINUS_CONSTANT_ALPHA
:
412 return BLEND_ONE_MINUS_CONSTANT_ALPHA
;
415 fprintf(stderr
, "unknown blend factor %x\n", factor
);
416 return (is_src
) ? BLEND_ONE
: BLEND_ZERO
;
421 static void r700SetBlendState(GLcontext
* ctx
)
423 context_t
*context
= R700_CONTEXT(ctx
);
424 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
426 uint32_t blend_reg
= 0, eqn
, eqnA
;
428 R600_STATECHANGE(context
, blnd
);
430 if (RGBA_LOGICOP_ENABLED(ctx
) || !ctx
->Color
.BlendEnabled
) {
432 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
434 BLEND_ZERO
, COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
436 COMB_DST_PLUS_SRC
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
438 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
440 BLEND_ZERO
, ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
442 COMB_DST_PLUS_SRC
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
443 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
444 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
446 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
451 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
452 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
454 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
455 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
457 switch (ctx
->Color
.BlendEquationRGB
) {
459 eqn
= COMB_DST_PLUS_SRC
;
461 case GL_FUNC_SUBTRACT
:
462 eqn
= COMB_SRC_MINUS_DST
;
464 case GL_FUNC_REVERSE_SUBTRACT
:
465 eqn
= COMB_DST_MINUS_SRC
;
468 eqn
= COMB_MIN_DST_SRC
;
471 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
474 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
477 eqn
= COMB_MAX_DST_SRC
;
480 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
483 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
488 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
489 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationRGB
);
493 eqn
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
496 blend_factor(ctx
->Color
.BlendSrcA
, GL_TRUE
),
497 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
499 blend_factor(ctx
->Color
.BlendDstA
, GL_FALSE
),
500 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
502 switch (ctx
->Color
.BlendEquationA
) {
504 eqnA
= COMB_DST_PLUS_SRC
;
506 case GL_FUNC_SUBTRACT
:
507 eqnA
= COMB_SRC_MINUS_DST
;
509 case GL_FUNC_REVERSE_SUBTRACT
:
510 eqnA
= COMB_DST_MINUS_SRC
;
513 eqnA
= COMB_MIN_DST_SRC
;
516 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
519 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
522 eqnA
= COMB_MAX_DST_SRC
;
525 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
528 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
532 "[%s:%u] Invalid A blend equation (0x%04x).\n",
533 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationA
);
538 eqnA
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
540 SETbit(blend_reg
, SEPARATE_ALPHA_BLEND_bit
);
542 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
543 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
545 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
546 SETbit(r700
->CB_COLOR_CONTROL
.u32All
, PER_MRT_BLEND_bit
);
548 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, (1 << id
),
549 TARGET_BLEND_ENABLE_shift
, TARGET_BLEND_ENABLE_mask
);
553 static void r700BlendEquationSeparate(GLcontext
* ctx
,
554 GLenum modeRGB
, GLenum modeA
) //-----------------
556 r700SetBlendState(ctx
);
559 static void r700BlendFuncSeparate(GLcontext
* ctx
,
560 GLenum sfactorRGB
, GLenum dfactorRGB
,
561 GLenum sfactorA
, GLenum dfactorA
) //------------------------
563 r700SetBlendState(ctx
);
567 * Translate LogicOp enums into hardware representation.
569 static GLuint
translate_logicop(GLenum logicop
)
578 case GL_COPY_INVERTED
:
598 case GL_AND_INVERTED
:
605 fprintf(stderr
, "unknown blend logic operation %x\n", logicop
);
611 * Used internally to update the r300->hw hardware state to match the
612 * current OpenGL state.
614 static void r700SetLogicOpState(GLcontext
*ctx
)
616 context_t
*context
= R700_CONTEXT(ctx
);
617 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
619 R600_STATECHANGE(context
, blnd
);
621 if (RGBA_LOGICOP_ENABLED(ctx
))
622 SETfield(r700
->CB_COLOR_CONTROL
.u32All
,
623 translate_logicop(ctx
->Color
.LogicOp
), ROP3_shift
, ROP3_mask
);
625 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, 0xCC, ROP3_shift
, ROP3_mask
);
629 * Called by Mesa when an application program changes the LogicOp state
632 static void r700LogicOpcode(GLcontext
*ctx
, GLenum logicop
)
634 if (RGBA_LOGICOP_ENABLED(ctx
))
635 r700SetLogicOpState(ctx
);
638 static void r700UpdateCulling(GLcontext
* ctx
)
640 context_t
*context
= R700_CONTEXT(ctx
);
641 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
643 R600_STATECHANGE(context
, su
);
645 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
646 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
647 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
649 if (ctx
->Polygon
.CullFlag
)
651 switch (ctx
->Polygon
.CullFaceMode
)
654 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
655 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
658 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
659 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
661 case GL_FRONT_AND_BACK
:
662 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
663 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
666 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
667 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
672 switch (ctx
->Polygon
.FrontFace
)
675 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
678 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
681 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
686 static void r700UpdateLineStipple(GLcontext
* ctx
)
688 context_t
*context
= R700_CONTEXT(ctx
);
689 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
691 R600_STATECHANGE(context
, sc
);
693 if (ctx
->Line
.StippleFlag
)
695 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
699 CLEARbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
703 static void r700Enable(GLcontext
* ctx
, GLenum cap
, GLboolean state
) //------------------
705 context_t
*context
= R700_CONTEXT(ctx
);
717 r700SetAlphaState(ctx
);
719 case GL_COLOR_LOGIC_OP
:
720 r700SetLogicOpState(ctx
);
721 /* fall-through, because logic op overrides blending */
723 r700SetBlendState(ctx
);
731 r700SetClipPlaneState(ctx
, cap
, state
);
734 r700SetDepthState(ctx
);
736 case GL_STENCIL_TEST
:
737 r700SetStencilState(ctx
, state
);
740 r700UpdateCulling(ctx
);
742 case GL_POLYGON_OFFSET_POINT
:
743 case GL_POLYGON_OFFSET_LINE
:
744 case GL_POLYGON_OFFSET_FILL
:
745 r700SetPolygonOffsetState(ctx
, state
);
747 case GL_SCISSOR_TEST
:
748 radeon_firevertices(&context
->radeon
);
749 context
->radeon
.state
.scissor
.enabled
= state
;
750 radeonUpdateScissor(ctx
);
752 case GL_LINE_STIPPLE
:
753 r700UpdateLineStipple(ctx
);
762 * Handle glColorMask()
764 static void r700ColorMask(GLcontext
* ctx
,
765 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //------------------
767 context_t
*context
= R700_CONTEXT(ctx
);
768 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
769 unsigned int mask
= ((r
? 1 : 0) |
774 if (mask
!= r700
->CB_TARGET_MASK
.u32All
) {
775 R600_STATECHANGE(context
, cb
);
776 SETfield(r700
->CB_TARGET_MASK
.u32All
, mask
, TARGET0_ENABLE_shift
, TARGET0_ENABLE_mask
);
781 * Change the depth testing function.
783 * \note Mesa already filters redundant calls to this function.
785 static void r700DepthFunc(GLcontext
* ctx
, GLenum func
) //--------------------
787 r700SetDepthState(ctx
);
791 * Enable/Disable depth writing.
793 * \note Mesa already filters redundant calls to this function.
795 static void r700DepthMask(GLcontext
* ctx
, GLboolean mask
) //------------------
797 r700SetDepthState(ctx
);
801 * Change the culling mode.
803 * \note Mesa already filters redundant calls to this function.
805 static void r700CullFace(GLcontext
* ctx
, GLenum mode
) //-----------------
807 r700UpdateCulling(ctx
);
810 /* =============================================================
813 static void r700Fogfv(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //--------------
818 * Change the polygon orientation.
820 * \note Mesa already filters redundant calls to this function.
822 static void r700FrontFace(GLcontext
* ctx
, GLenum mode
) //------------------
824 r700UpdateCulling(ctx
);
825 r700UpdatePolygonMode(ctx
);
828 static void r700ShadeModel(GLcontext
* ctx
, GLenum mode
) //--------------------
830 context_t
*context
= R700_CONTEXT(ctx
);
831 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
833 R600_STATECHANGE(context
, spi
);
835 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
838 SETbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
841 CLEARbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
848 /* =============================================================
851 static void r700PointSize(GLcontext
* ctx
, GLfloat size
)
853 context_t
*context
= R700_CONTEXT(ctx
);
854 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
856 R600_STATECHANGE(context
, su
);
858 /* We need to clamp to user defined range here, because
859 * the HW clamping happens only for per vertex point size. */
860 size
= CLAMP(size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
862 /* same size limits for AA, non-AA points */
863 size
= CLAMP(size
, ctx
->Const
.MinPointSize
, ctx
->Const
.MaxPointSize
);
865 /* format is 12.4 fixed point */
866 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 8.0),
867 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
868 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 8.0),
869 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
873 static void r700PointParameter(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //---------------
875 context_t
*context
= R700_CONTEXT(ctx
);
876 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
878 R600_STATECHANGE(context
, su
);
880 /* format is 12.4 fixed point */
882 case GL_POINT_SIZE_MIN
:
883 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MinSize
* 8.0),
884 MIN_SIZE_shift
, MIN_SIZE_mask
);
886 case GL_POINT_SIZE_MAX
:
887 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MaxSize
* 8.0),
888 MAX_SIZE_shift
, MAX_SIZE_mask
);
890 case GL_POINT_DISTANCE_ATTENUATION
:
892 case GL_POINT_FADE_THRESHOLD_SIZE
:
899 static int translate_stencil_func(int func
)
922 static int translate_stencil_op(int op
)
930 return STENCIL_REPLACE
;
932 return STENCIL_INCR_CLAMP
;
934 return STENCIL_DECR_CLAMP
;
935 case GL_INCR_WRAP_EXT
:
936 return STENCIL_INCR_WRAP
;
937 case GL_DECR_WRAP_EXT
:
938 return STENCIL_DECR_WRAP
;
940 return STENCIL_INVERT
;
942 WARN_ONCE("Do not know how to translate stencil op");
948 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
)
950 context_t
*context
= R700_CONTEXT(ctx
);
951 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
952 GLboolean hw_stencil
= GL_FALSE
;
954 if (ctx
->DrawBuffer
) {
955 struct radeon_renderbuffer
*rrbStencil
956 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
957 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
961 R600_STATECHANGE(context
, db
);
963 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
964 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, BACKFACE_ENABLE_bit
);
966 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
970 static void r700StencilFuncSeparate(GLcontext
* ctx
, GLenum face
,
971 GLenum func
, GLint ref
, GLuint mask
) //---------------------
973 context_t
*context
= R700_CONTEXT(ctx
);
974 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
975 const unsigned back
= ctx
->Stencil
._BackFace
;
977 R600_STATECHANGE(context
, stencil
);
978 R600_STATECHANGE(context
, db
);
981 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.Ref
[0],
982 STENCILREF_shift
, STENCILREF_mask
);
983 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.ValueMask
[0],
984 STENCILMASK_shift
, STENCILMASK_mask
);
986 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[0]),
987 STENCILFUNC_shift
, STENCILFUNC_mask
);
990 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.Ref
[back
],
991 STENCILREF_BF_shift
, STENCILREF_BF_mask
);
992 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.ValueMask
[back
],
993 STENCILMASK_BF_shift
, STENCILMASK_BF_mask
);
995 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[back
]),
996 STENCILFUNC_BF_shift
, STENCILFUNC_BF_mask
);
1000 static void r700StencilMaskSeparate(GLcontext
* ctx
, GLenum face
, GLuint mask
) //--------------
1002 context_t
*context
= R700_CONTEXT(ctx
);
1003 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1004 const unsigned back
= ctx
->Stencil
._BackFace
;
1006 R600_STATECHANGE(context
, stencil
);
1009 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.WriteMask
[0],
1010 STENCILWRITEMASK_shift
, STENCILWRITEMASK_mask
);
1013 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.WriteMask
[back
],
1014 STENCILWRITEMASK_BF_shift
, STENCILWRITEMASK_BF_mask
);
1018 static void r700StencilOpSeparate(GLcontext
* ctx
, GLenum face
,
1019 GLenum fail
, GLenum zfail
, GLenum zpass
) //--------------------
1021 context_t
*context
= R700_CONTEXT(ctx
);
1022 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1023 const unsigned back
= ctx
->Stencil
._BackFace
;
1025 R600_STATECHANGE(context
, db
);
1027 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[0]),
1028 STENCILFAIL_shift
, STENCILFAIL_mask
);
1029 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]),
1030 STENCILZFAIL_shift
, STENCILZFAIL_mask
);
1031 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]),
1032 STENCILZPASS_shift
, STENCILZPASS_mask
);
1034 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]),
1035 STENCILFAIL_BF_shift
, STENCILFAIL_BF_mask
);
1036 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]),
1037 STENCILZFAIL_BF_shift
, STENCILZFAIL_BF_mask
);
1038 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]),
1039 STENCILZPASS_BF_shift
, STENCILZPASS_BF_mask
);
1042 static void r700UpdateWindow(GLcontext
* ctx
, int id
) //--------------------
1044 context_t
*context
= R700_CONTEXT(ctx
);
1045 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1046 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
1047 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
1048 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
1049 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1050 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1051 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
1052 GLfloat y_scale
, y_bias
;
1054 if (render_to_fbo
) {
1062 GLfloat sx
= v
[MAT_SX
];
1063 GLfloat tx
= v
[MAT_TX
] + xoffset
;
1064 GLfloat sy
= v
[MAT_SY
] * y_scale
;
1065 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
1066 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
1067 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
1069 R600_STATECHANGE(context
, vpt
);
1071 r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
1072 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
1074 r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
1075 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
1077 r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
1078 r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
1080 r700
->viewport
[id
].enabled
= GL_TRUE
;
1082 r700SetScissor(context
);
1086 static void r700Viewport(GLcontext
* ctx
,
1090 GLsizei height
) //--------------------
1092 r700UpdateWindow(ctx
, 0);
1094 radeon_viewport(ctx
, x
, y
, width
, height
);
1097 static void r700DepthRange(GLcontext
* ctx
, GLclampd nearval
, GLclampd farval
) //-------------
1099 r700UpdateWindow(ctx
, 0);
1102 static void r700LineWidth(GLcontext
* ctx
, GLfloat widthf
) //---------------
1104 context_t
*context
= R700_CONTEXT(ctx
);
1105 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1106 uint32_t lineWidth
= (uint32_t)((widthf
* 0.5) * (1 << 4));
1108 R600_STATECHANGE(context
, su
);
1110 if (lineWidth
> 0xFFFF)
1112 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
,(uint16_t)lineWidth
,
1113 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1116 static void r700LineStipple(GLcontext
*ctx
, GLint factor
, GLushort pattern
)
1118 context_t
*context
= R700_CONTEXT(ctx
);
1119 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1121 R600_STATECHANGE(context
, sc
);
1123 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, pattern
, LINE_PATTERN_shift
, LINE_PATTERN_mask
);
1124 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, (factor
-1), REPEAT_COUNT_shift
, REPEAT_COUNT_mask
);
1125 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, 1, AUTO_RESET_CNTL_shift
, AUTO_RESET_CNTL_mask
);
1128 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
)
1130 context_t
*context
= R700_CONTEXT(ctx
);
1131 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1133 R600_STATECHANGE(context
, su
);
1136 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1137 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1138 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1140 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1141 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1142 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1146 static void r700PolygonOffset(GLcontext
* ctx
, GLfloat factor
, GLfloat units
) //--------------
1148 context_t
*context
= R700_CONTEXT(ctx
);
1149 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1150 GLfloat constant
= units
;
1153 R600_STATECHANGE(context
, poly
);
1155 switch (ctx
->Visual
.depthBits
) {
1167 SETfield(r700
->PA_SU_POLY_OFFSET_DB_FMT_CNTL
.u32All
, depth
,
1168 POLY_OFFSET_NEG_NUM_DB_BITS_shift
, POLY_OFFSET_NEG_NUM_DB_BITS_mask
);
1169 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1170 r700
->PA_SU_POLY_OFFSET_FRONT_SCALE
.f32All
= factor
;
1171 r700
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.f32All
= constant
;
1172 r700
->PA_SU_POLY_OFFSET_BACK_SCALE
.f32All
= factor
;
1173 r700
->PA_SU_POLY_OFFSET_BACK_OFFSET
.f32All
= constant
;
1176 static void r700UpdatePolygonMode(GLcontext
* ctx
)
1178 context_t
*context
= R700_CONTEXT(ctx
);
1179 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1181 R600_STATECHANGE(context
, su
);
1183 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DISABLE_POLY_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1185 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1186 if (ctx
->Polygon
.FrontMode
!= GL_FILL
||
1187 ctx
->Polygon
.BackMode
!= GL_FILL
) {
1190 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1191 * correctly by selecting the correct front and back face
1193 if (ctx
->Polygon
.FrontFace
== GL_CCW
) {
1194 f
= ctx
->Polygon
.FrontMode
;
1195 b
= ctx
->Polygon
.BackMode
;
1197 f
= ctx
->Polygon
.BackMode
;
1198 b
= ctx
->Polygon
.FrontMode
;
1201 /* Enable polygon mode */
1202 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DUAL_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1206 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1207 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1210 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1211 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1214 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1215 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1221 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1222 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1225 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1226 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1229 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1230 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1236 static void r700PolygonMode(GLcontext
* ctx
, GLenum face
, GLenum mode
) //------------------
1241 r700UpdatePolygonMode(ctx
);
1244 static void r700RenderMode(GLcontext
* ctx
, GLenum mode
) //---------------------
1248 static void r700ClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1250 context_t
*context
= R700_CONTEXT(ctx
);
1251 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1255 p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1256 ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1258 R600_STATECHANGE(context
, ucp
);
1260 r700
->ucp
[p
].PA_CL_UCP_0_X
.u32All
= ip
[0];
1261 r700
->ucp
[p
].PA_CL_UCP_0_Y
.u32All
= ip
[1];
1262 r700
->ucp
[p
].PA_CL_UCP_0_Z
.u32All
= ip
[2];
1263 r700
->ucp
[p
].PA_CL_UCP_0_W
.u32All
= ip
[3];
1266 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
)
1268 context_t
*context
= R700_CONTEXT(ctx
);
1269 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1272 p
= cap
- GL_CLIP_PLANE0
;
1274 R600_STATECHANGE(context
, cl
);
1277 r700
->PA_CL_CLIP_CNTL
.u32All
|= (UCP_ENA_0_bit
<< p
);
1278 r700
->ucp
[p
].enabled
= GL_TRUE
;
1279 r700ClipPlane(ctx
, cap
, NULL
);
1281 r700
->PA_CL_CLIP_CNTL
.u32All
&= ~(UCP_ENA_0_bit
<< p
);
1282 r700
->ucp
[p
].enabled
= GL_FALSE
;
1286 void r700SetScissor(context_t
*context
) //---------------
1288 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1289 unsigned x1
, y1
, x2
, y2
;
1291 struct radeon_renderbuffer
*rrb
;
1293 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1294 if (!rrb
|| !rrb
->bo
) {
1297 if (context
->radeon
.state
.scissor
.enabled
) {
1298 /* r600 has exclusive scissors */
1299 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
1300 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
1301 x2
= context
->radeon
.state
.scissor
.rect
.x2
+ 1;
1302 y2
= context
->radeon
.state
.scissor
.rect
.y2
+ 1;
1304 if (context
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
1307 x2
= rrb
->base
.Width
;
1308 y2
= rrb
->base
.Height
;
1312 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
1313 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
1317 R600_STATECHANGE(context
, scissor
);
1320 SETbit(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1321 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, x1
,
1322 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask
);
1323 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, y1
,
1324 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask
);
1326 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, x2
,
1327 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
1328 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, y2
,
1329 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
1332 SETbit(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1333 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
1334 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
1335 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
1336 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
1338 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
1339 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
1340 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
1341 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
1344 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
1345 PA_SC_CLIPRECT_0_TL__TL_X_shift
, PA_SC_CLIPRECT_0_TL__TL_X_mask
);
1346 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
1347 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
1348 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
1349 PA_SC_CLIPRECT_0_BR__BR_X_shift
, PA_SC_CLIPRECT_0_BR__BR_X_mask
);
1350 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
1351 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
1353 r700
->PA_SC_CLIPRECT_1_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1354 r700
->PA_SC_CLIPRECT_1_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1355 r700
->PA_SC_CLIPRECT_2_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1356 r700
->PA_SC_CLIPRECT_2_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1357 r700
->PA_SC_CLIPRECT_3_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1358 r700
->PA_SC_CLIPRECT_3_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1360 /* more....2d clip */
1361 SETbit(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1362 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
1363 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
1364 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
1365 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
1366 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
1367 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
1368 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
1369 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
1371 SETbit(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1372 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
1373 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
1374 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
1375 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
1376 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
1377 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
1378 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
1379 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
1381 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.u32All
= 0;
1382 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.u32All
= 0x3F800000;
1383 r700
->viewport
[id
].enabled
= GL_TRUE
;
1386 static void r700InitSQConfig(GLcontext
* ctx
)
1388 context_t
*context
= R700_CONTEXT(ctx
);
1389 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1403 int num_ps_stack_entries
;
1404 int num_vs_stack_entries
;
1405 int num_gs_stack_entries
;
1406 int num_es_stack_entries
;
1408 R600_STATECHANGE(context
, sq
);
1415 switch (context
->radeon
.radeonScreen
->chip_family
) {
1416 case CHIP_FAMILY_R600
:
1422 num_ps_threads
= 136;
1423 num_vs_threads
= 48;
1426 num_ps_stack_entries
= 128;
1427 num_vs_stack_entries
= 128;
1428 num_gs_stack_entries
= 0;
1429 num_es_stack_entries
= 0;
1431 case CHIP_FAMILY_RV630
:
1432 case CHIP_FAMILY_RV635
:
1438 num_ps_threads
= 144;
1439 num_vs_threads
= 40;
1442 num_ps_stack_entries
= 40;
1443 num_vs_stack_entries
= 40;
1444 num_gs_stack_entries
= 32;
1445 num_es_stack_entries
= 16;
1447 case CHIP_FAMILY_RV610
:
1448 case CHIP_FAMILY_RV620
:
1449 case CHIP_FAMILY_RS780
:
1450 case CHIP_FAMILY_RS880
:
1457 num_ps_threads
= 136;
1458 num_vs_threads
= 48;
1461 num_ps_stack_entries
= 40;
1462 num_vs_stack_entries
= 40;
1463 num_gs_stack_entries
= 32;
1464 num_es_stack_entries
= 16;
1466 case CHIP_FAMILY_RV670
:
1472 num_ps_threads
= 136;
1473 num_vs_threads
= 48;
1476 num_ps_stack_entries
= 40;
1477 num_vs_stack_entries
= 40;
1478 num_gs_stack_entries
= 32;
1479 num_es_stack_entries
= 16;
1481 case CHIP_FAMILY_RV770
:
1487 num_ps_threads
= 188;
1488 num_vs_threads
= 60;
1491 num_ps_stack_entries
= 256;
1492 num_vs_stack_entries
= 256;
1493 num_gs_stack_entries
= 0;
1494 num_es_stack_entries
= 0;
1496 case CHIP_FAMILY_RV730
:
1497 case CHIP_FAMILY_RV740
:
1503 num_ps_threads
= 188;
1504 num_vs_threads
= 60;
1507 num_ps_stack_entries
= 128;
1508 num_vs_stack_entries
= 128;
1509 num_gs_stack_entries
= 0;
1510 num_es_stack_entries
= 0;
1512 case CHIP_FAMILY_RV710
:
1518 num_ps_threads
= 144;
1519 num_vs_threads
= 48;
1522 num_ps_stack_entries
= 128;
1523 num_vs_stack_entries
= 128;
1524 num_gs_stack_entries
= 0;
1525 num_es_stack_entries
= 0;
1529 r700
->sq_config
.SQ_CONFIG
.u32All
= 0;
1530 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1531 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1532 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1533 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
1534 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1535 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1537 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1538 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
1539 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, ALU_INST_PREFER_VECTOR_bit
);
1540 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1541 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1542 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1543 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1545 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
1546 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1547 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1548 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_temp_gprs
,
1549 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1551 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
1552 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1553 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1555 r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
1556 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_ps_threads
,
1557 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1558 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_vs_threads
,
1559 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1560 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_gs_threads
,
1561 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1562 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_es_threads
,
1563 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1565 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
1566 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_ps_stack_entries
,
1567 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1568 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_vs_stack_entries
,
1569 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1571 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
1572 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_gs_stack_entries
,
1573 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1574 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_es_stack_entries
,
1575 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1580 * Calculate initial hardware state and register state functions.
1581 * Assumes that the command buffer and state atoms have been
1582 * initialized already.
1584 void r700InitState(GLcontext
* ctx
) //-------------------
1586 context_t
*context
= R700_CONTEXT(ctx
);
1587 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1590 radeon_firevertices(&context
->radeon
);
1592 r700
->TA_CNTL_AUX
.u32All
= 0;
1593 SETfield(r700
->TA_CNTL_AUX
.u32All
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1594 r700
->VC_ENHANCE
.u32All
= 0;
1595 r700
->DB_WATERMARKS
.u32All
= 0;
1596 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1597 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1598 SETfield(r700
->DB_WATERMARKS
.u32All
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1599 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1600 r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1601 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1602 SETfield(r700
->TA_CNTL_AUX
.u32All
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1603 r700
->DB_DEBUG
.u32All
= 0x82000000;
1604 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1606 SETfield(r700
->TA_CNTL_AUX
.u32All
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1607 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1608 SETbit(r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
, VS_PC_LIMIT_ENABLE_bit
);
1611 /* Turn off vgt reuse */
1612 r700
->VGT_REUSE_OFF
.u32All
= 0;
1613 SETbit(r700
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1615 /* Specify offsetting and clamp values for vertices */
1616 r700
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1617 r700
->VGT_MIN_VTX_INDX
.u32All
= 0;
1618 r700
->VGT_INDX_OFFSET
.u32All
= 0;
1620 /* default shader connections. */
1621 r700
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1622 r700
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1623 r700
->SPI_VS_OUT_ID_2
.u32All
= 0x0b0a0908;
1624 r700
->SPI_VS_OUT_ID_3
.u32All
= 0x0f0e0d0c;
1626 r700
->SPI_THREAD_GROUPING
.u32All
= 0;
1627 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
1628 SETfield(r700
->SPI_THREAD_GROUPING
.u32All
, 1, PS_GROUPING_shift
, PS_GROUPING_mask
);
1630 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1631 r700
->PA_SC_CLIPRECT_RULE
.u32All
= 0;
1632 SETfield(r700
->PA_SC_CLIPRECT_RULE
.u32All
, CLIP_RULE_mask
, CLIP_RULE_shift
, CLIP_RULE_mask
);
1634 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1635 r700
->PA_SC_EDGERULE
.u32All
= 0;
1637 r700
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1639 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1640 r700
->PA_SC_MODE_CNTL
.u32All
= 0;
1641 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, WALK_ORDER_ENABLE_bit
);
1642 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1644 r700
->PA_SC_MODE_CNTL
.u32All
= 0x00500000;
1645 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_REZ_ENABLE_bit
);
1646 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1649 /* Do scale XY and Z by 1/W0. */
1650 r700
->bEnablePerspective
= GL_TRUE
;
1651 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1652 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1653 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1655 /* Enable viewport scaling for all three axis */
1656 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1657 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1658 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1659 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1660 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1661 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1663 /* GL uses last vtx for flat shading components */
1664 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
1666 /* Set up vertex control */
1667 r700
->PA_SU_VTX_CNTL
.u32All
= 0;
1668 CLEARfield(r700
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1669 SETbit(r700
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1670 SETfield(r700
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1671 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1673 /* to 1.0 = no guard band */
1674 r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; /* 1.0 */
1675 r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000;
1676 r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000;
1677 r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000;
1679 /* Enable all samples for multi-sample anti-aliasing */
1680 r700
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1682 r700
->PA_SC_AA_CONFIG
.u32All
= 0;
1684 r700
->SX_MISC
.u32All
= 0;
1686 r700InitSQConfig(ctx
);
1689 ctx
->Color
.ColorMask
[RCOMP
],
1690 ctx
->Color
.ColorMask
[GCOMP
],
1691 ctx
->Color
.ColorMask
[BCOMP
],
1692 ctx
->Color
.ColorMask
[ACOMP
]);
1694 r700Enable(ctx
, GL_DEPTH_TEST
, ctx
->Depth
.Test
);
1695 r700DepthMask(ctx
, ctx
->Depth
.Mask
);
1696 r700DepthFunc(ctx
, ctx
->Depth
.Func
);
1697 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, DUAL_EXPORT_ENABLE_bit
);
1699 r700
->DB_DEPTH_CLEAR
.u32All
= 0x3F800000;
1701 r700
->DB_RENDER_CONTROL
.u32All
= 0;
1702 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, STENCIL_COMPRESS_DISABLE_bit
);
1703 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, DEPTH_COMPRESS_DISABLE_bit
);
1704 r700
->DB_RENDER_OVERRIDE
.u32All
= 0;
1705 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1706 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_SHADER_Z_ORDER_bit
);
1707 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
1708 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
1709 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
1711 r700
->DB_ALPHA_TO_MASK
.u32All
= 0;
1712 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET0_shift
, ALPHA_TO_MASK_OFFSET0_mask
);
1713 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET1_shift
, ALPHA_TO_MASK_OFFSET1_mask
);
1714 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET2_shift
, ALPHA_TO_MASK_OFFSET2_mask
);
1715 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET3_shift
, ALPHA_TO_MASK_OFFSET3_mask
);
1718 r700Enable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
._Enabled
);
1719 r700StencilMaskSeparate(ctx
, 0, ctx
->Stencil
.WriteMask
[0]);
1720 r700StencilFuncSeparate(ctx
, 0, ctx
->Stencil
.Function
[0],
1721 ctx
->Stencil
.Ref
[0], ctx
->Stencil
.ValueMask
[0]);
1722 r700StencilOpSeparate(ctx
, 0, ctx
->Stencil
.FailFunc
[0],
1723 ctx
->Stencil
.ZFailFunc
[0],
1724 ctx
->Stencil
.ZPassFunc
[0]);
1726 r700UpdateCulling(ctx
);
1728 r700SetBlendState(ctx
);
1729 r700SetLogicOpState(ctx
);
1731 r700AlphaFunc(ctx
, ctx
->Color
.AlphaFunc
, ctx
->Color
.AlphaRef
);
1732 r700Enable(ctx
, GL_ALPHA_TEST
, ctx
->Color
.AlphaEnabled
);
1734 r700PointSize(ctx
, 1.0);
1736 CLEARfield(r700
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1737 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1739 r700LineWidth(ctx
, 1.0);
1741 r700
->PA_SC_LINE_CNTL
.u32All
= 0;
1742 CLEARbit(r700
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1743 SETbit(r700
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1745 r700ShadeModel(ctx
, ctx
->Light
.ShadeModel
);
1746 r700PolygonMode(ctx
, GL_FRONT
, ctx
->Polygon
.FrontMode
);
1747 r700PolygonMode(ctx
, GL_BACK
, ctx
->Polygon
.BackMode
);
1748 r700PolygonOffset(ctx
, ctx
->Polygon
.OffsetFactor
,
1749 ctx
->Polygon
.OffsetUnits
);
1750 r700Enable(ctx
, GL_POLYGON_OFFSET_POINT
, ctx
->Polygon
.OffsetPoint
);
1751 r700Enable(ctx
, GL_POLYGON_OFFSET_LINE
, ctx
->Polygon
.OffsetLine
);
1752 r700Enable(ctx
, GL_POLYGON_OFFSET_FILL
, ctx
->Polygon
.OffsetFill
);
1755 r700BlendColor(ctx
, ctx
->Color
.BlendColor
);
1757 r700
->CB_CLEAR_RED_R6XX
.f32All
= 1.0; //r6xx only
1758 r700
->CB_CLEAR_GREEN_R6XX
.f32All
= 0.0; //r6xx only
1759 r700
->CB_CLEAR_BLUE_R6XX
.f32All
= 1.0; //r6xx only
1760 r700
->CB_CLEAR_ALPHA_R6XX
.f32All
= 1.0; //r6xx only
1761 r700
->CB_FOG_RED_R6XX
.u32All
= 0; //r6xx only
1762 r700
->CB_FOG_GREEN_R6XX
.u32All
= 0; //r6xx only
1763 r700
->CB_FOG_BLUE_R6XX
.u32All
= 0; //r6xx only
1765 /* Disable color compares */
1766 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1767 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1768 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1769 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1770 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1771 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1773 /* Zero out source */
1774 r700
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1776 /* Put a compare color in for error checking */
1777 r700
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1779 /* Set up color compare mask */
1780 r700
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1782 /* screen/window/view */
1783 SETfield(r700
->CB_SHADER_MASK
.u32All
, 0xF, (4 * id
), OUTPUT0_ENABLE_mask
);
1785 context
->radeon
.hw
.all_dirty
= GL_TRUE
;
1789 void r700InitStateFuncs(struct dd_function_table
*functions
) //-----------------
1791 functions
->UpdateState
= r700InvalidateState
;
1792 functions
->AlphaFunc
= r700AlphaFunc
;
1793 functions
->BlendColor
= r700BlendColor
;
1794 functions
->BlendEquationSeparate
= r700BlendEquationSeparate
;
1795 functions
->BlendFuncSeparate
= r700BlendFuncSeparate
;
1796 functions
->Enable
= r700Enable
;
1797 functions
->ColorMask
= r700ColorMask
;
1798 functions
->DepthFunc
= r700DepthFunc
;
1799 functions
->DepthMask
= r700DepthMask
;
1800 functions
->CullFace
= r700CullFace
;
1801 functions
->Fogfv
= r700Fogfv
;
1802 functions
->FrontFace
= r700FrontFace
;
1803 functions
->ShadeModel
= r700ShadeModel
;
1804 functions
->LogicOpcode
= r700LogicOpcode
;
1806 /* ARB_point_parameters */
1807 functions
->PointParameterfv
= r700PointParameter
;
1809 /* Stencil related */
1810 functions
->StencilFuncSeparate
= r700StencilFuncSeparate
;
1811 functions
->StencilMaskSeparate
= r700StencilMaskSeparate
;
1812 functions
->StencilOpSeparate
= r700StencilOpSeparate
;
1814 /* Viewport related */
1815 functions
->Viewport
= r700Viewport
;
1816 functions
->DepthRange
= r700DepthRange
;
1817 functions
->PointSize
= r700PointSize
;
1818 functions
->LineWidth
= r700LineWidth
;
1819 functions
->LineStipple
= r700LineStipple
;
1821 functions
->PolygonOffset
= r700PolygonOffset
;
1822 functions
->PolygonMode
= r700PolygonMode
;
1824 functions
->RenderMode
= r700RenderMode
;
1826 functions
->ClipPlane
= r700ClipPlane
;
1828 functions
->Scissor
= radeonScissor
;
1830 functions
->DrawBuffer
= radeonDrawBuffer
;
1831 functions
->ReadBuffer
= radeonReadBuffer
;