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Merge branch 'mesa_7_6_branch' into mesa_7_7_branch
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49
50 #include "r600_context.h"
51
52 #include "r700_state.h"
53
54 #include "r700_fragprog.h"
55 #include "r700_vertprog.h"
56
57 void r600UpdateTextureState(GLcontext * ctx);
58 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
59 static void r700UpdatePolygonMode(GLcontext * ctx);
60 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
61 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
62
63 void r700UpdateShaders(GLcontext * ctx)
64 {
65 context_t *context = R700_CONTEXT(ctx);
66
67 /* should only happenen once, just after context is created */
68 /* TODO: shouldn't we fallback to sw here? */
69 if (!ctx->FragmentProgram._Current) {
70 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
71 return;
72 }
73
74 r700SelectFragmentShader(ctx);
75
76 r700SelectVertexShader(ctx);
77 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
78 context->radeon.NewGLState = 0;
79 }
80
81 /*
82 * To correctly position primitives:
83 */
84 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
85 {
86 context_t *context = R700_CONTEXT(ctx);
87 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
88 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
89 GLfloat xoffset = (GLfloat) dPriv->x;
90 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
91 const GLfloat *v = ctx->Viewport._WindowMap.m;
92 int id = 0;
93
94 GLfloat tx = v[MAT_TX] + xoffset;
95 GLfloat ty = (-v[MAT_TY]) + yoffset;
96
97 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
98 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
99 /* Note: this should also modify whatever data the context reset
100 * code uses...
101 */
102 R600_STATECHANGE(context, vpt);
103 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
104 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
105 }
106
107 radeonUpdateScissor(ctx);
108 }
109
110 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
111 {
112 struct r700_fragment_program *fp =
113 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
114 struct gl_program_parameter_list *paramList;
115
116 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
117 return;
118
119 if (!ctx->FragmentProgram._Current || !fp)
120 return;
121
122 paramList = ctx->FragmentProgram._Current->Base.Parameters;
123
124 if (!paramList)
125 return;
126
127 _mesa_load_state_parameters(ctx, paramList);
128
129 }
130
131 /**
132 * Called by Mesa after an internal state update.
133 */
134 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
135 {
136 context_t *context = R700_CONTEXT(ctx);
137
138 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
139
140 _swrast_InvalidateState(ctx, new_state);
141 _swsetup_InvalidateState(ctx, new_state);
142 _vbo_InvalidateState(ctx, new_state);
143 _tnl_InvalidateState(ctx, new_state);
144 _ae_invalidate_state(ctx, new_state);
145
146 if (new_state & _NEW_BUFFERS) {
147 _mesa_update_framebuffer(ctx);
148 /* this updates the DrawBuffer's Width/Height if it's a FBO */
149 _mesa_update_draw_buffer_bounds(ctx);
150
151 R600_STATECHANGE(context, cb_target);
152 R600_STATECHANGE(context, db_target);
153 }
154
155 if (new_state & (_NEW_LIGHT)) {
156 R600_STATECHANGE(context, su);
157 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
158 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
159 else
160 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
161 }
162
163 r700UpdateStateParameters(ctx, new_state);
164
165 R600_STATECHANGE(context, cl);
166 R600_STATECHANGE(context, spi);
167
168 if(GL_TRUE == r700->bEnablePerspective)
169 {
170 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
171 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
172 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
173
174 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
175
176 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
177 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
178 }
179 else
180 {
181 /* For orthogonal case. */
182 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
183 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
184
185 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
186
187 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
188 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
189 }
190
191 context->radeon.NewGLState |= new_state;
192 }
193
194 static void r700SetDBRenderState(GLcontext * ctx)
195 {
196 context_t *context = R700_CONTEXT(ctx);
197 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
198 struct r700_fragment_program *fp = (struct r700_fragment_program *)
199 (ctx->FragmentProgram._Current);
200
201 R600_STATECHANGE(context, db);
202
203 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
204 SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask);
205 /* XXX need to enable htile for hiz/s */
206 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
207 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
208 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
209
210 if (context->radeon.query.current)
211 {
212 SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
213 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
214 {
215 SETbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
216 }
217 }
218 else
219 {
220 CLEARbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
221 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
222 {
223 CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
224 }
225 }
226
227 if (fp)
228 {
229 if (fp->r700Shader.killIsUsed)
230 {
231 SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
232 }
233 else
234 {
235 CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
236 }
237
238 if (fp->r700Shader.depthIsExported)
239 {
240 SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
241 }
242 else
243 {
244 CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
245 }
246 }
247 }
248
249 void r700UpdateShaderStates(GLcontext * ctx)
250 {
251 r700SetDBRenderState(ctx);
252 r600UpdateTextureState(ctx);
253 }
254
255 static void r700SetDepthState(GLcontext * ctx)
256 {
257 context_t *context = R700_CONTEXT(ctx);
258 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
259
260 R600_STATECHANGE(context, db);
261
262 if (ctx->Depth.Test)
263 {
264 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
265 if (ctx->Depth.Mask)
266 {
267 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
268 }
269 else
270 {
271 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
272 }
273
274 switch (ctx->Depth.Func)
275 {
276 case GL_NEVER:
277 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
278 ZFUNC_shift, ZFUNC_mask);
279 break;
280 case GL_LESS:
281 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
282 ZFUNC_shift, ZFUNC_mask);
283 break;
284 case GL_EQUAL:
285 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
286 ZFUNC_shift, ZFUNC_mask);
287 break;
288 case GL_LEQUAL:
289 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
290 ZFUNC_shift, ZFUNC_mask);
291 break;
292 case GL_GREATER:
293 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
294 ZFUNC_shift, ZFUNC_mask);
295 break;
296 case GL_NOTEQUAL:
297 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
298 ZFUNC_shift, ZFUNC_mask);
299 break;
300 case GL_GEQUAL:
301 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
302 ZFUNC_shift, ZFUNC_mask);
303 break;
304 case GL_ALWAYS:
305 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
306 ZFUNC_shift, ZFUNC_mask);
307 break;
308 default:
309 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
310 ZFUNC_shift, ZFUNC_mask);
311 break;
312 }
313 }
314 else
315 {
316 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
317 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
318 }
319 }
320
321 static void r700SetAlphaState(GLcontext * ctx)
322 {
323 context_t *context = R700_CONTEXT(ctx);
324 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
325 uint32_t alpha_func = REF_ALWAYS;
326 GLboolean really_enabled = ctx->Color.AlphaEnabled;
327
328 R600_STATECHANGE(context, sx);
329
330 switch (ctx->Color.AlphaFunc) {
331 case GL_NEVER:
332 alpha_func = REF_NEVER;
333 break;
334 case GL_LESS:
335 alpha_func = REF_LESS;
336 break;
337 case GL_EQUAL:
338 alpha_func = REF_EQUAL;
339 break;
340 case GL_LEQUAL:
341 alpha_func = REF_LEQUAL;
342 break;
343 case GL_GREATER:
344 alpha_func = REF_GREATER;
345 break;
346 case GL_NOTEQUAL:
347 alpha_func = REF_NOTEQUAL;
348 break;
349 case GL_GEQUAL:
350 alpha_func = REF_GEQUAL;
351 break;
352 case GL_ALWAYS:
353 /*alpha_func = REF_ALWAYS; */
354 really_enabled = GL_FALSE;
355 break;
356 }
357
358 if (really_enabled) {
359 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
360 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
361 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
362 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
363 } else {
364 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
365 }
366
367 }
368
369 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
370 {
371 (void)func;
372 (void)ref;
373 r700SetAlphaState(ctx);
374 }
375
376
377 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
378 {
379 context_t *context = R700_CONTEXT(ctx);
380 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
381
382 R600_STATECHANGE(context, blnd_clr);
383
384 r700->CB_BLEND_RED.f32All = cf[0];
385 r700->CB_BLEND_GREEN.f32All = cf[1];
386 r700->CB_BLEND_BLUE.f32All = cf[2];
387 r700->CB_BLEND_ALPHA.f32All = cf[3];
388 }
389
390 static int blend_factor(GLenum factor, GLboolean is_src)
391 {
392 switch (factor) {
393 case GL_ZERO:
394 return BLEND_ZERO;
395 break;
396 case GL_ONE:
397 return BLEND_ONE;
398 break;
399 case GL_DST_COLOR:
400 return BLEND_DST_COLOR;
401 break;
402 case GL_ONE_MINUS_DST_COLOR:
403 return BLEND_ONE_MINUS_DST_COLOR;
404 break;
405 case GL_SRC_COLOR:
406 return BLEND_SRC_COLOR;
407 break;
408 case GL_ONE_MINUS_SRC_COLOR:
409 return BLEND_ONE_MINUS_SRC_COLOR;
410 break;
411 case GL_SRC_ALPHA:
412 return BLEND_SRC_ALPHA;
413 break;
414 case GL_ONE_MINUS_SRC_ALPHA:
415 return BLEND_ONE_MINUS_SRC_ALPHA;
416 break;
417 case GL_DST_ALPHA:
418 return BLEND_DST_ALPHA;
419 break;
420 case GL_ONE_MINUS_DST_ALPHA:
421 return BLEND_ONE_MINUS_DST_ALPHA;
422 break;
423 case GL_SRC_ALPHA_SATURATE:
424 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
425 break;
426 case GL_CONSTANT_COLOR:
427 return BLEND_CONSTANT_COLOR;
428 break;
429 case GL_ONE_MINUS_CONSTANT_COLOR:
430 return BLEND_ONE_MINUS_CONSTANT_COLOR;
431 break;
432 case GL_CONSTANT_ALPHA:
433 return BLEND_CONSTANT_ALPHA;
434 break;
435 case GL_ONE_MINUS_CONSTANT_ALPHA:
436 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
437 break;
438 default:
439 fprintf(stderr, "unknown blend factor %x\n", factor);
440 return (is_src) ? BLEND_ONE : BLEND_ZERO;
441 break;
442 }
443 }
444
445 static void r700SetBlendState(GLcontext * ctx)
446 {
447 context_t *context = R700_CONTEXT(ctx);
448 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
449 int id = 0;
450 uint32_t blend_reg = 0, eqn, eqnA;
451
452 R600_STATECHANGE(context, blnd);
453
454 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
455 SETfield(blend_reg,
456 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
457 SETfield(blend_reg,
458 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
459 SETfield(blend_reg,
460 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
461 SETfield(blend_reg,
462 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
463 SETfield(blend_reg,
464 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
465 SETfield(blend_reg,
466 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
467 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
468 r700->CB_BLEND_CONTROL.u32All = blend_reg;
469 else
470 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
471 return;
472 }
473
474 SETfield(blend_reg,
475 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
476 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
477 SETfield(blend_reg,
478 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
479 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
480
481 switch (ctx->Color.BlendEquationRGB) {
482 case GL_FUNC_ADD:
483 eqn = COMB_DST_PLUS_SRC;
484 break;
485 case GL_FUNC_SUBTRACT:
486 eqn = COMB_SRC_MINUS_DST;
487 break;
488 case GL_FUNC_REVERSE_SUBTRACT:
489 eqn = COMB_DST_MINUS_SRC;
490 break;
491 case GL_MIN:
492 eqn = COMB_MIN_DST_SRC;
493 SETfield(blend_reg,
494 BLEND_ONE,
495 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
496 SETfield(blend_reg,
497 BLEND_ONE,
498 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
499 break;
500 case GL_MAX:
501 eqn = COMB_MAX_DST_SRC;
502 SETfield(blend_reg,
503 BLEND_ONE,
504 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
505 SETfield(blend_reg,
506 BLEND_ONE,
507 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
508 break;
509
510 default:
511 fprintf(stderr,
512 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
513 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
514 return;
515 }
516 SETfield(blend_reg,
517 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
518
519 SETfield(blend_reg,
520 blend_factor(ctx->Color.BlendSrcA, GL_TRUE),
521 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
522 SETfield(blend_reg,
523 blend_factor(ctx->Color.BlendDstA, GL_FALSE),
524 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
525
526 switch (ctx->Color.BlendEquationA) {
527 case GL_FUNC_ADD:
528 eqnA = COMB_DST_PLUS_SRC;
529 break;
530 case GL_FUNC_SUBTRACT:
531 eqnA = COMB_SRC_MINUS_DST;
532 break;
533 case GL_FUNC_REVERSE_SUBTRACT:
534 eqnA = COMB_DST_MINUS_SRC;
535 break;
536 case GL_MIN:
537 eqnA = COMB_MIN_DST_SRC;
538 SETfield(blend_reg,
539 BLEND_ONE,
540 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
541 SETfield(blend_reg,
542 BLEND_ONE,
543 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
544 break;
545 case GL_MAX:
546 eqnA = COMB_MAX_DST_SRC;
547 SETfield(blend_reg,
548 BLEND_ONE,
549 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
550 SETfield(blend_reg,
551 BLEND_ONE,
552 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
553 break;
554 default:
555 fprintf(stderr,
556 "[%s:%u] Invalid A blend equation (0x%04x).\n",
557 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
558 return;
559 }
560
561 SETfield(blend_reg,
562 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
563
564 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
565
566 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
567 r700->CB_BLEND_CONTROL.u32All = blend_reg;
568 else {
569 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
570 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
571 }
572 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
573 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
574
575 }
576
577 static void r700BlendEquationSeparate(GLcontext * ctx,
578 GLenum modeRGB, GLenum modeA) //-----------------
579 {
580 r700SetBlendState(ctx);
581 }
582
583 static void r700BlendFuncSeparate(GLcontext * ctx,
584 GLenum sfactorRGB, GLenum dfactorRGB,
585 GLenum sfactorA, GLenum dfactorA) //------------------------
586 {
587 r700SetBlendState(ctx);
588 }
589
590 /**
591 * Translate LogicOp enums into hardware representation.
592 */
593 static GLuint translate_logicop(GLenum logicop)
594 {
595 switch (logicop) {
596 case GL_CLEAR:
597 return 0x00;
598 case GL_SET:
599 return 0xff;
600 case GL_COPY:
601 return 0xcc;
602 case GL_COPY_INVERTED:
603 return 0x33;
604 case GL_NOOP:
605 return 0xaa;
606 case GL_INVERT:
607 return 0x55;
608 case GL_AND:
609 return 0x88;
610 case GL_NAND:
611 return 0x77;
612 case GL_OR:
613 return 0xee;
614 case GL_NOR:
615 return 0x11;
616 case GL_XOR:
617 return 0x66;
618 case GL_EQUIV:
619 return 0xaa;
620 case GL_AND_REVERSE:
621 return 0x44;
622 case GL_AND_INVERTED:
623 return 0x22;
624 case GL_OR_REVERSE:
625 return 0xdd;
626 case GL_OR_INVERTED:
627 return 0xbb;
628 default:
629 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
630 return 0xcc;
631 }
632 }
633
634 /**
635 * Used internally to update the r300->hw hardware state to match the
636 * current OpenGL state.
637 */
638 static void r700SetLogicOpState(GLcontext *ctx)
639 {
640 context_t *context = R700_CONTEXT(ctx);
641 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
642
643 R600_STATECHANGE(context, blnd);
644
645 if (RGBA_LOGICOP_ENABLED(ctx))
646 SETfield(r700->CB_COLOR_CONTROL.u32All,
647 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
648 else
649 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
650 }
651
652 /**
653 * Called by Mesa when an application program changes the LogicOp state
654 * via glLogicOp.
655 */
656 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
657 {
658 if (RGBA_LOGICOP_ENABLED(ctx))
659 r700SetLogicOpState(ctx);
660 }
661
662 static void r700UpdateCulling(GLcontext * ctx)
663 {
664 context_t *context = R700_CONTEXT(ctx);
665 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
666
667 R600_STATECHANGE(context, su);
668
669 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
670 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
671 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
672
673 if (ctx->Polygon.CullFlag)
674 {
675 switch (ctx->Polygon.CullFaceMode)
676 {
677 case GL_FRONT:
678 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
679 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
680 break;
681 case GL_BACK:
682 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
683 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
684 break;
685 case GL_FRONT_AND_BACK:
686 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
687 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
688 break;
689 default:
690 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
691 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
692 break;
693 }
694 }
695
696 switch (ctx->Polygon.FrontFace)
697 {
698 case GL_CW:
699 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
700 break;
701 case GL_CCW:
702 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
703 break;
704 default:
705 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
706 break;
707 }
708 }
709
710 static void r700UpdateLineStipple(GLcontext * ctx)
711 {
712 context_t *context = R700_CONTEXT(ctx);
713 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
714
715 R600_STATECHANGE(context, sc);
716
717 if (ctx->Line.StippleFlag)
718 {
719 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
720 }
721 else
722 {
723 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
724 }
725 }
726
727 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
728 {
729 context_t *context = R700_CONTEXT(ctx);
730
731 switch (cap) {
732 case GL_TEXTURE_1D:
733 case GL_TEXTURE_2D:
734 case GL_TEXTURE_3D:
735 /* empty */
736 break;
737 case GL_FOG:
738 /* empty */
739 break;
740 case GL_ALPHA_TEST:
741 r700SetAlphaState(ctx);
742 break;
743 case GL_COLOR_LOGIC_OP:
744 r700SetLogicOpState(ctx);
745 /* fall-through, because logic op overrides blending */
746 case GL_BLEND:
747 r700SetBlendState(ctx);
748 break;
749 case GL_CLIP_PLANE0:
750 case GL_CLIP_PLANE1:
751 case GL_CLIP_PLANE2:
752 case GL_CLIP_PLANE3:
753 case GL_CLIP_PLANE4:
754 case GL_CLIP_PLANE5:
755 r700SetClipPlaneState(ctx, cap, state);
756 break;
757 case GL_DEPTH_TEST:
758 r700SetDepthState(ctx);
759 break;
760 case GL_STENCIL_TEST:
761 r700SetStencilState(ctx, state);
762 break;
763 case GL_CULL_FACE:
764 r700UpdateCulling(ctx);
765 break;
766 case GL_POLYGON_OFFSET_POINT:
767 case GL_POLYGON_OFFSET_LINE:
768 case GL_POLYGON_OFFSET_FILL:
769 r700SetPolygonOffsetState(ctx, state);
770 break;
771 case GL_SCISSOR_TEST:
772 radeon_firevertices(&context->radeon);
773 context->radeon.state.scissor.enabled = state;
774 radeonUpdateScissor(ctx);
775 break;
776 case GL_LINE_STIPPLE:
777 r700UpdateLineStipple(ctx);
778 break;
779 default:
780 break;
781 }
782
783 }
784
785 /**
786 * Handle glColorMask()
787 */
788 static void r700ColorMask(GLcontext * ctx,
789 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
790 {
791 context_t *context = R700_CONTEXT(ctx);
792 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
793 unsigned int mask = ((r ? 1 : 0) |
794 (g ? 2 : 0) |
795 (b ? 4 : 0) |
796 (a ? 8 : 0));
797
798 if (mask != r700->CB_TARGET_MASK.u32All) {
799 R600_STATECHANGE(context, cb);
800 SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
801 }
802 }
803
804 /**
805 * Change the depth testing function.
806 *
807 * \note Mesa already filters redundant calls to this function.
808 */
809 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
810 {
811 r700SetDepthState(ctx);
812 }
813
814 /**
815 * Enable/Disable depth writing.
816 *
817 * \note Mesa already filters redundant calls to this function.
818 */
819 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
820 {
821 r700SetDepthState(ctx);
822 }
823
824 /**
825 * Change the culling mode.
826 *
827 * \note Mesa already filters redundant calls to this function.
828 */
829 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
830 {
831 r700UpdateCulling(ctx);
832 }
833
834 /* =============================================================
835 * Fog
836 */
837 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
838 {
839 }
840
841 /**
842 * Change the polygon orientation.
843 *
844 * \note Mesa already filters redundant calls to this function.
845 */
846 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
847 {
848 r700UpdateCulling(ctx);
849 r700UpdatePolygonMode(ctx);
850 }
851
852 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
853 {
854 context_t *context = R700_CONTEXT(ctx);
855 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
856
857 R600_STATECHANGE(context, spi);
858
859 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
860 switch (mode) {
861 case GL_FLAT:
862 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
863 break;
864 case GL_SMOOTH:
865 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
866 break;
867 default:
868 return;
869 }
870 }
871
872 /* =============================================================
873 * Point state
874 */
875 static void r700PointSize(GLcontext * ctx, GLfloat size)
876 {
877 context_t *context = R700_CONTEXT(ctx);
878 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
879
880 R600_STATECHANGE(context, su);
881
882 /* We need to clamp to user defined range here, because
883 * the HW clamping happens only for per vertex point size. */
884 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
885
886 /* same size limits for AA, non-AA points */
887 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
888
889 /* format is 12.4 fixed point */
890 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
891 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
892 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
893 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
894
895 }
896
897 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
898 {
899 context_t *context = R700_CONTEXT(ctx);
900 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
901
902 R600_STATECHANGE(context, su);
903
904 /* format is 12.4 fixed point */
905 switch (pname) {
906 case GL_POINT_SIZE_MIN:
907 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
908 MIN_SIZE_shift, MIN_SIZE_mask);
909 break;
910 case GL_POINT_SIZE_MAX:
911 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
912 MAX_SIZE_shift, MAX_SIZE_mask);
913 break;
914 case GL_POINT_DISTANCE_ATTENUATION:
915 break;
916 case GL_POINT_FADE_THRESHOLD_SIZE:
917 break;
918 default:
919 break;
920 }
921 }
922
923 static int translate_stencil_func(int func)
924 {
925 switch (func) {
926 case GL_NEVER:
927 return REF_NEVER;
928 case GL_LESS:
929 return REF_LESS;
930 case GL_EQUAL:
931 return REF_EQUAL;
932 case GL_LEQUAL:
933 return REF_LEQUAL;
934 case GL_GREATER:
935 return REF_GREATER;
936 case GL_NOTEQUAL:
937 return REF_NOTEQUAL;
938 case GL_GEQUAL:
939 return REF_GEQUAL;
940 case GL_ALWAYS:
941 return REF_ALWAYS;
942 }
943 return 0;
944 }
945
946 static int translate_stencil_op(int op)
947 {
948 switch (op) {
949 case GL_KEEP:
950 return STENCIL_KEEP;
951 case GL_ZERO:
952 return STENCIL_ZERO;
953 case GL_REPLACE:
954 return STENCIL_REPLACE;
955 case GL_INCR:
956 return STENCIL_INCR_CLAMP;
957 case GL_DECR:
958 return STENCIL_DECR_CLAMP;
959 case GL_INCR_WRAP_EXT:
960 return STENCIL_INCR_WRAP;
961 case GL_DECR_WRAP_EXT:
962 return STENCIL_DECR_WRAP;
963 case GL_INVERT:
964 return STENCIL_INVERT;
965 default:
966 WARN_ONCE("Do not know how to translate stencil op");
967 return STENCIL_KEEP;
968 }
969 return 0;
970 }
971
972 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
973 {
974 context_t *context = R700_CONTEXT(ctx);
975 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
976 GLboolean hw_stencil = GL_FALSE;
977
978 if (ctx->DrawBuffer) {
979 struct radeon_renderbuffer *rrbStencil
980 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
981 hw_stencil = (rrbStencil && rrbStencil->bo);
982 }
983
984 if (hw_stencil) {
985 R600_STATECHANGE(context, db);
986 if (state) {
987 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
988 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
989 } else
990 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
991 }
992 }
993
994 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
995 GLenum func, GLint ref, GLuint mask) //---------------------
996 {
997 context_t *context = R700_CONTEXT(ctx);
998 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
999 const unsigned back = ctx->Stencil._BackFace;
1000
1001 R600_STATECHANGE(context, stencil);
1002 R600_STATECHANGE(context, db);
1003
1004 //front
1005 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
1006 STENCILREF_shift, STENCILREF_mask);
1007 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
1008 STENCILMASK_shift, STENCILMASK_mask);
1009
1010 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
1011 STENCILFUNC_shift, STENCILFUNC_mask);
1012
1013 //back
1014 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
1015 STENCILREF_BF_shift, STENCILREF_BF_mask);
1016 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
1017 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1018
1019 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1020 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1021
1022 }
1023
1024 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1025 {
1026 context_t *context = R700_CONTEXT(ctx);
1027 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1028 const unsigned back = ctx->Stencil._BackFace;
1029
1030 R600_STATECHANGE(context, stencil);
1031
1032 // front
1033 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1034 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1035
1036 // back
1037 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1038 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1039
1040 }
1041
1042 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1043 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1044 {
1045 context_t *context = R700_CONTEXT(ctx);
1046 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1047 const unsigned back = ctx->Stencil._BackFace;
1048
1049 R600_STATECHANGE(context, db);
1050
1051 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1052 STENCILFAIL_shift, STENCILFAIL_mask);
1053 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1054 STENCILZFAIL_shift, STENCILZFAIL_mask);
1055 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1056 STENCILZPASS_shift, STENCILZPASS_mask);
1057
1058 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1059 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1060 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1061 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1062 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1063 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1064 }
1065
1066 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1067 {
1068 context_t *context = R700_CONTEXT(ctx);
1069 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1070 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1071 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1072 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1073 const GLfloat *v = ctx->Viewport._WindowMap.m;
1074 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1075 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1076 GLfloat y_scale, y_bias;
1077
1078 if (render_to_fbo) {
1079 y_scale = 1.0;
1080 y_bias = 0;
1081 } else {
1082 y_scale = -1.0;
1083 y_bias = yoffset;
1084 }
1085
1086 GLfloat sx = v[MAT_SX];
1087 GLfloat tx = v[MAT_TX] + xoffset;
1088 GLfloat sy = v[MAT_SY] * y_scale;
1089 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1090 GLfloat sz = v[MAT_SZ] * depthScale;
1091 GLfloat tz = v[MAT_TZ] * depthScale;
1092
1093 R600_STATECHANGE(context, vpt);
1094 R600_STATECHANGE(context, cl);
1095
1096 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1097 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1098
1099 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1100 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1101
1102 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1103 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1104
1105 if (ctx->Transform.DepthClamp) {
1106 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
1107 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
1108 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1109 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1110 } else {
1111 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0;
1112 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0;
1113 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1114 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1115 }
1116
1117 r700->viewport[id].enabled = GL_TRUE;
1118
1119 r700SetScissor(context);
1120 }
1121
1122
1123 static void r700Viewport(GLcontext * ctx,
1124 GLint x,
1125 GLint y,
1126 GLsizei width,
1127 GLsizei height) //--------------------
1128 {
1129 r700UpdateWindow(ctx, 0);
1130
1131 radeon_viewport(ctx, x, y, width, height);
1132 }
1133
1134 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1135 {
1136 r700UpdateWindow(ctx, 0);
1137 }
1138
1139 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1140 {
1141 context_t *context = R700_CONTEXT(ctx);
1142 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1143 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1144
1145 R600_STATECHANGE(context, su);
1146
1147 if (lineWidth > 0xFFFF)
1148 lineWidth = 0xFFFF;
1149 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1150 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1151 }
1152
1153 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1154 {
1155 context_t *context = R700_CONTEXT(ctx);
1156 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1157
1158 R600_STATECHANGE(context, sc);
1159
1160 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1161 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1162 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1163 }
1164
1165 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1166 {
1167 context_t *context = R700_CONTEXT(ctx);
1168 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1169
1170 R600_STATECHANGE(context, su);
1171
1172 if (state) {
1173 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1174 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1175 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1176 } else {
1177 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1178 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1179 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1180 }
1181 }
1182
1183 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1184 {
1185 context_t *context = R700_CONTEXT(ctx);
1186 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1187 GLfloat constant = units;
1188 GLchar depth = 0;
1189
1190 R600_STATECHANGE(context, poly);
1191
1192 switch (ctx->Visual.depthBits) {
1193 case 16:
1194 constant *= 4.0;
1195 depth = -16;
1196 break;
1197 case 24:
1198 constant *= 2.0;
1199 depth = -24;
1200 break;
1201 }
1202
1203 factor *= 12.0;
1204 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1205 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1206 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1207 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1208 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1209 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1210 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1211 }
1212
1213 static void r700UpdatePolygonMode(GLcontext * ctx)
1214 {
1215 context_t *context = R700_CONTEXT(ctx);
1216 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1217
1218 R600_STATECHANGE(context, su);
1219
1220 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1221
1222 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1223 if (ctx->Polygon.FrontMode != GL_FILL ||
1224 ctx->Polygon.BackMode != GL_FILL) {
1225 GLenum f, b;
1226
1227 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1228 * correctly by selecting the correct front and back face
1229 */
1230 if (ctx->Polygon.FrontFace == GL_CCW) {
1231 f = ctx->Polygon.FrontMode;
1232 b = ctx->Polygon.BackMode;
1233 } else {
1234 f = ctx->Polygon.BackMode;
1235 b = ctx->Polygon.FrontMode;
1236 }
1237
1238 /* Enable polygon mode */
1239 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1240
1241 switch (f) {
1242 case GL_LINE:
1243 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1244 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1245 break;
1246 case GL_POINT:
1247 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1248 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1249 break;
1250 case GL_FILL:
1251 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1252 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1253 break;
1254 }
1255
1256 switch (b) {
1257 case GL_LINE:
1258 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1259 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1260 break;
1261 case GL_POINT:
1262 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1263 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1264 break;
1265 case GL_FILL:
1266 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1267 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1268 break;
1269 }
1270 }
1271 }
1272
1273 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1274 {
1275 (void)face;
1276 (void)mode;
1277
1278 r700UpdatePolygonMode(ctx);
1279 }
1280
1281 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1282 {
1283 }
1284
1285 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1286 {
1287 context_t *context = R700_CONTEXT(ctx);
1288 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1289 GLint p;
1290 GLint *ip;
1291
1292 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1293 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1294
1295 R600_STATECHANGE(context, ucp);
1296
1297 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1298 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1299 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1300 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1301 }
1302
1303 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1304 {
1305 context_t *context = R700_CONTEXT(ctx);
1306 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1307 GLuint p;
1308
1309 p = cap - GL_CLIP_PLANE0;
1310
1311 R600_STATECHANGE(context, cl);
1312
1313 if (state) {
1314 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1315 r700->ucp[p].enabled = GL_TRUE;
1316 r700ClipPlane(ctx, cap, NULL);
1317 } else {
1318 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1319 r700->ucp[p].enabled = GL_FALSE;
1320 }
1321 }
1322
1323 void r700SetScissor(context_t *context) //---------------
1324 {
1325 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1326 unsigned x1, y1, x2, y2;
1327 int id = 0;
1328 struct radeon_renderbuffer *rrb;
1329
1330 rrb = radeon_get_colorbuffer(&context->radeon);
1331 if (!rrb || !rrb->bo) {
1332 return;
1333 }
1334 if (context->radeon.state.scissor.enabled) {
1335 x1 = context->radeon.state.scissor.rect.x1;
1336 y1 = context->radeon.state.scissor.rect.y1;
1337 x2 = context->radeon.state.scissor.rect.x2;
1338 y2 = context->radeon.state.scissor.rect.y2;
1339 /* r600 has exclusive BR scissors */
1340 if (context->radeon.radeonScreen->kernel_mm) {
1341 x2++;
1342 y2++;
1343 }
1344 } else {
1345 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1346 x1 = 0;
1347 y1 = 0;
1348 x2 = rrb->base.Width;
1349 y2 = rrb->base.Height;
1350 } else {
1351 x1 = rrb->dPriv->x;
1352 y1 = rrb->dPriv->y;
1353 x2 = rrb->dPriv->x + rrb->dPriv->w;
1354 y2 = rrb->dPriv->y + rrb->dPriv->h;
1355 }
1356 }
1357
1358 R600_STATECHANGE(context, scissor);
1359
1360 /* screen */
1361 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1362 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1363 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1364 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1365 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1366
1367 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1368 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1369 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1370 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1371
1372 /* window */
1373 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1374 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1375 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1376 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1377 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1378
1379 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1380 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1381 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1382 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1383
1384
1385 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1386 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1387 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1388 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1389 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1390 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1391 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1392 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1393
1394 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1395 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1396 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1397 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1398 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1399 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1400
1401 /* more....2d clip */
1402 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1403 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1404 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1405 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1406 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1407 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1408 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1409 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1410 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1411
1412 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1413 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1414 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1415 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1416 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1417 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1418 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1419 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1420 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1421
1422 r700->viewport[id].enabled = GL_TRUE;
1423 }
1424
1425 static void r700InitSQConfig(GLcontext * ctx)
1426 {
1427 context_t *context = R700_CONTEXT(ctx);
1428 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1429 int ps_prio;
1430 int vs_prio;
1431 int gs_prio;
1432 int es_prio;
1433 int num_ps_gprs;
1434 int num_vs_gprs;
1435 int num_gs_gprs;
1436 int num_es_gprs;
1437 int num_temp_gprs;
1438 int num_ps_threads;
1439 int num_vs_threads;
1440 int num_gs_threads;
1441 int num_es_threads;
1442 int num_ps_stack_entries;
1443 int num_vs_stack_entries;
1444 int num_gs_stack_entries;
1445 int num_es_stack_entries;
1446
1447 R600_STATECHANGE(context, sq);
1448
1449 // SQ
1450 ps_prio = 0;
1451 vs_prio = 1;
1452 gs_prio = 2;
1453 es_prio = 3;
1454 switch (context->radeon.radeonScreen->chip_family) {
1455 case CHIP_FAMILY_R600:
1456 num_ps_gprs = 192;
1457 num_vs_gprs = 56;
1458 num_temp_gprs = 4;
1459 num_gs_gprs = 0;
1460 num_es_gprs = 0;
1461 num_ps_threads = 136;
1462 num_vs_threads = 48;
1463 num_gs_threads = 4;
1464 num_es_threads = 4;
1465 num_ps_stack_entries = 128;
1466 num_vs_stack_entries = 128;
1467 num_gs_stack_entries = 0;
1468 num_es_stack_entries = 0;
1469 break;
1470 case CHIP_FAMILY_RV630:
1471 case CHIP_FAMILY_RV635:
1472 num_ps_gprs = 84;
1473 num_vs_gprs = 36;
1474 num_temp_gprs = 4;
1475 num_gs_gprs = 0;
1476 num_es_gprs = 0;
1477 num_ps_threads = 144;
1478 num_vs_threads = 40;
1479 num_gs_threads = 4;
1480 num_es_threads = 4;
1481 num_ps_stack_entries = 40;
1482 num_vs_stack_entries = 40;
1483 num_gs_stack_entries = 32;
1484 num_es_stack_entries = 16;
1485 break;
1486 case CHIP_FAMILY_RV610:
1487 case CHIP_FAMILY_RV620:
1488 case CHIP_FAMILY_RS780:
1489 case CHIP_FAMILY_RS880:
1490 default:
1491 num_ps_gprs = 84;
1492 num_vs_gprs = 36;
1493 num_temp_gprs = 4;
1494 num_gs_gprs = 0;
1495 num_es_gprs = 0;
1496 num_ps_threads = 136;
1497 num_vs_threads = 48;
1498 num_gs_threads = 4;
1499 num_es_threads = 4;
1500 num_ps_stack_entries = 40;
1501 num_vs_stack_entries = 40;
1502 num_gs_stack_entries = 32;
1503 num_es_stack_entries = 16;
1504 break;
1505 case CHIP_FAMILY_RV670:
1506 num_ps_gprs = 144;
1507 num_vs_gprs = 40;
1508 num_temp_gprs = 4;
1509 num_gs_gprs = 0;
1510 num_es_gprs = 0;
1511 num_ps_threads = 136;
1512 num_vs_threads = 48;
1513 num_gs_threads = 4;
1514 num_es_threads = 4;
1515 num_ps_stack_entries = 40;
1516 num_vs_stack_entries = 40;
1517 num_gs_stack_entries = 32;
1518 num_es_stack_entries = 16;
1519 break;
1520 case CHIP_FAMILY_RV770:
1521 num_ps_gprs = 192;
1522 num_vs_gprs = 56;
1523 num_temp_gprs = 4;
1524 num_gs_gprs = 0;
1525 num_es_gprs = 0;
1526 num_ps_threads = 188;
1527 num_vs_threads = 60;
1528 num_gs_threads = 0;
1529 num_es_threads = 0;
1530 num_ps_stack_entries = 256;
1531 num_vs_stack_entries = 256;
1532 num_gs_stack_entries = 0;
1533 num_es_stack_entries = 0;
1534 break;
1535 case CHIP_FAMILY_RV730:
1536 case CHIP_FAMILY_RV740:
1537 num_ps_gprs = 84;
1538 num_vs_gprs = 36;
1539 num_temp_gprs = 4;
1540 num_gs_gprs = 0;
1541 num_es_gprs = 0;
1542 num_ps_threads = 188;
1543 num_vs_threads = 60;
1544 num_gs_threads = 0;
1545 num_es_threads = 0;
1546 num_ps_stack_entries = 128;
1547 num_vs_stack_entries = 128;
1548 num_gs_stack_entries = 0;
1549 num_es_stack_entries = 0;
1550 break;
1551 case CHIP_FAMILY_RV710:
1552 num_ps_gprs = 192;
1553 num_vs_gprs = 56;
1554 num_temp_gprs = 4;
1555 num_gs_gprs = 0;
1556 num_es_gprs = 0;
1557 num_ps_threads = 144;
1558 num_vs_threads = 48;
1559 num_gs_threads = 0;
1560 num_es_threads = 0;
1561 num_ps_stack_entries = 128;
1562 num_vs_stack_entries = 128;
1563 num_gs_stack_entries = 0;
1564 num_es_stack_entries = 0;
1565 break;
1566 }
1567
1568 r700->sq_config.SQ_CONFIG.u32All = 0;
1569 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1570 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1571 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1572 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1573 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1574 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1575 else
1576 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1577 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1578 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1579 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1580 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1581 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1582 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1583
1584 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1585 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1586 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1587 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1588 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1589
1590 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1591 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1592 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1593
1594 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1595 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1596 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1597 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1598 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1599 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1600 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1601 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1602 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1603
1604 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1605 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1606 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1607 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1608 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1609
1610 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1611 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1612 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1613 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1614 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1615
1616 }
1617
1618 /**
1619 * Calculate initial hardware state and register state functions.
1620 * Assumes that the command buffer and state atoms have been
1621 * initialized already.
1622 */
1623 void r700InitState(GLcontext * ctx) //-------------------
1624 {
1625 context_t *context = R700_CONTEXT(ctx);
1626 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1627 int id = 0;
1628
1629 radeon_firevertices(&context->radeon);
1630
1631 r700->TA_CNTL_AUX.u32All = 0;
1632 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1633 r700->VC_ENHANCE.u32All = 0;
1634 r700->DB_WATERMARKS.u32All = 0;
1635 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1636 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1637 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1638 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1639 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1640 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1641 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1642 r700->DB_DEBUG.u32All = 0x82000000;
1643 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1644 } else {
1645 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1646 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1647 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1648 }
1649
1650 /* Turn off vgt reuse */
1651 r700->VGT_REUSE_OFF.u32All = 0;
1652 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1653
1654 /* Specify offsetting and clamp values for vertices */
1655 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1656 r700->VGT_MIN_VTX_INDX.u32All = 0;
1657 r700->VGT_INDX_OFFSET.u32All = 0;
1658
1659 /* default shader connections. */
1660 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1661 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1662 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1663 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1664
1665 r700->SPI_THREAD_GROUPING.u32All = 0;
1666 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1667 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1668
1669 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1670 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1671 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1672
1673 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1674 r700->PA_SC_EDGERULE.u32All = 0;
1675 else
1676 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1677
1678 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1679 r700->PA_SC_MODE_CNTL.u32All = 0;
1680 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1681 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1682 } else {
1683 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1684 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1685 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1686 }
1687
1688 /* Do scale XY and Z by 1/W0. */
1689 r700->bEnablePerspective = GL_TRUE;
1690 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1691 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1692 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1693
1694 /* Enable viewport scaling for all three axis */
1695 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1696 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1697 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1698 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1699 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1700 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1701
1702 /* GL uses last vtx for flat shading components */
1703 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1704
1705 /* Set up vertex control */
1706 r700->PA_SU_VTX_CNTL.u32All = 0;
1707 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1708 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1709 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1710 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1711
1712 /* to 1.0 = no guard band */
1713 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1714 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1715 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1716 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1717
1718 /* Enable all samples for multi-sample anti-aliasing */
1719 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1720 /* Turn off AA */
1721 r700->PA_SC_AA_CONFIG.u32All = 0;
1722
1723 r700->SX_MISC.u32All = 0;
1724
1725 r700InitSQConfig(ctx);
1726
1727 r700ColorMask(ctx,
1728 ctx->Color.ColorMask[RCOMP],
1729 ctx->Color.ColorMask[GCOMP],
1730 ctx->Color.ColorMask[BCOMP],
1731 ctx->Color.ColorMask[ACOMP]);
1732
1733 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1734 r700DepthMask(ctx, ctx->Depth.Mask);
1735 r700DepthFunc(ctx, ctx->Depth.Func);
1736 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1737 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1738 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1739 r700SetDBRenderState(ctx);
1740
1741 r700->DB_ALPHA_TO_MASK.u32All = 0;
1742 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1743 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1744 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1745 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1746
1747 /* stencil */
1748 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1749 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1750 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1751 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1752 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1753 ctx->Stencil.ZFailFunc[0],
1754 ctx->Stencil.ZPassFunc[0]);
1755
1756 r700UpdateCulling(ctx);
1757
1758 r700SetBlendState(ctx);
1759 r700SetLogicOpState(ctx);
1760
1761 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1762 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1763
1764 r700PointSize(ctx, 1.0);
1765
1766 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1767 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1768
1769 r700LineWidth(ctx, 1.0);
1770
1771 r700->PA_SC_LINE_CNTL.u32All = 0;
1772 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1773 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1774
1775 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1776 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1777 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1778 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1779 ctx->Polygon.OffsetUnits);
1780 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1781 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1782 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1783
1784 /* CB */
1785 r700BlendColor(ctx, ctx->Color.BlendColor);
1786
1787 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1788 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1789 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1790 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1791 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1792 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1793 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1794
1795 /* Disable color compares */
1796 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1797 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1798 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1799 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1800 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1801 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1802
1803 /* Zero out source */
1804 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1805
1806 /* Put a compare color in for error checking */
1807 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1808
1809 /* Set up color compare mask */
1810 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1811
1812 /* screen/window/view */
1813 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask);
1814
1815 context->radeon.hw.all_dirty = GL_TRUE;
1816
1817 }
1818
1819 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1820 {
1821 functions->UpdateState = r700InvalidateState;
1822 functions->AlphaFunc = r700AlphaFunc;
1823 functions->BlendColor = r700BlendColor;
1824 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1825 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1826 functions->Enable = r700Enable;
1827 functions->ColorMask = r700ColorMask;
1828 functions->DepthFunc = r700DepthFunc;
1829 functions->DepthMask = r700DepthMask;
1830 functions->CullFace = r700CullFace;
1831 functions->Fogfv = r700Fogfv;
1832 functions->FrontFace = r700FrontFace;
1833 functions->ShadeModel = r700ShadeModel;
1834 functions->LogicOpcode = r700LogicOpcode;
1835
1836 /* ARB_point_parameters */
1837 functions->PointParameterfv = r700PointParameter;
1838
1839 /* Stencil related */
1840 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1841 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1842 functions->StencilOpSeparate = r700StencilOpSeparate;
1843
1844 /* Viewport related */
1845 functions->Viewport = r700Viewport;
1846 functions->DepthRange = r700DepthRange;
1847 functions->PointSize = r700PointSize;
1848 functions->LineWidth = r700LineWidth;
1849 functions->LineStipple = r700LineStipple;
1850
1851 functions->PolygonOffset = r700PolygonOffset;
1852 functions->PolygonMode = r700PolygonMode;
1853
1854 functions->RenderMode = r700RenderMode;
1855
1856 functions->ClipPlane = r700ClipPlane;
1857
1858 functions->Scissor = radeonScissor;
1859
1860 functions->DrawBuffer = radeonDrawBuffer;
1861 functions->ReadBuffer = radeonReadBuffer;
1862
1863 }
1864