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r600: use CB_TARGET_MASK instead of CB_SHADER_MASK for setting color mask
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63
64 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
65 {
66 context_t *context = R700_CONTEXT(ctx);
67 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
68 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
69 int i;
70
71 /* should only happenen once, just after context is created */
72 /* TODO: shouldn't we fallback to sw here? */
73 if (!ctx->FragmentProgram._Current) {
74 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
75 return;
76 }
77
78 r700SelectFragmentShader(ctx);
79
80 if (context->radeon.NewGLState) {
81 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
82 /* mat states from state var not array for sw */
83 dummy_attrib[i].stride = 0;
84 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
85 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
86 }
87
88 _tnl_UpdateFixedFunctionProgram(ctx);
89
90 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
91 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
92 }
93 }
94
95 r700SelectVertexShader(ctx, 1);
96 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
97 context->radeon.NewGLState = 0;
98 }
99
100 void r700UpdateShaders2(GLcontext * ctx)
101 {
102 context_t *context = R700_CONTEXT(ctx);
103
104 /* should only happenen once, just after context is created */
105 /* TODO: shouldn't we fallback to sw here? */
106 if (!ctx->FragmentProgram._Current) {
107 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
108 return;
109 }
110
111 r700SelectFragmentShader(ctx);
112
113 r700SelectVertexShader(ctx, 2);
114 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
115 context->radeon.NewGLState = 0;
116 }
117
118 /*
119 * To correctly position primitives:
120 */
121 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
122 {
123 context_t *context = R700_CONTEXT(ctx);
124 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
125 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
126 GLfloat xoffset = (GLfloat) dPriv->x;
127 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
128 const GLfloat *v = ctx->Viewport._WindowMap.m;
129 int id = 0;
130
131 GLfloat tx = v[MAT_TX] + xoffset;
132 GLfloat ty = (-v[MAT_TY]) + yoffset;
133
134 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
135 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
136 /* Note: this should also modify whatever data the context reset
137 * code uses...
138 */
139 R600_STATECHANGE(context, vpt);
140 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
141 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
142 }
143
144 radeonUpdateScissor(ctx);
145 }
146
147 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
148 {
149 struct r700_fragment_program *fp =
150 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
151 struct gl_program_parameter_list *paramList;
152
153 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
154 return;
155
156 if (!ctx->FragmentProgram._Current || !fp)
157 return;
158
159 paramList = ctx->FragmentProgram._Current->Base.Parameters;
160
161 if (!paramList)
162 return;
163
164 _mesa_load_state_parameters(ctx, paramList);
165
166 }
167
168 /**
169 * Called by Mesa after an internal state update.
170 */
171 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
172 {
173 context_t *context = R700_CONTEXT(ctx);
174
175 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
176
177 _swrast_InvalidateState(ctx, new_state);
178 _swsetup_InvalidateState(ctx, new_state);
179 _vbo_InvalidateState(ctx, new_state);
180 _tnl_InvalidateState(ctx, new_state);
181 _ae_invalidate_state(ctx, new_state);
182
183 if (new_state & _NEW_BUFFERS) {
184 _mesa_update_framebuffer(ctx);
185 /* this updates the DrawBuffer's Width/Height if it's a FBO */
186 _mesa_update_draw_buffer_bounds(ctx);
187
188 R600_STATECHANGE(context, cb_target);
189 R600_STATECHANGE(context, db_target);
190 }
191
192 if (new_state & (_NEW_LIGHT)) {
193 R600_STATECHANGE(context, su);
194 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
195 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
196 else
197 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
198 }
199
200 r700UpdateStateParameters(ctx, new_state);
201
202 R600_STATECHANGE(context, cl);
203 R600_STATECHANGE(context, spi);
204
205 if(GL_TRUE == r700->bEnablePerspective)
206 {
207 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
208 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
209 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
210
211 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
212
213 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
214 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
215 }
216 else
217 {
218 /* For orthogonal case. */
219 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
220 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
221
222 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
223
224 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
225 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
226 }
227
228 context->radeon.NewGLState |= new_state;
229 }
230
231 static void r700SetDepthState(GLcontext * ctx)
232 {
233 context_t *context = R700_CONTEXT(ctx);
234 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
235
236 R600_STATECHANGE(context, db);
237
238 if (ctx->Depth.Test)
239 {
240 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
241 if (ctx->Depth.Mask)
242 {
243 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
244 }
245 else
246 {
247 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
248 }
249
250 switch (ctx->Depth.Func)
251 {
252 case GL_NEVER:
253 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
254 ZFUNC_shift, ZFUNC_mask);
255 break;
256 case GL_LESS:
257 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
258 ZFUNC_shift, ZFUNC_mask);
259 break;
260 case GL_EQUAL:
261 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
262 ZFUNC_shift, ZFUNC_mask);
263 break;
264 case GL_LEQUAL:
265 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
266 ZFUNC_shift, ZFUNC_mask);
267 break;
268 case GL_GREATER:
269 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
270 ZFUNC_shift, ZFUNC_mask);
271 break;
272 case GL_NOTEQUAL:
273 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
274 ZFUNC_shift, ZFUNC_mask);
275 break;
276 case GL_GEQUAL:
277 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
278 ZFUNC_shift, ZFUNC_mask);
279 break;
280 case GL_ALWAYS:
281 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
282 ZFUNC_shift, ZFUNC_mask);
283 break;
284 default:
285 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
286 ZFUNC_shift, ZFUNC_mask);
287 break;
288 }
289 }
290 else
291 {
292 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
293 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
294 }
295 }
296
297 static void r700SetAlphaState(GLcontext * ctx)
298 {
299 context_t *context = R700_CONTEXT(ctx);
300 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
301 uint32_t alpha_func = REF_ALWAYS;
302 GLboolean really_enabled = ctx->Color.AlphaEnabled;
303
304 R600_STATECHANGE(context, sx);
305
306 switch (ctx->Color.AlphaFunc) {
307 case GL_NEVER:
308 alpha_func = REF_NEVER;
309 break;
310 case GL_LESS:
311 alpha_func = REF_LESS;
312 break;
313 case GL_EQUAL:
314 alpha_func = REF_EQUAL;
315 break;
316 case GL_LEQUAL:
317 alpha_func = REF_LEQUAL;
318 break;
319 case GL_GREATER:
320 alpha_func = REF_GREATER;
321 break;
322 case GL_NOTEQUAL:
323 alpha_func = REF_NOTEQUAL;
324 break;
325 case GL_GEQUAL:
326 alpha_func = REF_GEQUAL;
327 break;
328 case GL_ALWAYS:
329 /*alpha_func = REF_ALWAYS; */
330 really_enabled = GL_FALSE;
331 break;
332 }
333
334 if (really_enabled) {
335 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
336 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
337 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
338 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
339 } else {
340 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
341 }
342
343 }
344
345 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
346 {
347 (void)func;
348 (void)ref;
349 r700SetAlphaState(ctx);
350 }
351
352
353 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
354 {
355 context_t *context = R700_CONTEXT(ctx);
356 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
357
358 R600_STATECHANGE(context, blnd_clr);
359
360 r700->CB_BLEND_RED.f32All = cf[0];
361 r700->CB_BLEND_GREEN.f32All = cf[1];
362 r700->CB_BLEND_BLUE.f32All = cf[2];
363 r700->CB_BLEND_ALPHA.f32All = cf[3];
364 }
365
366 static int blend_factor(GLenum factor, GLboolean is_src)
367 {
368 switch (factor) {
369 case GL_ZERO:
370 return BLEND_ZERO;
371 break;
372 case GL_ONE:
373 return BLEND_ONE;
374 break;
375 case GL_DST_COLOR:
376 return BLEND_DST_COLOR;
377 break;
378 case GL_ONE_MINUS_DST_COLOR:
379 return BLEND_ONE_MINUS_DST_COLOR;
380 break;
381 case GL_SRC_COLOR:
382 return BLEND_SRC_COLOR;
383 break;
384 case GL_ONE_MINUS_SRC_COLOR:
385 return BLEND_ONE_MINUS_SRC_COLOR;
386 break;
387 case GL_SRC_ALPHA:
388 return BLEND_SRC_ALPHA;
389 break;
390 case GL_ONE_MINUS_SRC_ALPHA:
391 return BLEND_ONE_MINUS_SRC_ALPHA;
392 break;
393 case GL_DST_ALPHA:
394 return BLEND_DST_ALPHA;
395 break;
396 case GL_ONE_MINUS_DST_ALPHA:
397 return BLEND_ONE_MINUS_DST_ALPHA;
398 break;
399 case GL_SRC_ALPHA_SATURATE:
400 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
401 break;
402 case GL_CONSTANT_COLOR:
403 return BLEND_CONSTANT_COLOR;
404 break;
405 case GL_ONE_MINUS_CONSTANT_COLOR:
406 return BLEND_ONE_MINUS_CONSTANT_COLOR;
407 break;
408 case GL_CONSTANT_ALPHA:
409 return BLEND_CONSTANT_ALPHA;
410 break;
411 case GL_ONE_MINUS_CONSTANT_ALPHA:
412 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
413 break;
414 default:
415 fprintf(stderr, "unknown blend factor %x\n", factor);
416 return (is_src) ? BLEND_ONE : BLEND_ZERO;
417 break;
418 }
419 }
420
421 static void r700SetBlendState(GLcontext * ctx)
422 {
423 context_t *context = R700_CONTEXT(ctx);
424 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
425 int id = 0;
426 uint32_t blend_reg = 0, eqn, eqnA;
427
428 R600_STATECHANGE(context, blnd);
429
430 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
431 SETfield(blend_reg,
432 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
433 SETfield(blend_reg,
434 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
435 SETfield(blend_reg,
436 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
437 SETfield(blend_reg,
438 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
439 SETfield(blend_reg,
440 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
441 SETfield(blend_reg,
442 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
443 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
444 r700->CB_BLEND_CONTROL.u32All = blend_reg;
445 else
446 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
447 return;
448 }
449
450 SETfield(blend_reg,
451 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
452 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
453 SETfield(blend_reg,
454 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
455 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
456
457 switch (ctx->Color.BlendEquationRGB) {
458 case GL_FUNC_ADD:
459 eqn = COMB_DST_PLUS_SRC;
460 break;
461 case GL_FUNC_SUBTRACT:
462 eqn = COMB_SRC_MINUS_DST;
463 break;
464 case GL_FUNC_REVERSE_SUBTRACT:
465 eqn = COMB_DST_MINUS_SRC;
466 break;
467 case GL_MIN:
468 eqn = COMB_MIN_DST_SRC;
469 SETfield(blend_reg,
470 BLEND_ONE,
471 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
472 SETfield(blend_reg,
473 BLEND_ONE,
474 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
475 break;
476 case GL_MAX:
477 eqn = COMB_MAX_DST_SRC;
478 SETfield(blend_reg,
479 BLEND_ONE,
480 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
481 SETfield(blend_reg,
482 BLEND_ONE,
483 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
484 break;
485
486 default:
487 fprintf(stderr,
488 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
489 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
490 return;
491 }
492 SETfield(blend_reg,
493 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
494
495 SETfield(blend_reg,
496 blend_factor(ctx->Color.BlendSrcA, GL_TRUE),
497 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
498 SETfield(blend_reg,
499 blend_factor(ctx->Color.BlendDstA, GL_FALSE),
500 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
501
502 switch (ctx->Color.BlendEquationA) {
503 case GL_FUNC_ADD:
504 eqnA = COMB_DST_PLUS_SRC;
505 break;
506 case GL_FUNC_SUBTRACT:
507 eqnA = COMB_SRC_MINUS_DST;
508 break;
509 case GL_FUNC_REVERSE_SUBTRACT:
510 eqnA = COMB_DST_MINUS_SRC;
511 break;
512 case GL_MIN:
513 eqnA = COMB_MIN_DST_SRC;
514 SETfield(blend_reg,
515 BLEND_ONE,
516 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
517 SETfield(blend_reg,
518 BLEND_ONE,
519 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
520 break;
521 case GL_MAX:
522 eqnA = COMB_MAX_DST_SRC;
523 SETfield(blend_reg,
524 BLEND_ONE,
525 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
526 SETfield(blend_reg,
527 BLEND_ONE,
528 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
529 break;
530 default:
531 fprintf(stderr,
532 "[%s:%u] Invalid A blend equation (0x%04x).\n",
533 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
534 return;
535 }
536
537 SETfield(blend_reg,
538 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
539
540 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
541
542 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
543 r700->CB_BLEND_CONTROL.u32All = blend_reg;
544 else {
545 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
546 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
547 }
548 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
549 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
550
551 }
552
553 static void r700BlendEquationSeparate(GLcontext * ctx,
554 GLenum modeRGB, GLenum modeA) //-----------------
555 {
556 r700SetBlendState(ctx);
557 }
558
559 static void r700BlendFuncSeparate(GLcontext * ctx,
560 GLenum sfactorRGB, GLenum dfactorRGB,
561 GLenum sfactorA, GLenum dfactorA) //------------------------
562 {
563 r700SetBlendState(ctx);
564 }
565
566 /**
567 * Translate LogicOp enums into hardware representation.
568 */
569 static GLuint translate_logicop(GLenum logicop)
570 {
571 switch (logicop) {
572 case GL_CLEAR:
573 return 0x00;
574 case GL_SET:
575 return 0xff;
576 case GL_COPY:
577 return 0xcc;
578 case GL_COPY_INVERTED:
579 return 0x33;
580 case GL_NOOP:
581 return 0xaa;
582 case GL_INVERT:
583 return 0x55;
584 case GL_AND:
585 return 0x88;
586 case GL_NAND:
587 return 0x77;
588 case GL_OR:
589 return 0xee;
590 case GL_NOR:
591 return 0x11;
592 case GL_XOR:
593 return 0x66;
594 case GL_EQUIV:
595 return 0xaa;
596 case GL_AND_REVERSE:
597 return 0x44;
598 case GL_AND_INVERTED:
599 return 0x22;
600 case GL_OR_REVERSE:
601 return 0xdd;
602 case GL_OR_INVERTED:
603 return 0xbb;
604 default:
605 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
606 return 0xcc;
607 }
608 }
609
610 /**
611 * Used internally to update the r300->hw hardware state to match the
612 * current OpenGL state.
613 */
614 static void r700SetLogicOpState(GLcontext *ctx)
615 {
616 context_t *context = R700_CONTEXT(ctx);
617 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
618
619 R600_STATECHANGE(context, blnd);
620
621 if (RGBA_LOGICOP_ENABLED(ctx))
622 SETfield(r700->CB_COLOR_CONTROL.u32All,
623 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
624 else
625 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
626 }
627
628 /**
629 * Called by Mesa when an application program changes the LogicOp state
630 * via glLogicOp.
631 */
632 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
633 {
634 if (RGBA_LOGICOP_ENABLED(ctx))
635 r700SetLogicOpState(ctx);
636 }
637
638 static void r700UpdateCulling(GLcontext * ctx)
639 {
640 context_t *context = R700_CONTEXT(ctx);
641 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
642
643 R600_STATECHANGE(context, su);
644
645 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
646 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
647 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
648
649 if (ctx->Polygon.CullFlag)
650 {
651 switch (ctx->Polygon.CullFaceMode)
652 {
653 case GL_FRONT:
654 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
655 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
656 break;
657 case GL_BACK:
658 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
659 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
660 break;
661 case GL_FRONT_AND_BACK:
662 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
663 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
664 break;
665 default:
666 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
667 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
668 break;
669 }
670 }
671
672 switch (ctx->Polygon.FrontFace)
673 {
674 case GL_CW:
675 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
676 break;
677 case GL_CCW:
678 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
679 break;
680 default:
681 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
682 break;
683 }
684 }
685
686 static void r700UpdateLineStipple(GLcontext * ctx)
687 {
688 context_t *context = R700_CONTEXT(ctx);
689 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
690
691 R600_STATECHANGE(context, sc);
692
693 if (ctx->Line.StippleFlag)
694 {
695 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
696 }
697 else
698 {
699 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
700 }
701 }
702
703 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
704 {
705 context_t *context = R700_CONTEXT(ctx);
706
707 switch (cap) {
708 case GL_TEXTURE_1D:
709 case GL_TEXTURE_2D:
710 case GL_TEXTURE_3D:
711 /* empty */
712 break;
713 case GL_FOG:
714 /* empty */
715 break;
716 case GL_ALPHA_TEST:
717 r700SetAlphaState(ctx);
718 break;
719 case GL_COLOR_LOGIC_OP:
720 r700SetLogicOpState(ctx);
721 /* fall-through, because logic op overrides blending */
722 case GL_BLEND:
723 r700SetBlendState(ctx);
724 break;
725 case GL_CLIP_PLANE0:
726 case GL_CLIP_PLANE1:
727 case GL_CLIP_PLANE2:
728 case GL_CLIP_PLANE3:
729 case GL_CLIP_PLANE4:
730 case GL_CLIP_PLANE5:
731 r700SetClipPlaneState(ctx, cap, state);
732 break;
733 case GL_DEPTH_TEST:
734 r700SetDepthState(ctx);
735 break;
736 case GL_STENCIL_TEST:
737 r700SetStencilState(ctx, state);
738 break;
739 case GL_CULL_FACE:
740 r700UpdateCulling(ctx);
741 break;
742 case GL_POLYGON_OFFSET_POINT:
743 case GL_POLYGON_OFFSET_LINE:
744 case GL_POLYGON_OFFSET_FILL:
745 r700SetPolygonOffsetState(ctx, state);
746 break;
747 case GL_SCISSOR_TEST:
748 radeon_firevertices(&context->radeon);
749 context->radeon.state.scissor.enabled = state;
750 radeonUpdateScissor(ctx);
751 break;
752 case GL_LINE_STIPPLE:
753 r700UpdateLineStipple(ctx);
754 break;
755 default:
756 break;
757 }
758
759 }
760
761 /**
762 * Handle glColorMask()
763 */
764 static void r700ColorMask(GLcontext * ctx,
765 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
766 {
767 context_t *context = R700_CONTEXT(ctx);
768 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
769 unsigned int mask = ((r ? 1 : 0) |
770 (g ? 2 : 0) |
771 (b ? 4 : 0) |
772 (a ? 8 : 0));
773
774 if (mask != r700->CB_TARGET_MASK.u32All) {
775 R600_STATECHANGE(context, cb);
776 SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
777 }
778 }
779
780 /**
781 * Change the depth testing function.
782 *
783 * \note Mesa already filters redundant calls to this function.
784 */
785 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
786 {
787 r700SetDepthState(ctx);
788 }
789
790 /**
791 * Enable/Disable depth writing.
792 *
793 * \note Mesa already filters redundant calls to this function.
794 */
795 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
796 {
797 r700SetDepthState(ctx);
798 }
799
800 /**
801 * Change the culling mode.
802 *
803 * \note Mesa already filters redundant calls to this function.
804 */
805 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
806 {
807 r700UpdateCulling(ctx);
808 }
809
810 /* =============================================================
811 * Fog
812 */
813 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
814 {
815 }
816
817 /**
818 * Change the polygon orientation.
819 *
820 * \note Mesa already filters redundant calls to this function.
821 */
822 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
823 {
824 r700UpdateCulling(ctx);
825 r700UpdatePolygonMode(ctx);
826 }
827
828 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
829 {
830 context_t *context = R700_CONTEXT(ctx);
831 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
832
833 R600_STATECHANGE(context, spi);
834
835 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
836 switch (mode) {
837 case GL_FLAT:
838 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
839 break;
840 case GL_SMOOTH:
841 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
842 break;
843 default:
844 return;
845 }
846 }
847
848 /* =============================================================
849 * Point state
850 */
851 static void r700PointSize(GLcontext * ctx, GLfloat size)
852 {
853 context_t *context = R700_CONTEXT(ctx);
854 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
855
856 R600_STATECHANGE(context, su);
857
858 /* We need to clamp to user defined range here, because
859 * the HW clamping happens only for per vertex point size. */
860 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
861
862 /* same size limits for AA, non-AA points */
863 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
864
865 /* format is 12.4 fixed point */
866 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
867 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
868 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
869 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
870
871 }
872
873 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
874 {
875 context_t *context = R700_CONTEXT(ctx);
876 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
877
878 R600_STATECHANGE(context, su);
879
880 /* format is 12.4 fixed point */
881 switch (pname) {
882 case GL_POINT_SIZE_MIN:
883 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
884 MIN_SIZE_shift, MIN_SIZE_mask);
885 break;
886 case GL_POINT_SIZE_MAX:
887 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
888 MAX_SIZE_shift, MAX_SIZE_mask);
889 break;
890 case GL_POINT_DISTANCE_ATTENUATION:
891 break;
892 case GL_POINT_FADE_THRESHOLD_SIZE:
893 break;
894 default:
895 break;
896 }
897 }
898
899 static int translate_stencil_func(int func)
900 {
901 switch (func) {
902 case GL_NEVER:
903 return REF_NEVER;
904 case GL_LESS:
905 return REF_LESS;
906 case GL_EQUAL:
907 return REF_EQUAL;
908 case GL_LEQUAL:
909 return REF_LEQUAL;
910 case GL_GREATER:
911 return REF_GREATER;
912 case GL_NOTEQUAL:
913 return REF_NOTEQUAL;
914 case GL_GEQUAL:
915 return REF_GEQUAL;
916 case GL_ALWAYS:
917 return REF_ALWAYS;
918 }
919 return 0;
920 }
921
922 static int translate_stencil_op(int op)
923 {
924 switch (op) {
925 case GL_KEEP:
926 return STENCIL_KEEP;
927 case GL_ZERO:
928 return STENCIL_ZERO;
929 case GL_REPLACE:
930 return STENCIL_REPLACE;
931 case GL_INCR:
932 return STENCIL_INCR_CLAMP;
933 case GL_DECR:
934 return STENCIL_DECR_CLAMP;
935 case GL_INCR_WRAP_EXT:
936 return STENCIL_INCR_WRAP;
937 case GL_DECR_WRAP_EXT:
938 return STENCIL_DECR_WRAP;
939 case GL_INVERT:
940 return STENCIL_INVERT;
941 default:
942 WARN_ONCE("Do not know how to translate stencil op");
943 return STENCIL_KEEP;
944 }
945 return 0;
946 }
947
948 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
949 {
950 context_t *context = R700_CONTEXT(ctx);
951 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
952 GLboolean hw_stencil = GL_FALSE;
953
954 if (ctx->DrawBuffer) {
955 struct radeon_renderbuffer *rrbStencil
956 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
957 hw_stencil = (rrbStencil && rrbStencil->bo);
958 }
959
960 if (hw_stencil) {
961 R600_STATECHANGE(context, db);
962 if (state) {
963 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
964 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
965 } else
966 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
967 }
968 }
969
970 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
971 GLenum func, GLint ref, GLuint mask) //---------------------
972 {
973 context_t *context = R700_CONTEXT(ctx);
974 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
975 const unsigned back = ctx->Stencil._BackFace;
976
977 R600_STATECHANGE(context, stencil);
978 R600_STATECHANGE(context, db);
979
980 //front
981 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
982 STENCILREF_shift, STENCILREF_mask);
983 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
984 STENCILMASK_shift, STENCILMASK_mask);
985
986 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
987 STENCILFUNC_shift, STENCILFUNC_mask);
988
989 //back
990 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
991 STENCILREF_BF_shift, STENCILREF_BF_mask);
992 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
993 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
994
995 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
996 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
997
998 }
999
1000 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1001 {
1002 context_t *context = R700_CONTEXT(ctx);
1003 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1004 const unsigned back = ctx->Stencil._BackFace;
1005
1006 R600_STATECHANGE(context, stencil);
1007
1008 // front
1009 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1010 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1011
1012 // back
1013 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1014 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1015
1016 }
1017
1018 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1019 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1020 {
1021 context_t *context = R700_CONTEXT(ctx);
1022 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1023 const unsigned back = ctx->Stencil._BackFace;
1024
1025 R600_STATECHANGE(context, db);
1026
1027 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1028 STENCILFAIL_shift, STENCILFAIL_mask);
1029 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1030 STENCILZFAIL_shift, STENCILZFAIL_mask);
1031 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1032 STENCILZPASS_shift, STENCILZPASS_mask);
1033
1034 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1035 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1036 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1037 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1038 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1039 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1040 }
1041
1042 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1043 {
1044 context_t *context = R700_CONTEXT(ctx);
1045 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1046 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1047 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1048 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1049 const GLfloat *v = ctx->Viewport._WindowMap.m;
1050 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1051 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1052 GLfloat y_scale, y_bias;
1053
1054 if (render_to_fbo) {
1055 y_scale = 1.0;
1056 y_bias = 0;
1057 } else {
1058 y_scale = -1.0;
1059 y_bias = yoffset;
1060 }
1061
1062 GLfloat sx = v[MAT_SX];
1063 GLfloat tx = v[MAT_TX] + xoffset;
1064 GLfloat sy = v[MAT_SY] * y_scale;
1065 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1066 GLfloat sz = v[MAT_SZ] * depthScale;
1067 GLfloat tz = v[MAT_TZ] * depthScale;
1068
1069 R600_STATECHANGE(context, vpt);
1070
1071 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1072 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1073
1074 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1075 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1076
1077 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1078 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1079
1080 r700->viewport[id].enabled = GL_TRUE;
1081
1082 r700SetScissor(context);
1083 }
1084
1085
1086 static void r700Viewport(GLcontext * ctx,
1087 GLint x,
1088 GLint y,
1089 GLsizei width,
1090 GLsizei height) //--------------------
1091 {
1092 r700UpdateWindow(ctx, 0);
1093
1094 radeon_viewport(ctx, x, y, width, height);
1095 }
1096
1097 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1098 {
1099 r700UpdateWindow(ctx, 0);
1100 }
1101
1102 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1103 {
1104 context_t *context = R700_CONTEXT(ctx);
1105 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1106 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1107
1108 R600_STATECHANGE(context, su);
1109
1110 if (lineWidth > 0xFFFF)
1111 lineWidth = 0xFFFF;
1112 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1113 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1114 }
1115
1116 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1117 {
1118 context_t *context = R700_CONTEXT(ctx);
1119 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1120
1121 R600_STATECHANGE(context, sc);
1122
1123 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1124 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1125 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1126 }
1127
1128 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1129 {
1130 context_t *context = R700_CONTEXT(ctx);
1131 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1132
1133 R600_STATECHANGE(context, su);
1134
1135 if (state) {
1136 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1137 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1138 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1139 } else {
1140 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1141 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1142 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1143 }
1144 }
1145
1146 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1147 {
1148 context_t *context = R700_CONTEXT(ctx);
1149 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1150 GLfloat constant = units;
1151 GLchar depth = 0;
1152
1153 R600_STATECHANGE(context, poly);
1154
1155 switch (ctx->Visual.depthBits) {
1156 case 16:
1157 constant *= 4.0;
1158 depth = -16;
1159 break;
1160 case 24:
1161 constant *= 2.0;
1162 depth = -24;
1163 break;
1164 }
1165
1166 factor *= 12.0;
1167 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1168 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1169 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1170 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1171 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1172 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1173 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1174 }
1175
1176 static void r700UpdatePolygonMode(GLcontext * ctx)
1177 {
1178 context_t *context = R700_CONTEXT(ctx);
1179 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1180
1181 R600_STATECHANGE(context, su);
1182
1183 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1184
1185 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1186 if (ctx->Polygon.FrontMode != GL_FILL ||
1187 ctx->Polygon.BackMode != GL_FILL) {
1188 GLenum f, b;
1189
1190 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1191 * correctly by selecting the correct front and back face
1192 */
1193 if (ctx->Polygon.FrontFace == GL_CCW) {
1194 f = ctx->Polygon.FrontMode;
1195 b = ctx->Polygon.BackMode;
1196 } else {
1197 f = ctx->Polygon.BackMode;
1198 b = ctx->Polygon.FrontMode;
1199 }
1200
1201 /* Enable polygon mode */
1202 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1203
1204 switch (f) {
1205 case GL_LINE:
1206 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1207 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1208 break;
1209 case GL_POINT:
1210 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1211 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1212 break;
1213 case GL_FILL:
1214 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1215 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1216 break;
1217 }
1218
1219 switch (b) {
1220 case GL_LINE:
1221 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1222 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1223 break;
1224 case GL_POINT:
1225 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1226 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1227 break;
1228 case GL_FILL:
1229 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1230 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1231 break;
1232 }
1233 }
1234 }
1235
1236 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1237 {
1238 (void)face;
1239 (void)mode;
1240
1241 r700UpdatePolygonMode(ctx);
1242 }
1243
1244 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1245 {
1246 }
1247
1248 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1249 {
1250 context_t *context = R700_CONTEXT(ctx);
1251 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1252 GLint p;
1253 GLint *ip;
1254
1255 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1256 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1257
1258 R600_STATECHANGE(context, ucp);
1259
1260 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1261 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1262 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1263 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1264 }
1265
1266 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1267 {
1268 context_t *context = R700_CONTEXT(ctx);
1269 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1270 GLuint p;
1271
1272 p = cap - GL_CLIP_PLANE0;
1273
1274 R600_STATECHANGE(context, cl);
1275
1276 if (state) {
1277 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1278 r700->ucp[p].enabled = GL_TRUE;
1279 r700ClipPlane(ctx, cap, NULL);
1280 } else {
1281 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1282 r700->ucp[p].enabled = GL_FALSE;
1283 }
1284 }
1285
1286 void r700SetScissor(context_t *context) //---------------
1287 {
1288 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1289 unsigned x1, y1, x2, y2;
1290 int id = 0;
1291 struct radeon_renderbuffer *rrb;
1292
1293 rrb = radeon_get_colorbuffer(&context->radeon);
1294 if (!rrb || !rrb->bo) {
1295 return;
1296 }
1297 if (context->radeon.state.scissor.enabled) {
1298 /* r600 has exclusive scissors */
1299 x1 = context->radeon.state.scissor.rect.x1;
1300 y1 = context->radeon.state.scissor.rect.y1;
1301 x2 = context->radeon.state.scissor.rect.x2 + 1;
1302 y2 = context->radeon.state.scissor.rect.y2 + 1;
1303 } else {
1304 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1305 x1 = 0;
1306 y1 = 0;
1307 x2 = rrb->base.Width;
1308 y2 = rrb->base.Height;
1309 } else {
1310 x1 = rrb->dPriv->x;
1311 y1 = rrb->dPriv->y;
1312 x2 = rrb->dPriv->x + rrb->dPriv->w;
1313 y2 = rrb->dPriv->y + rrb->dPriv->h;
1314 }
1315 }
1316
1317 R600_STATECHANGE(context, scissor);
1318
1319 /* screen */
1320 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1321 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1322 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1323 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1324 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1325
1326 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1327 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1328 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1329 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1330
1331 /* window */
1332 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1333 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1334 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1335 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1336 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1337
1338 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1339 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1340 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1341 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1342
1343
1344 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1345 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1346 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1347 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1348 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1349 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1350 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1351 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1352
1353 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1354 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1355 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1356 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1357 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1358 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1359
1360 /* more....2d clip */
1361 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1362 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1363 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1364 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1365 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1366 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1367 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1368 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1369 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1370
1371 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1372 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1373 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1374 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1375 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1376 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1377 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1378 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1379 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1380
1381 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1382 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1383 r700->viewport[id].enabled = GL_TRUE;
1384 }
1385
1386 static void r700InitSQConfig(GLcontext * ctx)
1387 {
1388 context_t *context = R700_CONTEXT(ctx);
1389 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1390 int ps_prio;
1391 int vs_prio;
1392 int gs_prio;
1393 int es_prio;
1394 int num_ps_gprs;
1395 int num_vs_gprs;
1396 int num_gs_gprs;
1397 int num_es_gprs;
1398 int num_temp_gprs;
1399 int num_ps_threads;
1400 int num_vs_threads;
1401 int num_gs_threads;
1402 int num_es_threads;
1403 int num_ps_stack_entries;
1404 int num_vs_stack_entries;
1405 int num_gs_stack_entries;
1406 int num_es_stack_entries;
1407
1408 R600_STATECHANGE(context, sq);
1409
1410 // SQ
1411 ps_prio = 0;
1412 vs_prio = 1;
1413 gs_prio = 2;
1414 es_prio = 3;
1415 switch (context->radeon.radeonScreen->chip_family) {
1416 case CHIP_FAMILY_R600:
1417 num_ps_gprs = 192;
1418 num_vs_gprs = 56;
1419 num_temp_gprs = 4;
1420 num_gs_gprs = 0;
1421 num_es_gprs = 0;
1422 num_ps_threads = 136;
1423 num_vs_threads = 48;
1424 num_gs_threads = 4;
1425 num_es_threads = 4;
1426 num_ps_stack_entries = 128;
1427 num_vs_stack_entries = 128;
1428 num_gs_stack_entries = 0;
1429 num_es_stack_entries = 0;
1430 break;
1431 case CHIP_FAMILY_RV630:
1432 case CHIP_FAMILY_RV635:
1433 num_ps_gprs = 84;
1434 num_vs_gprs = 36;
1435 num_temp_gprs = 4;
1436 num_gs_gprs = 0;
1437 num_es_gprs = 0;
1438 num_ps_threads = 144;
1439 num_vs_threads = 40;
1440 num_gs_threads = 4;
1441 num_es_threads = 4;
1442 num_ps_stack_entries = 40;
1443 num_vs_stack_entries = 40;
1444 num_gs_stack_entries = 32;
1445 num_es_stack_entries = 16;
1446 break;
1447 case CHIP_FAMILY_RV610:
1448 case CHIP_FAMILY_RV620:
1449 case CHIP_FAMILY_RS780:
1450 case CHIP_FAMILY_RS880:
1451 default:
1452 num_ps_gprs = 84;
1453 num_vs_gprs = 36;
1454 num_temp_gprs = 4;
1455 num_gs_gprs = 0;
1456 num_es_gprs = 0;
1457 num_ps_threads = 136;
1458 num_vs_threads = 48;
1459 num_gs_threads = 4;
1460 num_es_threads = 4;
1461 num_ps_stack_entries = 40;
1462 num_vs_stack_entries = 40;
1463 num_gs_stack_entries = 32;
1464 num_es_stack_entries = 16;
1465 break;
1466 case CHIP_FAMILY_RV670:
1467 num_ps_gprs = 144;
1468 num_vs_gprs = 40;
1469 num_temp_gprs = 4;
1470 num_gs_gprs = 0;
1471 num_es_gprs = 0;
1472 num_ps_threads = 136;
1473 num_vs_threads = 48;
1474 num_gs_threads = 4;
1475 num_es_threads = 4;
1476 num_ps_stack_entries = 40;
1477 num_vs_stack_entries = 40;
1478 num_gs_stack_entries = 32;
1479 num_es_stack_entries = 16;
1480 break;
1481 case CHIP_FAMILY_RV770:
1482 num_ps_gprs = 192;
1483 num_vs_gprs = 56;
1484 num_temp_gprs = 4;
1485 num_gs_gprs = 0;
1486 num_es_gprs = 0;
1487 num_ps_threads = 188;
1488 num_vs_threads = 60;
1489 num_gs_threads = 0;
1490 num_es_threads = 0;
1491 num_ps_stack_entries = 256;
1492 num_vs_stack_entries = 256;
1493 num_gs_stack_entries = 0;
1494 num_es_stack_entries = 0;
1495 break;
1496 case CHIP_FAMILY_RV730:
1497 case CHIP_FAMILY_RV740:
1498 num_ps_gprs = 84;
1499 num_vs_gprs = 36;
1500 num_temp_gprs = 4;
1501 num_gs_gprs = 0;
1502 num_es_gprs = 0;
1503 num_ps_threads = 188;
1504 num_vs_threads = 60;
1505 num_gs_threads = 0;
1506 num_es_threads = 0;
1507 num_ps_stack_entries = 128;
1508 num_vs_stack_entries = 128;
1509 num_gs_stack_entries = 0;
1510 num_es_stack_entries = 0;
1511 break;
1512 case CHIP_FAMILY_RV710:
1513 num_ps_gprs = 192;
1514 num_vs_gprs = 56;
1515 num_temp_gprs = 4;
1516 num_gs_gprs = 0;
1517 num_es_gprs = 0;
1518 num_ps_threads = 144;
1519 num_vs_threads = 48;
1520 num_gs_threads = 0;
1521 num_es_threads = 0;
1522 num_ps_stack_entries = 128;
1523 num_vs_stack_entries = 128;
1524 num_gs_stack_entries = 0;
1525 num_es_stack_entries = 0;
1526 break;
1527 }
1528
1529 r700->sq_config.SQ_CONFIG.u32All = 0;
1530 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1531 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1532 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1533 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1534 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1535 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1536 else
1537 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1538 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1539 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1540 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1541 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1542 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1543 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1544
1545 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1546 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1547 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1548 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1549 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1550
1551 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1552 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1553 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1554
1555 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1556 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1557 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1558 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1559 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1560 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1561 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1562 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1563 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1564
1565 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1566 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1567 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1568 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1569 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1570
1571 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1572 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1573 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1574 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1575 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1576
1577 }
1578
1579 /**
1580 * Calculate initial hardware state and register state functions.
1581 * Assumes that the command buffer and state atoms have been
1582 * initialized already.
1583 */
1584 void r700InitState(GLcontext * ctx) //-------------------
1585 {
1586 context_t *context = R700_CONTEXT(ctx);
1587 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1588 int id = 0;
1589
1590 radeon_firevertices(&context->radeon);
1591
1592 r700->TA_CNTL_AUX.u32All = 0;
1593 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1594 r700->VC_ENHANCE.u32All = 0;
1595 r700->DB_WATERMARKS.u32All = 0;
1596 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1597 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1598 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1599 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1600 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1601 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1602 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1603 r700->DB_DEBUG.u32All = 0x82000000;
1604 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1605 } else {
1606 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1607 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1608 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1609 }
1610
1611 /* Turn off vgt reuse */
1612 r700->VGT_REUSE_OFF.u32All = 0;
1613 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1614
1615 /* Specify offsetting and clamp values for vertices */
1616 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1617 r700->VGT_MIN_VTX_INDX.u32All = 0;
1618 r700->VGT_INDX_OFFSET.u32All = 0;
1619
1620 /* default shader connections. */
1621 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1622 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1623 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1624 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1625
1626 r700->SPI_THREAD_GROUPING.u32All = 0;
1627 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1628 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1629
1630 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1631 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1632 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1633
1634 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1635 r700->PA_SC_EDGERULE.u32All = 0;
1636 else
1637 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1638
1639 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1640 r700->PA_SC_MODE_CNTL.u32All = 0;
1641 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1642 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1643 } else {
1644 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1645 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1646 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1647 }
1648
1649 /* Do scale XY and Z by 1/W0. */
1650 r700->bEnablePerspective = GL_TRUE;
1651 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1652 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1653 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1654
1655 /* Enable viewport scaling for all three axis */
1656 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1657 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1658 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1659 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1660 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1661 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1662
1663 /* GL uses last vtx for flat shading components */
1664 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1665
1666 /* Set up vertex control */
1667 r700->PA_SU_VTX_CNTL.u32All = 0;
1668 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1669 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1670 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1671 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1672
1673 /* to 1.0 = no guard band */
1674 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1675 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1676 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1677 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1678
1679 /* Enable all samples for multi-sample anti-aliasing */
1680 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1681 /* Turn off AA */
1682 r700->PA_SC_AA_CONFIG.u32All = 0;
1683
1684 r700->SX_MISC.u32All = 0;
1685
1686 r700InitSQConfig(ctx);
1687
1688 r700ColorMask(ctx,
1689 ctx->Color.ColorMask[RCOMP],
1690 ctx->Color.ColorMask[GCOMP],
1691 ctx->Color.ColorMask[BCOMP],
1692 ctx->Color.ColorMask[ACOMP]);
1693
1694 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1695 r700DepthMask(ctx, ctx->Depth.Mask);
1696 r700DepthFunc(ctx, ctx->Depth.Func);
1697 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1698
1699 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1700
1701 r700->DB_RENDER_CONTROL.u32All = 0;
1702 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1703 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1704 r700->DB_RENDER_OVERRIDE.u32All = 0;
1705 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1706 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1707 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1708 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1709 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1710
1711 r700->DB_ALPHA_TO_MASK.u32All = 0;
1712 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1713 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1714 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1715 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1716
1717 /* stencil */
1718 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1719 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1720 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1721 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1722 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1723 ctx->Stencil.ZFailFunc[0],
1724 ctx->Stencil.ZPassFunc[0]);
1725
1726 r700UpdateCulling(ctx);
1727
1728 r700SetBlendState(ctx);
1729 r700SetLogicOpState(ctx);
1730
1731 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1732 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1733
1734 r700PointSize(ctx, 1.0);
1735
1736 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1737 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1738
1739 r700LineWidth(ctx, 1.0);
1740
1741 r700->PA_SC_LINE_CNTL.u32All = 0;
1742 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1743 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1744
1745 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1746 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1747 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1748 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1749 ctx->Polygon.OffsetUnits);
1750 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1751 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1752 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1753
1754 /* CB */
1755 r700BlendColor(ctx, ctx->Color.BlendColor);
1756
1757 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1758 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1759 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1760 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1761 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1762 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1763 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1764
1765 /* Disable color compares */
1766 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1767 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1768 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1769 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1770 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1771 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1772
1773 /* Zero out source */
1774 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1775
1776 /* Put a compare color in for error checking */
1777 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1778
1779 /* Set up color compare mask */
1780 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1781
1782 /* screen/window/view */
1783 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask);
1784
1785 context->radeon.hw.all_dirty = GL_TRUE;
1786
1787 }
1788
1789 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1790 {
1791 functions->UpdateState = r700InvalidateState;
1792 functions->AlphaFunc = r700AlphaFunc;
1793 functions->BlendColor = r700BlendColor;
1794 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1795 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1796 functions->Enable = r700Enable;
1797 functions->ColorMask = r700ColorMask;
1798 functions->DepthFunc = r700DepthFunc;
1799 functions->DepthMask = r700DepthMask;
1800 functions->CullFace = r700CullFace;
1801 functions->Fogfv = r700Fogfv;
1802 functions->FrontFace = r700FrontFace;
1803 functions->ShadeModel = r700ShadeModel;
1804 functions->LogicOpcode = r700LogicOpcode;
1805
1806 /* ARB_point_parameters */
1807 functions->PointParameterfv = r700PointParameter;
1808
1809 /* Stencil related */
1810 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1811 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1812 functions->StencilOpSeparate = r700StencilOpSeparate;
1813
1814 /* Viewport related */
1815 functions->Viewport = r700Viewport;
1816 functions->DepthRange = r700DepthRange;
1817 functions->PointSize = r700PointSize;
1818 functions->LineWidth = r700LineWidth;
1819 functions->LineStipple = r700LineStipple;
1820
1821 functions->PolygonOffset = r700PolygonOffset;
1822 functions->PolygonMode = r700PolygonMode;
1823
1824 functions->RenderMode = r700RenderMode;
1825
1826 functions->ClipPlane = r700ClipPlane;
1827
1828 functions->Scissor = radeonScissor;
1829
1830 functions->DrawBuffer = radeonDrawBuffer;
1831 functions->ReadBuffer = radeonReadBuffer;
1832
1833 }
1834