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mesa: implement per-buffer color masking
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49
50 #include "r600_context.h"
51
52 #include "r700_state.h"
53
54 #include "r700_fragprog.h"
55 #include "r700_vertprog.h"
56
57 void r600UpdateTextureState(GLcontext * ctx);
58 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
59 static void r700UpdatePolygonMode(GLcontext * ctx);
60 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
61 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
62
63 void r700UpdateShaders(GLcontext * ctx)
64 {
65 context_t *context = R700_CONTEXT(ctx);
66
67 /* should only happenen once, just after context is created */
68 /* TODO: shouldn't we fallback to sw here? */
69 if (!ctx->FragmentProgram._Current) {
70 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
71 return;
72 }
73
74 r700SelectFragmentShader(ctx);
75
76 r700SelectVertexShader(ctx);
77 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
78 context->radeon.NewGLState = 0;
79 }
80
81 /*
82 * To correctly position primitives:
83 */
84 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
85 {
86 context_t *context = R700_CONTEXT(ctx);
87 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
88 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
89 GLfloat xoffset = (GLfloat) dPriv->x;
90 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
91 const GLfloat *v = ctx->Viewport._WindowMap.m;
92 int id = 0;
93
94 GLfloat tx = v[MAT_TX] + xoffset;
95 GLfloat ty = (-v[MAT_TY]) + yoffset;
96
97 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
98 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
99 /* Note: this should also modify whatever data the context reset
100 * code uses...
101 */
102 R600_STATECHANGE(context, vpt);
103 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
104 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
105 }
106
107 radeonUpdateScissor(ctx);
108 }
109
110 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
111 {
112 struct r700_fragment_program *fp =
113 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
114 struct gl_program_parameter_list *paramList;
115
116 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
117 return;
118
119 if (!ctx->FragmentProgram._Current || !fp)
120 return;
121
122 paramList = ctx->FragmentProgram._Current->Base.Parameters;
123
124 if (!paramList)
125 return;
126
127 _mesa_load_state_parameters(ctx, paramList);
128
129 }
130
131 /**
132 * Called by Mesa after an internal state update.
133 */
134 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
135 {
136 context_t *context = R700_CONTEXT(ctx);
137
138 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
139
140 _swrast_InvalidateState(ctx, new_state);
141 _swsetup_InvalidateState(ctx, new_state);
142 _vbo_InvalidateState(ctx, new_state);
143 _tnl_InvalidateState(ctx, new_state);
144 _ae_invalidate_state(ctx, new_state);
145
146 if (new_state & _NEW_BUFFERS) {
147 _mesa_update_framebuffer(ctx);
148 /* this updates the DrawBuffer's Width/Height if it's a FBO */
149 _mesa_update_draw_buffer_bounds(ctx);
150
151 R600_STATECHANGE(context, cb_target);
152 R600_STATECHANGE(context, db_target);
153 }
154
155 if (new_state & (_NEW_LIGHT)) {
156 R600_STATECHANGE(context, su);
157 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
158 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
159 else
160 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
161 }
162
163 r700UpdateStateParameters(ctx, new_state);
164
165 R600_STATECHANGE(context, cl);
166 R600_STATECHANGE(context, spi);
167
168 if(GL_TRUE == r700->bEnablePerspective)
169 {
170 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
171 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
172 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
173
174 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
175
176 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
177 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
178 }
179 else
180 {
181 /* For orthogonal case. */
182 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
183 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
184
185 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
186
187 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
188 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
189 }
190
191 context->radeon.NewGLState |= new_state;
192 }
193
194 static void r700SetDBRenderState(GLcontext * ctx)
195 {
196 context_t *context = R700_CONTEXT(ctx);
197 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
198 struct r700_fragment_program *fp = (struct r700_fragment_program *)
199 (ctx->FragmentProgram._Current);
200
201 R600_STATECHANGE(context, db);
202
203 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
204 SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask);
205 /* XXX need to enable htile for hiz/s */
206 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
207 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
208 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
209
210 if (context->radeon.query.current)
211 {
212 SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
213 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
214 {
215 SETbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
216 }
217 }
218 else
219 {
220 CLEARbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
221 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
222 {
223 CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
224 }
225 }
226
227 if (fp)
228 {
229 if (fp->r700Shader.killIsUsed)
230 {
231 SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
232 }
233 else
234 {
235 CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
236 }
237
238 if (fp->r700Shader.depthIsExported)
239 {
240 SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
241 }
242 else
243 {
244 CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
245 }
246 }
247 }
248
249 void r700UpdateShaderStates(GLcontext * ctx)
250 {
251 r700SetDBRenderState(ctx);
252 r600UpdateTextureState(ctx);
253 }
254
255 static void r700SetDepthState(GLcontext * ctx)
256 {
257 context_t *context = R700_CONTEXT(ctx);
258 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
259
260 R600_STATECHANGE(context, db);
261
262 if (ctx->Depth.Test)
263 {
264 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
265 if (ctx->Depth.Mask)
266 {
267 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
268 }
269 else
270 {
271 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
272 }
273
274 switch (ctx->Depth.Func)
275 {
276 case GL_NEVER:
277 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
278 ZFUNC_shift, ZFUNC_mask);
279 break;
280 case GL_LESS:
281 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
282 ZFUNC_shift, ZFUNC_mask);
283 break;
284 case GL_EQUAL:
285 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
286 ZFUNC_shift, ZFUNC_mask);
287 break;
288 case GL_LEQUAL:
289 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
290 ZFUNC_shift, ZFUNC_mask);
291 break;
292 case GL_GREATER:
293 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
294 ZFUNC_shift, ZFUNC_mask);
295 break;
296 case GL_NOTEQUAL:
297 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
298 ZFUNC_shift, ZFUNC_mask);
299 break;
300 case GL_GEQUAL:
301 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
302 ZFUNC_shift, ZFUNC_mask);
303 break;
304 case GL_ALWAYS:
305 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
306 ZFUNC_shift, ZFUNC_mask);
307 break;
308 default:
309 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
310 ZFUNC_shift, ZFUNC_mask);
311 break;
312 }
313 }
314 else
315 {
316 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
317 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
318 }
319 }
320
321 static void r700SetAlphaState(GLcontext * ctx)
322 {
323 context_t *context = R700_CONTEXT(ctx);
324 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
325 uint32_t alpha_func = REF_ALWAYS;
326 GLboolean really_enabled = ctx->Color.AlphaEnabled;
327
328 R600_STATECHANGE(context, sx);
329
330 switch (ctx->Color.AlphaFunc) {
331 case GL_NEVER:
332 alpha_func = REF_NEVER;
333 break;
334 case GL_LESS:
335 alpha_func = REF_LESS;
336 break;
337 case GL_EQUAL:
338 alpha_func = REF_EQUAL;
339 break;
340 case GL_LEQUAL:
341 alpha_func = REF_LEQUAL;
342 break;
343 case GL_GREATER:
344 alpha_func = REF_GREATER;
345 break;
346 case GL_NOTEQUAL:
347 alpha_func = REF_NOTEQUAL;
348 break;
349 case GL_GEQUAL:
350 alpha_func = REF_GEQUAL;
351 break;
352 case GL_ALWAYS:
353 /*alpha_func = REF_ALWAYS; */
354 really_enabled = GL_FALSE;
355 break;
356 }
357
358 if (really_enabled) {
359 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
360 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
361 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
362 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
363 } else {
364 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
365 }
366
367 }
368
369 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
370 {
371 (void)func;
372 (void)ref;
373 r700SetAlphaState(ctx);
374 }
375
376
377 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
378 {
379 context_t *context = R700_CONTEXT(ctx);
380 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
381
382 R600_STATECHANGE(context, blnd_clr);
383
384 r700->CB_BLEND_RED.f32All = cf[0];
385 r700->CB_BLEND_GREEN.f32All = cf[1];
386 r700->CB_BLEND_BLUE.f32All = cf[2];
387 r700->CB_BLEND_ALPHA.f32All = cf[3];
388 }
389
390 static int blend_factor(GLenum factor, GLboolean is_src)
391 {
392 switch (factor) {
393 case GL_ZERO:
394 return BLEND_ZERO;
395 break;
396 case GL_ONE:
397 return BLEND_ONE;
398 break;
399 case GL_DST_COLOR:
400 return BLEND_DST_COLOR;
401 break;
402 case GL_ONE_MINUS_DST_COLOR:
403 return BLEND_ONE_MINUS_DST_COLOR;
404 break;
405 case GL_SRC_COLOR:
406 return BLEND_SRC_COLOR;
407 break;
408 case GL_ONE_MINUS_SRC_COLOR:
409 return BLEND_ONE_MINUS_SRC_COLOR;
410 break;
411 case GL_SRC_ALPHA:
412 return BLEND_SRC_ALPHA;
413 break;
414 case GL_ONE_MINUS_SRC_ALPHA:
415 return BLEND_ONE_MINUS_SRC_ALPHA;
416 break;
417 case GL_DST_ALPHA:
418 return BLEND_DST_ALPHA;
419 break;
420 case GL_ONE_MINUS_DST_ALPHA:
421 return BLEND_ONE_MINUS_DST_ALPHA;
422 break;
423 case GL_SRC_ALPHA_SATURATE:
424 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
425 break;
426 case GL_CONSTANT_COLOR:
427 return BLEND_CONSTANT_COLOR;
428 break;
429 case GL_ONE_MINUS_CONSTANT_COLOR:
430 return BLEND_ONE_MINUS_CONSTANT_COLOR;
431 break;
432 case GL_CONSTANT_ALPHA:
433 return BLEND_CONSTANT_ALPHA;
434 break;
435 case GL_ONE_MINUS_CONSTANT_ALPHA:
436 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
437 break;
438 default:
439 fprintf(stderr, "unknown blend factor %x\n", factor);
440 return (is_src) ? BLEND_ONE : BLEND_ZERO;
441 break;
442 }
443 }
444
445 static void r700SetBlendState(GLcontext * ctx)
446 {
447 context_t *context = R700_CONTEXT(ctx);
448 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
449 int id = 0;
450 uint32_t blend_reg = 0, eqn, eqnA;
451
452 R600_STATECHANGE(context, blnd);
453
454 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
455 SETfield(blend_reg,
456 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
457 SETfield(blend_reg,
458 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
459 SETfield(blend_reg,
460 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
461 SETfield(blend_reg,
462 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
463 SETfield(blend_reg,
464 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
465 SETfield(blend_reg,
466 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
467 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
468 r700->CB_BLEND_CONTROL.u32All = blend_reg;
469 else
470 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
471 return;
472 }
473
474 SETfield(blend_reg,
475 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
476 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
477 SETfield(blend_reg,
478 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
479 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
480
481 switch (ctx->Color.BlendEquationRGB) {
482 case GL_FUNC_ADD:
483 eqn = COMB_DST_PLUS_SRC;
484 break;
485 case GL_FUNC_SUBTRACT:
486 eqn = COMB_SRC_MINUS_DST;
487 break;
488 case GL_FUNC_REVERSE_SUBTRACT:
489 eqn = COMB_DST_MINUS_SRC;
490 break;
491 case GL_MIN:
492 eqn = COMB_MIN_DST_SRC;
493 SETfield(blend_reg,
494 BLEND_ONE,
495 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
496 SETfield(blend_reg,
497 BLEND_ONE,
498 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
499 break;
500 case GL_MAX:
501 eqn = COMB_MAX_DST_SRC;
502 SETfield(blend_reg,
503 BLEND_ONE,
504 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
505 SETfield(blend_reg,
506 BLEND_ONE,
507 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
508 break;
509
510 default:
511 fprintf(stderr,
512 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
513 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
514 return;
515 }
516 SETfield(blend_reg,
517 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
518
519 SETfield(blend_reg,
520 blend_factor(ctx->Color.BlendSrcA, GL_TRUE),
521 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
522 SETfield(blend_reg,
523 blend_factor(ctx->Color.BlendDstA, GL_FALSE),
524 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
525
526 switch (ctx->Color.BlendEquationA) {
527 case GL_FUNC_ADD:
528 eqnA = COMB_DST_PLUS_SRC;
529 break;
530 case GL_FUNC_SUBTRACT:
531 eqnA = COMB_SRC_MINUS_DST;
532 break;
533 case GL_FUNC_REVERSE_SUBTRACT:
534 eqnA = COMB_DST_MINUS_SRC;
535 break;
536 case GL_MIN:
537 eqnA = COMB_MIN_DST_SRC;
538 SETfield(blend_reg,
539 BLEND_ONE,
540 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
541 SETfield(blend_reg,
542 BLEND_ONE,
543 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
544 break;
545 case GL_MAX:
546 eqnA = COMB_MAX_DST_SRC;
547 SETfield(blend_reg,
548 BLEND_ONE,
549 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
550 SETfield(blend_reg,
551 BLEND_ONE,
552 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
553 break;
554 default:
555 fprintf(stderr,
556 "[%s:%u] Invalid A blend equation (0x%04x).\n",
557 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
558 return;
559 }
560
561 SETfield(blend_reg,
562 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
563
564 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
565
566 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
567 r700->CB_BLEND_CONTROL.u32All = blend_reg;
568 else {
569 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
570 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
571 }
572 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
573 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
574
575 }
576
577 static void r700BlendEquationSeparate(GLcontext * ctx,
578 GLenum modeRGB, GLenum modeA) //-----------------
579 {
580 r700SetBlendState(ctx);
581 }
582
583 static void r700BlendFuncSeparate(GLcontext * ctx,
584 GLenum sfactorRGB, GLenum dfactorRGB,
585 GLenum sfactorA, GLenum dfactorA) //------------------------
586 {
587 r700SetBlendState(ctx);
588 }
589
590 /**
591 * Translate LogicOp enums into hardware representation.
592 */
593 static GLuint translate_logicop(GLenum logicop)
594 {
595 switch (logicop) {
596 case GL_CLEAR:
597 return 0x00;
598 case GL_SET:
599 return 0xff;
600 case GL_COPY:
601 return 0xcc;
602 case GL_COPY_INVERTED:
603 return 0x33;
604 case GL_NOOP:
605 return 0xaa;
606 case GL_INVERT:
607 return 0x55;
608 case GL_AND:
609 return 0x88;
610 case GL_NAND:
611 return 0x77;
612 case GL_OR:
613 return 0xee;
614 case GL_NOR:
615 return 0x11;
616 case GL_XOR:
617 return 0x66;
618 case GL_EQUIV:
619 return 0xaa;
620 case GL_AND_REVERSE:
621 return 0x44;
622 case GL_AND_INVERTED:
623 return 0x22;
624 case GL_OR_REVERSE:
625 return 0xdd;
626 case GL_OR_INVERTED:
627 return 0xbb;
628 default:
629 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
630 return 0xcc;
631 }
632 }
633
634 /**
635 * Used internally to update the r300->hw hardware state to match the
636 * current OpenGL state.
637 */
638 static void r700SetLogicOpState(GLcontext *ctx)
639 {
640 context_t *context = R700_CONTEXT(ctx);
641 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
642
643 R600_STATECHANGE(context, blnd);
644
645 if (RGBA_LOGICOP_ENABLED(ctx))
646 SETfield(r700->CB_COLOR_CONTROL.u32All,
647 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
648 else
649 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
650 }
651
652 /**
653 * Called by Mesa when an application program changes the LogicOp state
654 * via glLogicOp.
655 */
656 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
657 {
658 if (RGBA_LOGICOP_ENABLED(ctx))
659 r700SetLogicOpState(ctx);
660 }
661
662 static void r700UpdateCulling(GLcontext * ctx)
663 {
664 context_t *context = R700_CONTEXT(ctx);
665 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
666
667 R600_STATECHANGE(context, su);
668
669 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
670 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
671 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
672
673 if (ctx->Polygon.CullFlag)
674 {
675 switch (ctx->Polygon.CullFaceMode)
676 {
677 case GL_FRONT:
678 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
679 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
680 break;
681 case GL_BACK:
682 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
683 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
684 break;
685 case GL_FRONT_AND_BACK:
686 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
687 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
688 break;
689 default:
690 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
691 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
692 break;
693 }
694 }
695
696 switch (ctx->Polygon.FrontFace)
697 {
698 case GL_CW:
699 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
700 break;
701 case GL_CCW:
702 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
703 break;
704 default:
705 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
706 break;
707 }
708
709 /* Winding is inverted when rendering to FBO */
710 if (ctx->DrawBuffer && ctx->DrawBuffer->Name)
711 r700->PA_SU_SC_MODE_CNTL.u32All ^= FACE_bit;
712 }
713
714 static void r700UpdateLineStipple(GLcontext * ctx)
715 {
716 context_t *context = R700_CONTEXT(ctx);
717 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
718
719 R600_STATECHANGE(context, sc);
720
721 if (ctx->Line.StippleFlag)
722 {
723 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
724 }
725 else
726 {
727 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
728 }
729 }
730
731 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
732 {
733 context_t *context = R700_CONTEXT(ctx);
734
735 switch (cap) {
736 case GL_TEXTURE_1D:
737 case GL_TEXTURE_2D:
738 case GL_TEXTURE_3D:
739 /* empty */
740 break;
741 case GL_FOG:
742 /* empty */
743 break;
744 case GL_ALPHA_TEST:
745 r700SetAlphaState(ctx);
746 break;
747 case GL_COLOR_LOGIC_OP:
748 r700SetLogicOpState(ctx);
749 /* fall-through, because logic op overrides blending */
750 case GL_BLEND:
751 r700SetBlendState(ctx);
752 break;
753 case GL_CLIP_PLANE0:
754 case GL_CLIP_PLANE1:
755 case GL_CLIP_PLANE2:
756 case GL_CLIP_PLANE3:
757 case GL_CLIP_PLANE4:
758 case GL_CLIP_PLANE5:
759 r700SetClipPlaneState(ctx, cap, state);
760 break;
761 case GL_DEPTH_TEST:
762 r700SetDepthState(ctx);
763 break;
764 case GL_STENCIL_TEST:
765 r700SetStencilState(ctx, state);
766 break;
767 case GL_CULL_FACE:
768 r700UpdateCulling(ctx);
769 break;
770 case GL_POLYGON_OFFSET_POINT:
771 case GL_POLYGON_OFFSET_LINE:
772 case GL_POLYGON_OFFSET_FILL:
773 r700SetPolygonOffsetState(ctx, state);
774 break;
775 case GL_SCISSOR_TEST:
776 radeon_firevertices(&context->radeon);
777 context->radeon.state.scissor.enabled = state;
778 radeonUpdateScissor(ctx);
779 break;
780 case GL_LINE_STIPPLE:
781 r700UpdateLineStipple(ctx);
782 break;
783 default:
784 break;
785 }
786
787 }
788
789 /**
790 * Handle glColorMask()
791 */
792 static void r700ColorMask(GLcontext * ctx,
793 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
794 {
795 context_t *context = R700_CONTEXT(ctx);
796 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
797 unsigned int mask = ((r ? 1 : 0) |
798 (g ? 2 : 0) |
799 (b ? 4 : 0) |
800 (a ? 8 : 0));
801
802 if (mask != r700->CB_TARGET_MASK.u32All) {
803 R600_STATECHANGE(context, cb);
804 SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
805 }
806 }
807
808 /**
809 * Change the depth testing function.
810 *
811 * \note Mesa already filters redundant calls to this function.
812 */
813 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
814 {
815 r700SetDepthState(ctx);
816 }
817
818 /**
819 * Enable/Disable depth writing.
820 *
821 * \note Mesa already filters redundant calls to this function.
822 */
823 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
824 {
825 r700SetDepthState(ctx);
826 }
827
828 /**
829 * Change the culling mode.
830 *
831 * \note Mesa already filters redundant calls to this function.
832 */
833 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
834 {
835 r700UpdateCulling(ctx);
836 }
837
838 /* =============================================================
839 * Fog
840 */
841 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
842 {
843 }
844
845 /**
846 * Change the polygon orientation.
847 *
848 * \note Mesa already filters redundant calls to this function.
849 */
850 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
851 {
852 r700UpdateCulling(ctx);
853 r700UpdatePolygonMode(ctx);
854 }
855
856 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
857 {
858 context_t *context = R700_CONTEXT(ctx);
859 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
860
861 R600_STATECHANGE(context, spi);
862
863 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
864 switch (mode) {
865 case GL_FLAT:
866 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
867 break;
868 case GL_SMOOTH:
869 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
870 break;
871 default:
872 return;
873 }
874 }
875
876 /* =============================================================
877 * Point state
878 */
879 static void r700PointSize(GLcontext * ctx, GLfloat size)
880 {
881 context_t *context = R700_CONTEXT(ctx);
882 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
883
884 R600_STATECHANGE(context, su);
885
886 /* We need to clamp to user defined range here, because
887 * the HW clamping happens only for per vertex point size. */
888 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
889
890 /* same size limits for AA, non-AA points */
891 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
892
893 /* format is 12.4 fixed point */
894 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
895 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
896 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
897 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
898
899 }
900
901 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
902 {
903 context_t *context = R700_CONTEXT(ctx);
904 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
905
906 R600_STATECHANGE(context, su);
907
908 /* format is 12.4 fixed point */
909 switch (pname) {
910 case GL_POINT_SIZE_MIN:
911 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
912 MIN_SIZE_shift, MIN_SIZE_mask);
913 break;
914 case GL_POINT_SIZE_MAX:
915 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
916 MAX_SIZE_shift, MAX_SIZE_mask);
917 break;
918 case GL_POINT_DISTANCE_ATTENUATION:
919 break;
920 case GL_POINT_FADE_THRESHOLD_SIZE:
921 break;
922 default:
923 break;
924 }
925 }
926
927 static int translate_stencil_func(int func)
928 {
929 switch (func) {
930 case GL_NEVER:
931 return REF_NEVER;
932 case GL_LESS:
933 return REF_LESS;
934 case GL_EQUAL:
935 return REF_EQUAL;
936 case GL_LEQUAL:
937 return REF_LEQUAL;
938 case GL_GREATER:
939 return REF_GREATER;
940 case GL_NOTEQUAL:
941 return REF_NOTEQUAL;
942 case GL_GEQUAL:
943 return REF_GEQUAL;
944 case GL_ALWAYS:
945 return REF_ALWAYS;
946 }
947 return 0;
948 }
949
950 static int translate_stencil_op(int op)
951 {
952 switch (op) {
953 case GL_KEEP:
954 return STENCIL_KEEP;
955 case GL_ZERO:
956 return STENCIL_ZERO;
957 case GL_REPLACE:
958 return STENCIL_REPLACE;
959 case GL_INCR:
960 return STENCIL_INCR_CLAMP;
961 case GL_DECR:
962 return STENCIL_DECR_CLAMP;
963 case GL_INCR_WRAP_EXT:
964 return STENCIL_INCR_WRAP;
965 case GL_DECR_WRAP_EXT:
966 return STENCIL_DECR_WRAP;
967 case GL_INVERT:
968 return STENCIL_INVERT;
969 default:
970 WARN_ONCE("Do not know how to translate stencil op");
971 return STENCIL_KEEP;
972 }
973 return 0;
974 }
975
976 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
977 {
978 context_t *context = R700_CONTEXT(ctx);
979 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
980 GLboolean hw_stencil = GL_FALSE;
981
982 if (ctx->DrawBuffer) {
983 struct radeon_renderbuffer *rrbStencil
984 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
985 hw_stencil = (rrbStencil && rrbStencil->bo);
986 }
987
988 if (hw_stencil) {
989 R600_STATECHANGE(context, db);
990 if (state) {
991 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
992 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
993 } else
994 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
995 }
996 }
997
998 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
999 GLenum func, GLint ref, GLuint mask) //---------------------
1000 {
1001 context_t *context = R700_CONTEXT(ctx);
1002 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1003 const unsigned back = ctx->Stencil._BackFace;
1004
1005 R600_STATECHANGE(context, stencil);
1006 R600_STATECHANGE(context, db);
1007
1008 //front
1009 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
1010 STENCILREF_shift, STENCILREF_mask);
1011 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
1012 STENCILMASK_shift, STENCILMASK_mask);
1013
1014 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
1015 STENCILFUNC_shift, STENCILFUNC_mask);
1016
1017 //back
1018 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
1019 STENCILREF_BF_shift, STENCILREF_BF_mask);
1020 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
1021 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1022
1023 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1024 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1025
1026 }
1027
1028 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1029 {
1030 context_t *context = R700_CONTEXT(ctx);
1031 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1032 const unsigned back = ctx->Stencil._BackFace;
1033
1034 R600_STATECHANGE(context, stencil);
1035
1036 // front
1037 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1038 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1039
1040 // back
1041 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1042 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1043
1044 }
1045
1046 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1047 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1048 {
1049 context_t *context = R700_CONTEXT(ctx);
1050 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1051 const unsigned back = ctx->Stencil._BackFace;
1052
1053 R600_STATECHANGE(context, db);
1054
1055 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1056 STENCILFAIL_shift, STENCILFAIL_mask);
1057 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1058 STENCILZFAIL_shift, STENCILZFAIL_mask);
1059 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1060 STENCILZPASS_shift, STENCILZPASS_mask);
1061
1062 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1063 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1064 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1065 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1066 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1067 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1068 }
1069
1070 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1071 {
1072 context_t *context = R700_CONTEXT(ctx);
1073 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1074 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1075 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1076 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1077 const GLfloat *v = ctx->Viewport._WindowMap.m;
1078 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1079 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1080 GLfloat y_scale, y_bias;
1081
1082 if (render_to_fbo) {
1083 y_scale = 1.0;
1084 y_bias = 0;
1085 } else {
1086 y_scale = -1.0;
1087 y_bias = yoffset;
1088 }
1089
1090 GLfloat sx = v[MAT_SX];
1091 GLfloat tx = v[MAT_TX] + xoffset;
1092 GLfloat sy = v[MAT_SY] * y_scale;
1093 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1094 GLfloat sz = v[MAT_SZ] * depthScale;
1095 GLfloat tz = v[MAT_TZ] * depthScale;
1096
1097 R600_STATECHANGE(context, vpt);
1098 R600_STATECHANGE(context, cl);
1099
1100 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1101 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1102
1103 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1104 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1105
1106 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1107 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1108
1109 if (ctx->Transform.DepthClamp) {
1110 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
1111 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
1112 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1113 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1114 } else {
1115 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0;
1116 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0;
1117 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1118 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1119 }
1120
1121 r700->viewport[id].enabled = GL_TRUE;
1122
1123 r700SetScissor(context);
1124 }
1125
1126
1127 static void r700Viewport(GLcontext * ctx,
1128 GLint x,
1129 GLint y,
1130 GLsizei width,
1131 GLsizei height) //--------------------
1132 {
1133 r700UpdateWindow(ctx, 0);
1134
1135 radeon_viewport(ctx, x, y, width, height);
1136 }
1137
1138 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1139 {
1140 r700UpdateWindow(ctx, 0);
1141 }
1142
1143 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1144 {
1145 context_t *context = R700_CONTEXT(ctx);
1146 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1147 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1148
1149 R600_STATECHANGE(context, su);
1150
1151 if (lineWidth > 0xFFFF)
1152 lineWidth = 0xFFFF;
1153 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1154 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1155 }
1156
1157 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1158 {
1159 context_t *context = R700_CONTEXT(ctx);
1160 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1161
1162 R600_STATECHANGE(context, sc);
1163
1164 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1165 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1166 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1167 }
1168
1169 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1170 {
1171 context_t *context = R700_CONTEXT(ctx);
1172 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1173
1174 R600_STATECHANGE(context, su);
1175
1176 if (state) {
1177 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1178 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1179 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1180 } else {
1181 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1182 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1183 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1184 }
1185 }
1186
1187 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1188 {
1189 context_t *context = R700_CONTEXT(ctx);
1190 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1191 GLfloat constant = units;
1192 GLchar depth = 0;
1193
1194 R600_STATECHANGE(context, poly);
1195
1196 switch (ctx->Visual.depthBits) {
1197 case 16:
1198 constant *= 4.0;
1199 depth = -16;
1200 break;
1201 case 24:
1202 constant *= 2.0;
1203 depth = -24;
1204 break;
1205 }
1206
1207 factor *= 12.0;
1208 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1209 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1210 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1211 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1212 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1213 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1214 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1215 }
1216
1217 static void r700UpdatePolygonMode(GLcontext * ctx)
1218 {
1219 context_t *context = R700_CONTEXT(ctx);
1220 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1221
1222 R600_STATECHANGE(context, su);
1223
1224 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1225
1226 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1227 if (ctx->Polygon.FrontMode != GL_FILL ||
1228 ctx->Polygon.BackMode != GL_FILL) {
1229 GLenum f, b;
1230
1231 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1232 * correctly by selecting the correct front and back face
1233 */
1234 f = ctx->Polygon.FrontMode;
1235 b = ctx->Polygon.BackMode;
1236
1237 /* Enable polygon mode */
1238 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1239
1240 switch (f) {
1241 case GL_LINE:
1242 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1243 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1244 break;
1245 case GL_POINT:
1246 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1247 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1248 break;
1249 case GL_FILL:
1250 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1251 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1252 break;
1253 }
1254
1255 switch (b) {
1256 case GL_LINE:
1257 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1258 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1259 break;
1260 case GL_POINT:
1261 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1262 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1263 break;
1264 case GL_FILL:
1265 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1266 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1267 break;
1268 }
1269 }
1270 }
1271
1272 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1273 {
1274 (void)face;
1275 (void)mode;
1276
1277 r700UpdatePolygonMode(ctx);
1278 }
1279
1280 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1281 {
1282 }
1283
1284 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1285 {
1286 context_t *context = R700_CONTEXT(ctx);
1287 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1288 GLint p;
1289 GLint *ip;
1290
1291 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1292 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1293
1294 R600_STATECHANGE(context, ucp);
1295
1296 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1297 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1298 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1299 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1300 }
1301
1302 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1303 {
1304 context_t *context = R700_CONTEXT(ctx);
1305 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1306 GLuint p;
1307
1308 p = cap - GL_CLIP_PLANE0;
1309
1310 R600_STATECHANGE(context, cl);
1311
1312 if (state) {
1313 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1314 r700->ucp[p].enabled = GL_TRUE;
1315 r700ClipPlane(ctx, cap, NULL);
1316 } else {
1317 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1318 r700->ucp[p].enabled = GL_FALSE;
1319 }
1320 }
1321
1322 void r700SetScissor(context_t *context) //---------------
1323 {
1324 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1325 unsigned x1, y1, x2, y2;
1326 int id = 0;
1327 struct radeon_renderbuffer *rrb;
1328
1329 rrb = radeon_get_colorbuffer(&context->radeon);
1330 if (!rrb || !rrb->bo) {
1331 return;
1332 }
1333 if (context->radeon.state.scissor.enabled) {
1334 x1 = context->radeon.state.scissor.rect.x1;
1335 y1 = context->radeon.state.scissor.rect.y1;
1336 x2 = context->radeon.state.scissor.rect.x2;
1337 y2 = context->radeon.state.scissor.rect.y2;
1338 /* r600 has exclusive BR scissors */
1339 if (context->radeon.radeonScreen->kernel_mm) {
1340 x2++;
1341 y2++;
1342 }
1343 } else {
1344 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1345 x1 = 0;
1346 y1 = 0;
1347 x2 = rrb->base.Width;
1348 y2 = rrb->base.Height;
1349 } else {
1350 x1 = rrb->dPriv->x;
1351 y1 = rrb->dPriv->y;
1352 x2 = rrb->dPriv->x + rrb->dPriv->w;
1353 y2 = rrb->dPriv->y + rrb->dPriv->h;
1354 }
1355 }
1356
1357 R600_STATECHANGE(context, scissor);
1358
1359 /* screen */
1360 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1361 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1362 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1363 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1364 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1365
1366 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1367 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1368 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1369 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1370
1371 /* window */
1372 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1373 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1374 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1375 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1376 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1377
1378 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1379 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1380 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1381 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1382
1383
1384 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1385 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1386 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1387 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1388 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1389 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1390 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1391 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1392
1393 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1394 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1395 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1396 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1397 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1398 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1399
1400 /* more....2d clip */
1401 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1402 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1403 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1404 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1405 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1406 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1407 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1408 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1409 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1410
1411 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1412 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1413 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1414 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1415 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1416 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1417 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1418 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1419 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1420
1421 r700->viewport[id].enabled = GL_TRUE;
1422 }
1423
1424 static void r700InitSQConfig(GLcontext * ctx)
1425 {
1426 context_t *context = R700_CONTEXT(ctx);
1427 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1428 int ps_prio;
1429 int vs_prio;
1430 int gs_prio;
1431 int es_prio;
1432 int num_ps_gprs;
1433 int num_vs_gprs;
1434 int num_gs_gprs;
1435 int num_es_gprs;
1436 int num_temp_gprs;
1437 int num_ps_threads;
1438 int num_vs_threads;
1439 int num_gs_threads;
1440 int num_es_threads;
1441 int num_ps_stack_entries;
1442 int num_vs_stack_entries;
1443 int num_gs_stack_entries;
1444 int num_es_stack_entries;
1445
1446 R600_STATECHANGE(context, sq);
1447
1448 // SQ
1449 ps_prio = 0;
1450 vs_prio = 1;
1451 gs_prio = 2;
1452 es_prio = 3;
1453 switch (context->radeon.radeonScreen->chip_family) {
1454 case CHIP_FAMILY_R600:
1455 num_ps_gprs = 192;
1456 num_vs_gprs = 56;
1457 num_temp_gprs = 4;
1458 num_gs_gprs = 0;
1459 num_es_gprs = 0;
1460 num_ps_threads = 136;
1461 num_vs_threads = 48;
1462 num_gs_threads = 4;
1463 num_es_threads = 4;
1464 num_ps_stack_entries = 128;
1465 num_vs_stack_entries = 128;
1466 num_gs_stack_entries = 0;
1467 num_es_stack_entries = 0;
1468 break;
1469 case CHIP_FAMILY_RV630:
1470 case CHIP_FAMILY_RV635:
1471 num_ps_gprs = 84;
1472 num_vs_gprs = 36;
1473 num_temp_gprs = 4;
1474 num_gs_gprs = 0;
1475 num_es_gprs = 0;
1476 num_ps_threads = 144;
1477 num_vs_threads = 40;
1478 num_gs_threads = 4;
1479 num_es_threads = 4;
1480 num_ps_stack_entries = 40;
1481 num_vs_stack_entries = 40;
1482 num_gs_stack_entries = 32;
1483 num_es_stack_entries = 16;
1484 break;
1485 case CHIP_FAMILY_RV610:
1486 case CHIP_FAMILY_RV620:
1487 case CHIP_FAMILY_RS780:
1488 case CHIP_FAMILY_RS880:
1489 default:
1490 num_ps_gprs = 84;
1491 num_vs_gprs = 36;
1492 num_temp_gprs = 4;
1493 num_gs_gprs = 0;
1494 num_es_gprs = 0;
1495 num_ps_threads = 136;
1496 num_vs_threads = 48;
1497 num_gs_threads = 4;
1498 num_es_threads = 4;
1499 num_ps_stack_entries = 40;
1500 num_vs_stack_entries = 40;
1501 num_gs_stack_entries = 32;
1502 num_es_stack_entries = 16;
1503 break;
1504 case CHIP_FAMILY_RV670:
1505 num_ps_gprs = 144;
1506 num_vs_gprs = 40;
1507 num_temp_gprs = 4;
1508 num_gs_gprs = 0;
1509 num_es_gprs = 0;
1510 num_ps_threads = 136;
1511 num_vs_threads = 48;
1512 num_gs_threads = 4;
1513 num_es_threads = 4;
1514 num_ps_stack_entries = 40;
1515 num_vs_stack_entries = 40;
1516 num_gs_stack_entries = 32;
1517 num_es_stack_entries = 16;
1518 break;
1519 case CHIP_FAMILY_RV770:
1520 num_ps_gprs = 192;
1521 num_vs_gprs = 56;
1522 num_temp_gprs = 4;
1523 num_gs_gprs = 0;
1524 num_es_gprs = 0;
1525 num_ps_threads = 188;
1526 num_vs_threads = 60;
1527 num_gs_threads = 0;
1528 num_es_threads = 0;
1529 num_ps_stack_entries = 256;
1530 num_vs_stack_entries = 256;
1531 num_gs_stack_entries = 0;
1532 num_es_stack_entries = 0;
1533 break;
1534 case CHIP_FAMILY_RV730:
1535 case CHIP_FAMILY_RV740:
1536 num_ps_gprs = 84;
1537 num_vs_gprs = 36;
1538 num_temp_gprs = 4;
1539 num_gs_gprs = 0;
1540 num_es_gprs = 0;
1541 num_ps_threads = 188;
1542 num_vs_threads = 60;
1543 num_gs_threads = 0;
1544 num_es_threads = 0;
1545 num_ps_stack_entries = 128;
1546 num_vs_stack_entries = 128;
1547 num_gs_stack_entries = 0;
1548 num_es_stack_entries = 0;
1549 break;
1550 case CHIP_FAMILY_RV710:
1551 num_ps_gprs = 192;
1552 num_vs_gprs = 56;
1553 num_temp_gprs = 4;
1554 num_gs_gprs = 0;
1555 num_es_gprs = 0;
1556 num_ps_threads = 144;
1557 num_vs_threads = 48;
1558 num_gs_threads = 0;
1559 num_es_threads = 0;
1560 num_ps_stack_entries = 128;
1561 num_vs_stack_entries = 128;
1562 num_gs_stack_entries = 0;
1563 num_es_stack_entries = 0;
1564 break;
1565 }
1566
1567 r700->sq_config.SQ_CONFIG.u32All = 0;
1568 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1569 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1570 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1571 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1572 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1573 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1574 else
1575 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1576 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1577 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1578 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1579 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1580 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1581 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1582
1583 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1584 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1585 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1586 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1587 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1588
1589 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1590 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1591 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1592
1593 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1594 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1595 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1596 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1597 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1598 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1599 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1600 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1601 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1602
1603 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1604 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1605 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1606 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1607 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1608
1609 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1610 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1611 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1612 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1613 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1614
1615 }
1616
1617 /**
1618 * Calculate initial hardware state and register state functions.
1619 * Assumes that the command buffer and state atoms have been
1620 * initialized already.
1621 */
1622 void r700InitState(GLcontext * ctx) //-------------------
1623 {
1624 context_t *context = R700_CONTEXT(ctx);
1625 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1626 int id = 0;
1627
1628 radeon_firevertices(&context->radeon);
1629
1630 r700->TA_CNTL_AUX.u32All = 0;
1631 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1632 r700->VC_ENHANCE.u32All = 0;
1633 r700->DB_WATERMARKS.u32All = 0;
1634 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1635 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1636 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1637 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1638 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1639 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1640 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1641 r700->DB_DEBUG.u32All = 0x82000000;
1642 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1643 } else {
1644 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1645 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1646 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1647 }
1648
1649 /* Turn off vgt reuse */
1650 r700->VGT_REUSE_OFF.u32All = 0;
1651 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1652
1653 /* Specify offsetting and clamp values for vertices */
1654 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1655 r700->VGT_MIN_VTX_INDX.u32All = 0;
1656 r700->VGT_INDX_OFFSET.u32All = 0;
1657
1658 /* default shader connections. */
1659 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1660 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1661 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1662 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1663
1664 r700->SPI_THREAD_GROUPING.u32All = 0;
1665 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1666 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1667
1668 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1669 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1670 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1671
1672 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1673 r700->PA_SC_EDGERULE.u32All = 0;
1674 else
1675 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1676
1677 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1678 r700->PA_SC_MODE_CNTL.u32All = 0;
1679 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1680 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1681 } else {
1682 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1683 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1684 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1685 }
1686
1687 /* Do scale XY and Z by 1/W0. */
1688 r700->bEnablePerspective = GL_TRUE;
1689 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1690 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1691 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1692
1693 /* Enable viewport scaling for all three axis */
1694 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1695 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1696 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1697 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1698 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1699 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1700
1701 /* GL uses last vtx for flat shading components */
1702 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1703
1704 /* Set up vertex control */
1705 r700->PA_SU_VTX_CNTL.u32All = 0;
1706 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1707 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1708 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1709 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1710
1711 /* to 1.0 = no guard band */
1712 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1713 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1714 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1715 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1716
1717 /* Enable all samples for multi-sample anti-aliasing */
1718 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1719 /* Turn off AA */
1720 r700->PA_SC_AA_CONFIG.u32All = 0;
1721
1722 r700->SX_MISC.u32All = 0;
1723
1724 r700InitSQConfig(ctx);
1725
1726 r700ColorMask(ctx,
1727 ctx->Color.ColorMask[0][RCOMP],
1728 ctx->Color.ColorMask[0][GCOMP],
1729 ctx->Color.ColorMask[0][BCOMP],
1730 ctx->Color.ColorMask[0][ACOMP]);
1731
1732 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1733 r700DepthMask(ctx, ctx->Depth.Mask);
1734 r700DepthFunc(ctx, ctx->Depth.Func);
1735 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1736 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1737 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1738 r700SetDBRenderState(ctx);
1739
1740 r700->DB_ALPHA_TO_MASK.u32All = 0;
1741 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1742 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1743 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1744 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1745
1746 /* stencil */
1747 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1748 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1749 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1750 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1751 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1752 ctx->Stencil.ZFailFunc[0],
1753 ctx->Stencil.ZPassFunc[0]);
1754
1755 r700UpdateCulling(ctx);
1756
1757 r700SetBlendState(ctx);
1758 r700SetLogicOpState(ctx);
1759
1760 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1761 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1762
1763 r700PointSize(ctx, 1.0);
1764
1765 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1766 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1767
1768 r700LineWidth(ctx, 1.0);
1769
1770 r700->PA_SC_LINE_CNTL.u32All = 0;
1771 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1772 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1773
1774 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1775 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1776 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1777 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1778 ctx->Polygon.OffsetUnits);
1779 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1780 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1781 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1782
1783 /* CB */
1784 r700BlendColor(ctx, ctx->Color.BlendColor);
1785
1786 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1787 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1788 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1789 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1790 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1791 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1792 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1793
1794 /* Disable color compares */
1795 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1796 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1797 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1798 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1799 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1800 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1801
1802 /* Zero out source */
1803 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1804
1805 /* Put a compare color in for error checking */
1806 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1807
1808 /* Set up color compare mask */
1809 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1810
1811 /* screen/window/view */
1812 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask);
1813
1814 context->radeon.hw.all_dirty = GL_TRUE;
1815
1816 }
1817
1818 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1819 {
1820 functions->UpdateState = r700InvalidateState;
1821 functions->AlphaFunc = r700AlphaFunc;
1822 functions->BlendColor = r700BlendColor;
1823 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1824 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1825 functions->Enable = r700Enable;
1826 functions->ColorMask = r700ColorMask;
1827 functions->DepthFunc = r700DepthFunc;
1828 functions->DepthMask = r700DepthMask;
1829 functions->CullFace = r700CullFace;
1830 functions->Fogfv = r700Fogfv;
1831 functions->FrontFace = r700FrontFace;
1832 functions->ShadeModel = r700ShadeModel;
1833 functions->LogicOpcode = r700LogicOpcode;
1834
1835 /* ARB_point_parameters */
1836 functions->PointParameterfv = r700PointParameter;
1837
1838 /* Stencil related */
1839 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1840 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1841 functions->StencilOpSeparate = r700StencilOpSeparate;
1842
1843 /* Viewport related */
1844 functions->Viewport = r700Viewport;
1845 functions->DepthRange = r700DepthRange;
1846 functions->PointSize = r700PointSize;
1847 functions->LineWidth = r700LineWidth;
1848 functions->LineStipple = r700LineStipple;
1849
1850 functions->PolygonOffset = r700PolygonOffset;
1851 functions->PolygonMode = r700PolygonMode;
1852
1853 functions->RenderMode = r700RenderMode;
1854
1855 functions->ClipPlane = r700ClipPlane;
1856
1857 functions->Scissor = radeonScissor;
1858
1859 functions->DrawBuffer = radeonDrawBuffer;
1860 functions->ReadBuffer = radeonReadBuffer;
1861
1862 }
1863