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Merge branch 'mesa_7_7_branch'
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_common_context.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
6
7 The Weather Channel (TM) funded Tungsten Graphics to develop the
8 initial release of the Radeon 8500 driver under the XFree86 license.
9 This notice must be preserved.
10
11 All Rights Reserved.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
24
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32
33 **************************************************************************/
34
35 #include "radeon_common.h"
36 #include "xmlpool.h" /* for symbolic values of enum-type options */
37 #include "utils.h"
38 #include "vblank.h"
39 #include "drirenderbuffer.h"
40 #include "drivers/common/meta.h"
41 #include "main/context.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44 #include "main/state.h"
45 #include "main/simple_list.h"
46 #include "swrast/swrast.h"
47 #include "swrast_setup/swrast_setup.h"
48 #include "tnl/tnl.h"
49
50 #if defined(RADEON_R600)
51 #include "r600_context.h"
52 #endif
53
54 #define DRIVER_DATE "20090101"
55
56 #ifndef RADEON_DEBUG
57 int RADEON_DEBUG = (0);
58 #endif
59
60
61 static const char* get_chip_family_name(int chip_family)
62 {
63 switch(chip_family) {
64 case CHIP_FAMILY_R100: return "R100";
65 case CHIP_FAMILY_RV100: return "RV100";
66 case CHIP_FAMILY_RS100: return "RS100";
67 case CHIP_FAMILY_RV200: return "RV200";
68 case CHIP_FAMILY_RS200: return "RS200";
69 case CHIP_FAMILY_R200: return "R200";
70 case CHIP_FAMILY_RV250: return "RV250";
71 case CHIP_FAMILY_RS300: return "RS300";
72 case CHIP_FAMILY_RV280: return "RV280";
73 case CHIP_FAMILY_R300: return "R300";
74 case CHIP_FAMILY_R350: return "R350";
75 case CHIP_FAMILY_RV350: return "RV350";
76 case CHIP_FAMILY_RV380: return "RV380";
77 case CHIP_FAMILY_R420: return "R420";
78 case CHIP_FAMILY_RV410: return "RV410";
79 case CHIP_FAMILY_RS400: return "RS400";
80 case CHIP_FAMILY_RS600: return "RS600";
81 case CHIP_FAMILY_RS690: return "RS690";
82 case CHIP_FAMILY_RS740: return "RS740";
83 case CHIP_FAMILY_RV515: return "RV515";
84 case CHIP_FAMILY_R520: return "R520";
85 case CHIP_FAMILY_RV530: return "RV530";
86 case CHIP_FAMILY_R580: return "R580";
87 case CHIP_FAMILY_RV560: return "RV560";
88 case CHIP_FAMILY_RV570: return "RV570";
89 case CHIP_FAMILY_R600: return "R600";
90 case CHIP_FAMILY_RV610: return "RV610";
91 case CHIP_FAMILY_RV630: return "RV630";
92 case CHIP_FAMILY_RV670: return "RV670";
93 case CHIP_FAMILY_RV620: return "RV620";
94 case CHIP_FAMILY_RV635: return "RV635";
95 case CHIP_FAMILY_RS780: return "RS780";
96 case CHIP_FAMILY_RS880: return "RS880";
97 case CHIP_FAMILY_RV770: return "RV770";
98 case CHIP_FAMILY_RV730: return "RV730";
99 case CHIP_FAMILY_RV710: return "RV710";
100 case CHIP_FAMILY_RV740: return "RV740";
101 default: return "unknown";
102 }
103 }
104
105
106 /* Return various strings for glGetString().
107 */
108 static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
109 {
110 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
111 static char buffer[128];
112
113 switch (name) {
114 case GL_VENDOR:
115 if (IS_R600_CLASS(radeon->radeonScreen))
116 return (GLubyte *) "Advanced Micro Devices, Inc.";
117 else if (IS_R300_CLASS(radeon->radeonScreen))
118 return (GLubyte *) "DRI R300 Project";
119 else
120 return (GLubyte *) "Tungsten Graphics, Inc.";
121
122 case GL_RENDERER:
123 {
124 unsigned offset;
125 GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
126 radeon->radeonScreen->AGPMode;
127 const char* chipclass;
128 char hardwarename[32];
129
130 if (IS_R600_CLASS(radeon->radeonScreen))
131 chipclass = "R600";
132 else if (IS_R300_CLASS(radeon->radeonScreen))
133 chipclass = "R300";
134 else if (IS_R200_CLASS(radeon->radeonScreen))
135 chipclass = "R200";
136 else
137 chipclass = "R100";
138
139 sprintf(hardwarename, "%s (%s %04X)",
140 chipclass,
141 get_chip_family_name(radeon->radeonScreen->chip_family),
142 radeon->radeonScreen->device_id);
143
144 offset = driGetRendererString(buffer, hardwarename, DRIVER_DATE,
145 agp_mode);
146
147 if (IS_R600_CLASS(radeon->radeonScreen)) {
148 sprintf(&buffer[offset], " TCL");
149 } else if (IS_R300_CLASS(radeon->radeonScreen)) {
150 sprintf(&buffer[offset], " %sTCL",
151 (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)
152 ? "" : "NO-");
153 } else {
154 sprintf(&buffer[offset], " %sTCL",
155 !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
156 ? "" : "NO-");
157 }
158
159 if (radeon->radeonScreen->driScreen->dri2.enabled)
160 strcat(buffer, " DRI2");
161
162 return (GLubyte *) buffer;
163 }
164
165 default:
166 return NULL;
167 }
168 }
169
170 /* Initialize the driver's misc functions.
171 */
172 static void radeonInitDriverFuncs(struct dd_function_table *functions)
173 {
174 functions->GetString = radeonGetString;
175 }
176
177 /**
178 * Create and initialize all common fields of the context,
179 * including the Mesa context itself.
180 */
181 GLboolean radeonInitContext(radeonContextPtr radeon,
182 struct dd_function_table* functions,
183 const __GLcontextModes * glVisual,
184 __DRIcontext * driContextPriv,
185 void *sharedContextPrivate)
186 {
187 __DRIscreen *sPriv = driContextPriv->driScreenPriv;
188 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
189 GLcontext* ctx;
190 GLcontext* shareCtx;
191 int fthrottle_mode;
192
193 /* Fill in additional standard functions. */
194 radeonInitDriverFuncs(functions);
195
196 radeon->radeonScreen = screen;
197 /* Allocate and initialize the Mesa context */
198 if (sharedContextPrivate)
199 shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx;
200 else
201 shareCtx = NULL;
202 radeon->glCtx = _mesa_create_context(glVisual, shareCtx,
203 functions, (void *)radeon);
204 if (!radeon->glCtx)
205 return GL_FALSE;
206
207 ctx = radeon->glCtx;
208 driContextPriv->driverPrivate = radeon;
209
210 meta_init_metaops(ctx, &radeon->meta);
211
212 _mesa_meta_init(ctx);
213
214 /* DRI fields */
215 radeon->dri.context = driContextPriv;
216 radeon->dri.screen = sPriv;
217 radeon->dri.hwContext = driContextPriv->hHWContext;
218 radeon->dri.hwLock = &sPriv->pSAREA->lock;
219 radeon->dri.hwLockCount = 0;
220 radeon->dri.fd = sPriv->fd;
221 radeon->dri.drmMinor = sPriv->drm_version.minor;
222
223 radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
224 screen->sarea_priv_offset);
225
226 /* Setup IRQs */
227 fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode");
228 radeon->iw.irq_seq = -1;
229 radeon->irqsEmitted = 0;
230 radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
231 radeon->radeonScreen->irq);
232
233 radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
234
235 if (!radeon->do_irqs)
236 fprintf(stderr,
237 "IRQ's not enabled, falling back to %s: %d %d\n",
238 radeon->do_usleeps ? "usleeps" : "busy waits",
239 fthrottle_mode, radeon->radeonScreen->irq);
240
241 radeon->texture_depth = driQueryOptioni (&radeon->optionCache,
242 "texture_depth");
243 if (radeon->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
244 radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
245 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
246
247 if (IS_R600_CLASS(radeon->radeonScreen)) {
248 radeon->texture_row_align = 256;
249 radeon->texture_rect_row_align = 256;
250 radeon->texture_compressed_row_align = 256;
251 } else if (IS_R200_CLASS(radeon->radeonScreen) ||
252 IS_R100_CLASS(radeon->radeonScreen)) {
253 radeon->texture_row_align = 32;
254 radeon->texture_rect_row_align = 64;
255 radeon->texture_compressed_row_align = 32;
256 } else { /* R300 - not sure this is all correct */
257 int chip_family = radeon->radeonScreen->chip_family;
258 if (chip_family == CHIP_FAMILY_RS600 ||
259 chip_family == CHIP_FAMILY_RS690 ||
260 chip_family == CHIP_FAMILY_RS740)
261 radeon->texture_row_align = 64;
262 else
263 radeon->texture_row_align = 32;
264 radeon->texture_rect_row_align = 64;
265 radeon->texture_compressed_row_align = 32;
266 }
267
268 radeon_init_dma(radeon);
269
270 return GL_TRUE;
271 }
272
273
274
275 /**
276 * Destroy the command buffer and state atoms.
277 */
278 static void radeon_destroy_atom_list(radeonContextPtr radeon)
279 {
280 struct radeon_state_atom *atom;
281
282 foreach(atom, &radeon->hw.atomlist) {
283 FREE(atom->cmd);
284 if (atom->lastcmd)
285 FREE(atom->lastcmd);
286 }
287
288 }
289
290 /**
291 * Cleanup common context fields.
292 * Called by r200DestroyContext/r300DestroyContext
293 */
294 void radeonDestroyContext(__DRIcontext *driContextPriv )
295 {
296 #ifdef RADEON_BO_TRACK
297 FILE *track;
298 #endif
299 GET_CURRENT_CONTEXT(ctx);
300 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
301 radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
302
303 assert(radeon);
304
305 _mesa_meta_free(radeon->glCtx);
306
307 if (radeon == current) {
308 radeon_firevertices(radeon);
309 _mesa_make_current(NULL, NULL, NULL);
310 }
311
312 if (!is_empty_list(&radeon->dma.reserved)) {
313 rcommonFlushCmdBuf( radeon, __FUNCTION__ );
314 }
315
316 radeonFreeDmaRegions(radeon);
317 radeonReleaseArrays(radeon->glCtx, ~0);
318 meta_destroy_metaops(&radeon->meta);
319 if (radeon->vtbl.free_context)
320 radeon->vtbl.free_context(radeon->glCtx);
321 _swsetup_DestroyContext( radeon->glCtx );
322 _tnl_DestroyContext( radeon->glCtx );
323 _vbo_DestroyContext( radeon->glCtx );
324 _swrast_DestroyContext( radeon->glCtx );
325
326 /* free atom list */
327 /* free the Mesa context */
328 _mesa_destroy_context(radeon->glCtx);
329
330 /* _mesa_destroy_context() might result in calls to functions that
331 * depend on the DriverCtx, so don't set it to NULL before.
332 *
333 * radeon->glCtx->DriverCtx = NULL;
334 */
335 /* free the option cache */
336 driDestroyOptionCache(&radeon->optionCache);
337
338 rcommonDestroyCmdBuf(radeon);
339
340 radeon_destroy_atom_list(radeon);
341
342 if (radeon->state.scissor.pClipRects) {
343 FREE(radeon->state.scissor.pClipRects);
344 radeon->state.scissor.pClipRects = 0;
345 }
346 #ifdef RADEON_BO_TRACK
347 track = fopen("/tmp/tracklog", "w");
348 if (track) {
349 radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track);
350 fclose(track);
351 }
352 #endif
353 FREE(radeon);
354 }
355
356 /* Force the context `c' to be unbound from its buffer.
357 */
358 GLboolean radeonUnbindContext(__DRIcontext * driContextPriv)
359 {
360 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
361
362 if (RADEON_DEBUG & RADEON_DRI)
363 fprintf(stderr, "%s ctx %p\n", __FUNCTION__,
364 radeon->glCtx);
365
366 return GL_TRUE;
367 }
368
369
370 static void
371 radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
372 struct radeon_framebuffer *draw)
373 {
374 /* if radeon->fake */
375 struct radeon_renderbuffer *rb;
376
377 if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
378 if (!rb->bo) {
379 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
380 radeon->radeonScreen->frontOffset,
381 0,
382 0,
383 RADEON_GEM_DOMAIN_VRAM,
384 0);
385 }
386 rb->cpp = radeon->radeonScreen->cpp;
387 rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
388 }
389 if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
390 if (!rb->bo) {
391 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
392 radeon->radeonScreen->backOffset,
393 0,
394 0,
395 RADEON_GEM_DOMAIN_VRAM,
396 0);
397 }
398 rb->cpp = radeon->radeonScreen->cpp;
399 rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
400 }
401 if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
402 if (!rb->bo) {
403 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
404 radeon->radeonScreen->depthOffset,
405 0,
406 0,
407 RADEON_GEM_DOMAIN_VRAM,
408 0);
409 }
410 rb->cpp = radeon->radeonScreen->cpp;
411 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
412 }
413 if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
414 if (!rb->bo) {
415 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
416 radeon->radeonScreen->depthOffset,
417 0,
418 0,
419 RADEON_GEM_DOMAIN_VRAM,
420 0);
421 }
422 rb->cpp = radeon->radeonScreen->cpp;
423 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
424 }
425 }
426
427 static void
428 radeon_make_renderbuffer_current(radeonContextPtr radeon,
429 struct radeon_framebuffer *draw)
430 {
431 int size = 4096*4096*4;
432 /* if radeon->fake */
433 struct radeon_renderbuffer *rb;
434
435 if (radeon->radeonScreen->kernel_mm) {
436 radeon_make_kernel_renderbuffer_current(radeon, draw);
437 return;
438 }
439
440
441 if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
442 if (!rb->bo) {
443 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
444 radeon->radeonScreen->frontOffset +
445 radeon->radeonScreen->fbLocation,
446 size,
447 4096,
448 RADEON_GEM_DOMAIN_VRAM,
449 0);
450 }
451 rb->cpp = radeon->radeonScreen->cpp;
452 rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
453 }
454 if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
455 if (!rb->bo) {
456 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
457 radeon->radeonScreen->backOffset +
458 radeon->radeonScreen->fbLocation,
459 size,
460 4096,
461 RADEON_GEM_DOMAIN_VRAM,
462 0);
463 }
464 rb->cpp = radeon->radeonScreen->cpp;
465 rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
466 }
467 if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
468 if (!rb->bo) {
469 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
470 radeon->radeonScreen->depthOffset +
471 radeon->radeonScreen->fbLocation,
472 size,
473 4096,
474 RADEON_GEM_DOMAIN_VRAM,
475 0);
476 }
477 rb->cpp = radeon->radeonScreen->cpp;
478 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
479 }
480 if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
481 if (!rb->bo) {
482 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
483 radeon->radeonScreen->depthOffset +
484 radeon->radeonScreen->fbLocation,
485 size,
486 4096,
487 RADEON_GEM_DOMAIN_VRAM,
488 0);
489 }
490 rb->cpp = radeon->radeonScreen->cpp;
491 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
492 }
493 }
494
495 static unsigned
496 radeon_bits_per_pixel(const struct radeon_renderbuffer *rb)
497 {
498 return _mesa_get_format_bytes(rb->base.Format) * 8;
499 }
500
501 void
502 radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
503 GLboolean front_only)
504 {
505 unsigned int attachments[10];
506 __DRIbuffer *buffers = NULL;
507 __DRIscreen *screen;
508 struct radeon_renderbuffer *rb;
509 int i, count;
510 struct radeon_framebuffer *draw;
511 radeonContextPtr radeon;
512 char *regname;
513 struct radeon_bo *depth_bo = NULL, *bo;
514
515 if (RADEON_DEBUG & RADEON_DRI)
516 fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
517
518 draw = drawable->driverPrivate;
519 screen = context->driScreenPriv;
520 radeon = (radeonContextPtr) context->driverPrivate;
521
522 if (screen->dri2.loader
523 && (screen->dri2.loader->base.version > 2)
524 && (screen->dri2.loader->getBuffersWithFormat != NULL)) {
525 struct radeon_renderbuffer *depth_rb;
526 struct radeon_renderbuffer *stencil_rb;
527
528 i = 0;
529 if ((front_only || radeon->is_front_buffer_rendering ||
530 radeon->is_front_buffer_reading ||
531 !draw->color_rb[1])
532 && draw->color_rb[0]) {
533 attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
534 attachments[i++] = radeon_bits_per_pixel(draw->color_rb[0]);
535 }
536
537 if (!front_only) {
538 if (draw->color_rb[1]) {
539 attachments[i++] = __DRI_BUFFER_BACK_LEFT;
540 attachments[i++] = radeon_bits_per_pixel(draw->color_rb[1]);
541 }
542
543 depth_rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
544 stencil_rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
545
546 if ((depth_rb != NULL) && (stencil_rb != NULL)) {
547 attachments[i++] = __DRI_BUFFER_DEPTH_STENCIL;
548 attachments[i++] = radeon_bits_per_pixel(depth_rb);
549 } else if (depth_rb != NULL) {
550 attachments[i++] = __DRI_BUFFER_DEPTH;
551 attachments[i++] = radeon_bits_per_pixel(depth_rb);
552 } else if (stencil_rb != NULL) {
553 attachments[i++] = __DRI_BUFFER_STENCIL;
554 attachments[i++] = radeon_bits_per_pixel(stencil_rb);
555 }
556 }
557
558 buffers = (*screen->dri2.loader->getBuffersWithFormat)(drawable,
559 &drawable->w,
560 &drawable->h,
561 attachments, i / 2,
562 &count,
563 drawable->loaderPrivate);
564 } else if (screen->dri2.loader) {
565 i = 0;
566 if (draw->color_rb[0])
567 attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
568 if (!front_only) {
569 if (draw->color_rb[1])
570 attachments[i++] = __DRI_BUFFER_BACK_LEFT;
571 if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH))
572 attachments[i++] = __DRI_BUFFER_DEPTH;
573 if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL))
574 attachments[i++] = __DRI_BUFFER_STENCIL;
575 }
576
577 buffers = (*screen->dri2.loader->getBuffers)(drawable,
578 &drawable->w,
579 &drawable->h,
580 attachments, i,
581 &count,
582 drawable->loaderPrivate);
583 }
584
585 if (buffers == NULL)
586 return;
587
588 /* set one cliprect to cover the whole drawable */
589 drawable->x = 0;
590 drawable->y = 0;
591 drawable->backX = 0;
592 drawable->backY = 0;
593 drawable->numClipRects = 1;
594 drawable->pClipRects[0].x1 = 0;
595 drawable->pClipRects[0].y1 = 0;
596 drawable->pClipRects[0].x2 = drawable->w;
597 drawable->pClipRects[0].y2 = drawable->h;
598 drawable->numBackClipRects = 1;
599 drawable->pBackClipRects[0].x1 = 0;
600 drawable->pBackClipRects[0].y1 = 0;
601 drawable->pBackClipRects[0].x2 = drawable->w;
602 drawable->pBackClipRects[0].y2 = drawable->h;
603 for (i = 0; i < count; i++) {
604 switch (buffers[i].attachment) {
605 case __DRI_BUFFER_FRONT_LEFT:
606 rb = draw->color_rb[0];
607 regname = "dri2 front buffer";
608 break;
609 case __DRI_BUFFER_FAKE_FRONT_LEFT:
610 rb = draw->color_rb[0];
611 regname = "dri2 fake front buffer";
612 break;
613 case __DRI_BUFFER_BACK_LEFT:
614 rb = draw->color_rb[1];
615 regname = "dri2 back buffer";
616 break;
617 case __DRI_BUFFER_DEPTH:
618 rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
619 regname = "dri2 depth buffer";
620 break;
621 case __DRI_BUFFER_DEPTH_STENCIL:
622 rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
623 regname = "dri2 depth / stencil buffer";
624 break;
625 case __DRI_BUFFER_STENCIL:
626 rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
627 regname = "dri2 stencil buffer";
628 break;
629 case __DRI_BUFFER_ACCUM:
630 default:
631 fprintf(stderr,
632 "unhandled buffer attach event, attacment type %d\n",
633 buffers[i].attachment);
634 return;
635 }
636
637 if (rb == NULL)
638 continue;
639
640 if (rb->bo) {
641 uint32_t name = radeon_gem_name_bo(rb->bo);
642 if (name == buffers[i].name)
643 continue;
644 }
645
646 if (RADEON_DEBUG & RADEON_DRI)
647 fprintf(stderr,
648 "attaching buffer %s, %d, at %d, cpp %d, pitch %d\n",
649 regname, buffers[i].name, buffers[i].attachment,
650 buffers[i].cpp, buffers[i].pitch);
651
652 rb->cpp = buffers[i].cpp;
653 rb->pitch = buffers[i].pitch;
654 rb->base.Width = drawable->w;
655 rb->base.Height = drawable->h;
656 rb->has_surface = 0;
657
658 if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
659 if (RADEON_DEBUG & RADEON_DRI)
660 fprintf(stderr, "(reusing depth buffer as stencil)\n");
661 bo = depth_bo;
662 radeon_bo_ref(bo);
663 } else {
664 uint32_t tiling_flags = 0, pitch = 0;
665 int ret;
666
667 bo = radeon_bo_open(radeon->radeonScreen->bom,
668 buffers[i].name,
669 0,
670 0,
671 RADEON_GEM_DOMAIN_VRAM,
672 buffers[i].flags);
673
674 if (bo == NULL) {
675
676 fprintf(stderr, "failed to attach %s %d\n",
677 regname, buffers[i].name);
678
679 }
680
681 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
682 if (tiling_flags & RADEON_TILING_MACRO)
683 bo->flags |= RADEON_BO_FLAGS_MACRO_TILE;
684 if (tiling_flags & RADEON_TILING_MICRO)
685 bo->flags |= RADEON_BO_FLAGS_MICRO_TILE;
686
687 }
688
689 if (buffers[i].attachment == __DRI_BUFFER_DEPTH) {
690 if (draw->base.Visual.depthBits == 16)
691 rb->cpp = 2;
692 depth_bo = bo;
693 }
694
695 radeon_renderbuffer_set_bo(rb, bo);
696 radeon_bo_unref(bo);
697
698 if (buffers[i].attachment == __DRI_BUFFER_DEPTH_STENCIL) {
699 rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
700 if (rb != NULL) {
701 struct radeon_bo *stencil_bo = NULL;
702
703 if (rb->bo) {
704 uint32_t name = radeon_gem_name_bo(rb->bo);
705 if (name == buffers[i].name)
706 continue;
707 }
708
709 stencil_bo = bo;
710 radeon_bo_ref(stencil_bo);
711 radeon_renderbuffer_set_bo(rb, stencil_bo);
712 radeon_bo_unref(stencil_bo);
713 }
714 }
715 }
716
717 driUpdateFramebufferSize(radeon->glCtx, drawable);
718 }
719
720 /* Force the context `c' to be the current context and associate with it
721 * buffer `b'.
722 */
723 GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
724 __DRIdrawable * driDrawPriv,
725 __DRIdrawable * driReadPriv)
726 {
727 radeonContextPtr radeon;
728 struct radeon_framebuffer *drfb;
729 struct gl_framebuffer *readfb;
730
731 if (!driContextPriv) {
732 if (RADEON_DEBUG & RADEON_DRI)
733 fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
734 _mesa_make_current(NULL, NULL, NULL);
735 return GL_TRUE;
736 }
737
738 radeon = (radeonContextPtr) driContextPriv->driverPrivate;
739 drfb = driDrawPriv->driverPrivate;
740 readfb = driReadPriv->driverPrivate;
741
742 if (driContextPriv->driScreenPriv->dri2.enabled) {
743 radeon_update_renderbuffers(driContextPriv, driDrawPriv, GL_FALSE);
744 if (driDrawPriv != driReadPriv)
745 radeon_update_renderbuffers(driContextPriv, driReadPriv, GL_FALSE);
746 _mesa_reference_renderbuffer(&radeon->state.color.rb,
747 &(radeon_get_renderbuffer(&drfb->base, BUFFER_BACK_LEFT)->base));
748 _mesa_reference_renderbuffer(&radeon->state.depth.rb,
749 &(radeon_get_renderbuffer(&drfb->base, BUFFER_DEPTH)->base));
750 } else {
751 radeon_make_renderbuffer_current(radeon, drfb);
752 }
753
754 if (RADEON_DEBUG & RADEON_DRI)
755 fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb);
756
757 driUpdateFramebufferSize(radeon->glCtx, driDrawPriv);
758 if (driReadPriv != driDrawPriv)
759 driUpdateFramebufferSize(radeon->glCtx, driReadPriv);
760
761 _mesa_make_current(radeon->glCtx, &drfb->base, readfb);
762
763 _mesa_update_state(radeon->glCtx);
764
765 if (radeon->glCtx->DrawBuffer == &drfb->base) {
766 if (driDrawPriv->swap_interval == (unsigned)-1) {
767 int i;
768 driDrawPriv->vblFlags =
769 (radeon->radeonScreen->irq != 0)
770 ? driGetDefaultVBlankFlags(&radeon->
771 optionCache)
772 : VBLANK_FLAG_NO_IRQ;
773
774 driDrawableInitVBlank(driDrawPriv);
775 drfb->vbl_waited = driDrawPriv->vblSeq;
776
777 for (i = 0; i < 2; i++) {
778 if (drfb->color_rb[i])
779 drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq;
780 }
781
782 }
783
784 radeon_window_moved(radeon);
785 radeon_draw_buffer(radeon->glCtx, &drfb->base);
786 }
787
788
789 if (RADEON_DEBUG & RADEON_DRI)
790 fprintf(stderr, "End %s\n", __FUNCTION__);
791
792 return GL_TRUE;
793 }
794