src/mesa/drivers/dri/radeon/radeon_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  *   Keith Whitwell <keith@tungstengraphics.com>
  35  */
  36
  37 #include "main/glheader.h"
  38 #include "main/api_arrayelt.h"
  39 #include "main/context.h"
  40 #include "main/simple_list.h"
  41 #include "main/imports.h"
  42 #include "main/extensions.h"
  43
  44 #include "swrast/swrast.h"
  45 #include "swrast_setup/swrast_setup.h"
  46 #include "vbo/vbo.h"
  47
  48 #include "tnl/tnl.h"
  49 #include "tnl/t_pipeline.h"
  50
  51 #include "drivers/common/driverfuncs.h"
  52
  53 #include "radeon_common.h"
  54 #include "radeon_context.h"
  55 #include "radeon_ioctl.h"
  56 #include "radeon_state.h"
  57 #include "radeon_span.h"
  58 #include "radeon_tex.h"
  59 #include "radeon_swtcl.h"
  60 #include "radeon_tcl.h"
  61 #include "radeon_queryobj.h"
  62 #include "radeon_blit.h"
  63
  64 #define need_GL_ARB_occlusion_query
  65 #define need_GL_EXT_blend_minmax
  66 #define need_GL_EXT_fog_coord
  67 #define need_GL_EXT_secondary_color
  68 #define need_GL_EXT_framebuffer_object
  69 #include "main/remap_helper.h"
  70
  71 #define DRIVER_DATE     "20061018"
  72
  73 #include "utils.h"
  74 #include "xmlpool.h" /* for symbolic values of enum-type options */
  75
  76 /* Extension strings exported by the R100 driver.
  77  */
  78 static const struct dri_extension card_extensions[] =
  79 {
  80     { "GL_ARB_multitexture",               NULL },
  81     { "GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
  82     { "GL_ARB_texture_border_clamp",       NULL },
  83     { "GL_ARB_texture_env_add",            NULL },
  84     { "GL_ARB_texture_env_combine",        NULL },
  85     { "GL_ARB_texture_env_crossbar",       NULL },
  86     { "GL_ARB_texture_env_dot3",           NULL },
  87     { "GL_ARB_texture_mirrored_repeat",    NULL },
  88     { "GL_EXT_blend_logic_op",             NULL },
  89     { "GL_EXT_blend_subtract",             GL_EXT_blend_minmax_functions },
  90     { "GL_EXT_fog_coord",                  GL_EXT_fog_coord_functions },
  91     { "GL_EXT_packed_depth_stencil",       NULL},
  92     { "GL_EXT_secondary_color",            GL_EXT_secondary_color_functions },
  93     { "GL_EXT_stencil_wrap",               NULL },
  94     { "GL_EXT_texture_edge_clamp",         NULL },
  95     { "GL_EXT_texture_env_combine",        NULL },
  96     { "GL_EXT_texture_env_dot3",           NULL },
  97     { "GL_EXT_texture_filter_anisotropic", NULL },
  98     { "GL_EXT_texture_lod_bias",           NULL },
  99     { "GL_EXT_texture_mirror_clamp",       NULL },
 100     { "GL_ATI_texture_env_combine3",       NULL },
 101     { "GL_ATI_texture_mirror_once",        NULL },
 102     { "GL_MESA_ycbcr_texture",             NULL },
 103     { "GL_NV_blend_square",                NULL },
 104     { "GL_SGIS_generate_mipmap",           NULL },
 105     { NULL,                                NULL }
 106 };
 107
 108 static const struct dri_extension mm_extensions[] = {
 109   { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
 110   { NULL, NULL }
 111 };
 112
 113 extern const struct tnl_pipeline_stage _radeon_render_stage;
 114 extern const struct tnl_pipeline_stage _radeon_tcl_stage;
 115
 116 static const struct tnl_pipeline_stage *radeon_pipeline[] = {
 117
 118    /* Try and go straight to t&l
 119     */
 120    &_radeon_tcl_stage,
 121
 122    /* Catch any t&l fallbacks
 123     */
 124    &_tnl_vertex_transform_stage,
 125    &_tnl_normal_transform_stage,
 126    &_tnl_lighting_stage,
 127    &_tnl_fog_coordinate_stage,
 128    &_tnl_texgen_stage,
 129    &_tnl_texture_transform_stage,
 130
 131    &_radeon_render_stage,
 132    &_tnl_render_stage,          /* FALLBACK:  */
 133    NULL,
 134 };
 135
 136 static void r100_get_lock(radeonContextPtr radeon)
 137 {
 138    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 139    drm_radeon_sarea_t *sarea = radeon->sarea;
 140
 141    RADEON_STATECHANGE(rmesa, ctx);
 142    if (rmesa->radeon.sarea->tiling_enabled) {
 143       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
 144          RADEON_COLOR_TILE_ENABLE;
 145    } else {
 146       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
 147          ~RADEON_COLOR_TILE_ENABLE;
 148    }
 149
 150    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
 151       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
 152
 153       if (!radeon->radeonScreen->kernel_mm)
 154          radeon_bo_legacy_texture_age(radeon->radeonScreen->bom);
 155    }
 156 }
 157
 158 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 159 {
 160 }
 161
 162 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
 163 {
 164    r100ContextPtr rmesa = (r100ContextPtr)radeon;
 165
 166    /* r100 always needs to emit ZBS to avoid TCL lockups */
 167    rmesa->hw.zbs.dirty = 1;
 168    radeon->hw.is_dirty = 1;
 169 }
 170
 171 static void r100_vtbl_free_context(GLcontext *ctx)
 172 {
 173    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 174    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
 175 }
 176
 177 static void r100_emit_query_finish(radeonContextPtr radeon)
 178 {
 179    BATCH_LOCALS(radeon);
 180    struct radeon_query_object *query = radeon->query.current;
 181
 182    BEGIN_BATCH_NO_AUTOSTATE(4);
 183    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
 184    OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 185    END_BATCH();
 186    query->curr_offset += sizeof(uint32_t);
 187    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 188    query->emitted_begin = GL_FALSE;
 189 }
 190
 191 static void r100_init_vtbl(radeonContextPtr radeon)
 192 {
 193    radeon->vtbl.get_lock = r100_get_lock;
 194    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
 195    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
 196    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
 197    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
 198    radeon->vtbl.fallback = radeonFallback;
 199    radeon->vtbl.free_context = r100_vtbl_free_context;
 200    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
 201    radeon->vtbl.check_blit = r100_check_blit;
 202    radeon->vtbl.blit = r100_blit;
 203    radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
 204 }
 205
 206 /* Create the device specific context.
 207  */
 208 GLboolean
 209 r100CreateContext( const __GLcontextModes *glVisual,
 210                      __DRIcontext *driContextPriv,
 211                      void *sharedContextPrivate)
 212 {
 213    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 214    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
 215    struct dd_function_table functions;
 216    r100ContextPtr rmesa;
 217    GLcontext *ctx;
 218    int i;
 219    int tcl_mode, fthrottle_mode;
 220
 221    assert(glVisual);
 222    assert(driContextPriv);
 223    assert(screen);
 224
 225    /* Allocate the Radeon context */
 226    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
 227    if ( !rmesa )
 228       return GL_FALSE;
 229
 230    rmesa->radeon.radeonScreen = screen;
 231    r100_init_vtbl(&rmesa->radeon);
 232
 233    /* init exp fog table data */
 234    radeonInitStaticFogData();
 235
 236    /* Parse configuration files.
 237     * Do this here so that initialMaxAnisotropy is set before we create
 238     * the default textures.
 239     */
 240    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
 241                         screen->driScreen->myNum, "radeon");
 242    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
 243                                                  "def_max_anisotropy");
 244
 245    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
 246       if ( sPriv->drm_version.minor < 13 )
 247          fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
 248                           "disabling.\n", sPriv->drm_version.minor );
 249       else
 250          rmesa->using_hyperz = GL_TRUE;
 251    }
 252
 253    if ( sPriv->drm_version.minor >= 15 )
 254       rmesa->texmicrotile = GL_TRUE;
 255
 256    /* Init default driver functions then plug in our Radeon-specific functions
 257     * (the texture functions are especially important)
 258     */
 259    _mesa_init_driver_functions( &functions );
 260    radeonInitTextureFuncs( &rmesa->radeon, &functions );
 261    radeonInitQueryObjFunctions(&functions);
 262
 263    if (!radeonInitContext(&rmesa->radeon, &functions,
 264                           glVisual, driContextPriv,
 265                           sharedContextPrivate)) {
 266      FREE(rmesa);
 267      return GL_FALSE;
 268    }
 269
 270    rmesa->radeon.swtcl.RenderIndex = ~0;
 271    rmesa->radeon.hw.all_dirty = GL_TRUE;
 272
 273    /* Set the maximum texture size small enough that we can guarentee that
 274     * all texture units can bind a maximal texture and have all of them in
 275     * texturable memory at once. Depending on the allow_large_textures driconf
 276     * setting allow larger textures.
 277     */
 278
 279    ctx = rmesa->radeon.glCtx;
 280    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
 281                                                  "texture_units");
 282    ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
 283    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
 284    ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
 285
 286    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
 287
 288    /* FIXME: When no memory manager is available we should set this
 289     * to some reasonable value based on texture memory pool size */
 290    ctx->Const.MaxTextureLevels = 12;
 291    ctx->Const.Max3DTextureLevels = 9;
 292    ctx->Const.MaxCubeTextureLevels = 12;
 293    ctx->Const.MaxTextureRectSize = 2048;
 294
 295    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 296
 297    /* No wide points.
 298     */
 299    ctx->Const.MinPointSize = 1.0;
 300    ctx->Const.MinPointSizeAA = 1.0;
 301    ctx->Const.MaxPointSize = 1.0;
 302    ctx->Const.MaxPointSizeAA = 1.0;
 303
 304    ctx->Const.MinLineWidth = 1.0;
 305    ctx->Const.MinLineWidthAA = 1.0;
 306    ctx->Const.MaxLineWidth = 10.0;
 307    ctx->Const.MaxLineWidthAA = 10.0;
 308    ctx->Const.LineWidthGranularity = 0.0625;
 309
 310    /* Set maxlocksize (and hence vb size) small enough to avoid
 311     * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
 312     * fit in a single dma buffer for indexed rendering of quad strips,
 313     * etc.
 314     */
 315    ctx->Const.MaxArrayLockSize =
 316       MIN2( ctx->Const.MaxArrayLockSize,
 317             RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
 318
 319    rmesa->boxes = 0;
 320
 321    ctx->Const.MaxDrawBuffers = 1;
 322    ctx->Const.MaxColorAttachments = 1;
 323    ctx->Const.MaxRenderbufferSize = 2048;
 324
 325    _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 326
 327    /* Initialize the software rasterizer and helper modules.
 328     */
 329    _swrast_CreateContext( ctx );
 330    _vbo_CreateContext( ctx );
 331    _tnl_CreateContext( ctx );
 332    _swsetup_CreateContext( ctx );
 333    _ae_create_context( ctx );
 334
 335    /* Install the customized pipeline:
 336     */
 337    _tnl_destroy_pipeline( ctx );
 338    _tnl_install_pipeline( ctx, radeon_pipeline );
 339
 340    /* Try and keep materials and vertices separate:
 341     */
 342 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
 343
 344    /* Configure swrast and T&L to match hardware characteristics:
 345     */
 346    _swrast_allow_pixel_fog( ctx, GL_FALSE );
 347    _swrast_allow_vertex_fog( ctx, GL_TRUE );
 348    _tnl_allow_pixel_fog( ctx, GL_FALSE );
 349    _tnl_allow_vertex_fog( ctx, GL_TRUE );
 350
 351
 352    for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
 353       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
 354       _math_matrix_ctr( &rmesa->tmpmat[i] );
 355       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
 356       _math_matrix_set_identity( &rmesa->tmpmat[i] );
 357    }
 358
 359    driInitExtensions( ctx, card_extensions, GL_TRUE );
 360    if (rmesa->radeon.radeonScreen->kernel_mm)
 361      driInitExtensions(ctx, mm_extensions, GL_FALSE);
 362    if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
 363       _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
 364    if (rmesa->radeon.glCtx->Mesa_DXTn) {
 365       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 366       _mesa_enable_extension( ctx, "GL_S3_s3tc" );
 367    }
 368    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
 369       _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
 370    }
 371
 372    if (rmesa->radeon.radeonScreen->kernel_mm || rmesa->radeon.dri.drmMinor >= 9)
 373       _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
 374
 375    if (!rmesa->radeon.radeonScreen->kernel_mm)
 376       _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
 377
 378    /* XXX these should really go right after _mesa_init_driver_functions() */
 379    radeon_fbo_init(&rmesa->radeon);
 380    radeonInitSpanFuncs( ctx );
 381    radeonInitIoctlFuncs( ctx );
 382    radeonInitStateFuncs( ctx , rmesa->radeon.radeonScreen->kernel_mm );
 383    radeonInitState( rmesa );
 384    radeonInitSwtcl( ctx );
 385
 386    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
 387                          ctx->Const.MaxArrayLockSize, 32 );
 388
 389    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
 390    rmesa->radeon.iw.irq_seq = -1;
 391    rmesa->radeon.irqsEmitted = 0;
 392    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
 393                             fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
 394
 395    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 396
 397
 398 #if DO_DEBUG
 399    RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
 400                                        debug_control );
 401 #endif
 402
 403    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
 404    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
 405       fprintf(stderr, "disabling 3D acceleration\n");
 406       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
 407    } else if (tcl_mode == DRI_CONF_TCL_SW ||
 408               !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
 409       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 410          rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
 411          fprintf(stderr, "Disabling HW TCL support\n");
 412       }
 413       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
 414    }
 415
 416    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
 417 /*       _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
 418    }
 419    return GL_TRUE;
 420 }