1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 * Keith Whitwell <keith@tungstengraphics.com>
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "main/imports.h"
43 #include "main/extensions.h"
44 #include "main/mfeatures.h"
45 #include "main/version.h"
47 #include "swrast/swrast.h"
48 #include "swrast_setup/swrast_setup.h"
52 #include "tnl/t_pipeline.h"
54 #include "drivers/common/driverfuncs.h"
56 #include "radeon_common.h"
57 #include "radeon_context.h"
58 #include "radeon_ioctl.h"
59 #include "radeon_state.h"
60 #include "radeon_span.h"
61 #include "radeon_tex.h"
62 #include "radeon_swtcl.h"
63 #include "radeon_tcl.h"
64 #include "radeon_queryobj.h"
65 #include "radeon_blit.h"
66 #include "radeon_fog.h"
69 #include "xmlpool.h" /* for symbolic values of enum-type options */
71 extern const struct tnl_pipeline_stage _radeon_render_stage
;
72 extern const struct tnl_pipeline_stage _radeon_tcl_stage
;
74 static const struct tnl_pipeline_stage
*radeon_pipeline
[] = {
76 /* Try and go straight to t&l
80 /* Catch any t&l fallbacks
82 &_tnl_vertex_transform_stage
,
83 &_tnl_normal_transform_stage
,
85 &_tnl_fog_coordinate_stage
,
87 &_tnl_texture_transform_stage
,
89 &_radeon_render_stage
,
90 &_tnl_render_stage
, /* FALLBACK: */
94 static void r100_get_lock(radeonContextPtr radeon
)
96 r100ContextPtr rmesa
= (r100ContextPtr
)radeon
;
97 drm_radeon_sarea_t
*sarea
= radeon
->sarea
;
99 RADEON_STATECHANGE(rmesa
, ctx
);
100 if (rmesa
->radeon
.sarea
->tiling_enabled
) {
101 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |=
102 RADEON_COLOR_TILE_ENABLE
;
104 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] &=
105 ~RADEON_COLOR_TILE_ENABLE
;
108 if (sarea
->ctx_owner
!= rmesa
->radeon
.dri
.hwContext
) {
109 sarea
->ctx_owner
= rmesa
->radeon
.dri
.hwContext
;
113 static void r100_vtbl_emit_cs_header(struct radeon_cs
*cs
, radeonContextPtr rmesa
)
117 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon
)
119 r100ContextPtr rmesa
= (r100ContextPtr
)radeon
;
121 /* r100 always needs to emit ZBS to avoid TCL lockups */
122 rmesa
->hw
.zbs
.dirty
= 1;
123 radeon
->hw
.is_dirty
= 1;
126 static void r100_vtbl_free_context(struct gl_context
*ctx
)
128 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
129 _mesa_vector4f_free( &rmesa
->tcl
.ObjClean
);
132 static void r100_emit_query_finish(radeonContextPtr radeon
)
134 BATCH_LOCALS(radeon
);
135 struct radeon_query_object
*query
= radeon
->query
.current
;
137 BEGIN_BATCH_NO_AUTOSTATE(4);
138 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR
, 0));
139 OUT_BATCH_RELOC(0, query
->bo
, query
->curr_offset
, 0, RADEON_GEM_DOMAIN_GTT
, 0);
141 query
->curr_offset
+= sizeof(uint32_t);
142 assert(query
->curr_offset
< RADEON_QUERY_PAGE_SIZE
);
143 query
->emitted_begin
= GL_FALSE
;
146 static void r100_init_vtbl(radeonContextPtr radeon
)
148 radeon
->vtbl
.get_lock
= r100_get_lock
;
149 radeon
->vtbl
.update_viewport_offset
= radeonUpdateViewportOffset
;
150 radeon
->vtbl
.emit_cs_header
= r100_vtbl_emit_cs_header
;
151 radeon
->vtbl
.swtcl_flush
= r100_swtcl_flush
;
152 radeon
->vtbl
.pre_emit_state
= r100_vtbl_pre_emit_state
;
153 radeon
->vtbl
.fallback
= radeonFallback
;
154 radeon
->vtbl
.free_context
= r100_vtbl_free_context
;
155 radeon
->vtbl
.emit_query_finish
= r100_emit_query_finish
;
156 radeon
->vtbl
.check_blit
= r100_check_blit
;
157 radeon
->vtbl
.blit
= r100_blit
;
158 radeon
->vtbl
.is_format_renderable
= radeonIsFormatRenderable
;
161 /* Create the device specific context.
164 r100CreateContext( gl_api api
,
165 const struct gl_config
*glVisual
,
166 __DRIcontext
*driContextPriv
,
167 unsigned major_version
,
168 unsigned minor_version
,
171 void *sharedContextPrivate
)
173 __DRIscreen
*sPriv
= driContextPriv
->driScreenPriv
;
174 radeonScreenPtr screen
= (radeonScreenPtr
)(sPriv
->driverPrivate
);
175 struct dd_function_table functions
;
176 r100ContextPtr rmesa
;
177 struct gl_context
*ctx
;
179 int tcl_mode
, fthrottle_mode
;
183 if (major_version
> 1 || minor_version
> 3) {
184 *error
= __DRI_CTX_ERROR_BAD_VERSION
;
191 *error
= __DRI_CTX_ERROR_BAD_API
;
195 /* Flag filtering is handled in dri2CreateContextAttribs.
200 assert(driContextPriv
);
203 /* Allocate the Radeon context */
204 rmesa
= calloc(1, sizeof(*rmesa
));
206 *error
= __DRI_CTX_ERROR_NO_MEMORY
;
210 rmesa
->radeon
.radeonScreen
= screen
;
211 r100_init_vtbl(&rmesa
->radeon
);
213 /* init exp fog table data */
214 radeonInitStaticFogData();
216 /* Parse configuration files.
217 * Do this here so that initialMaxAnisotropy is set before we create
218 * the default textures.
220 driParseConfigFiles (&rmesa
->radeon
.optionCache
, &screen
->optionCache
,
221 screen
->driScreen
->myNum
, "radeon");
222 rmesa
->radeon
.initialMaxAnisotropy
= driQueryOptionf(&rmesa
->radeon
.optionCache
,
223 "def_max_anisotropy");
225 if ( driQueryOptionb( &rmesa
->radeon
.optionCache
, "hyperz" ) ) {
226 if ( sPriv
->drm_version
.minor
< 13 )
227 fprintf( stderr
, "DRM version 1.%d too old to support HyperZ, "
228 "disabling.\n", sPriv
->drm_version
.minor
);
230 rmesa
->using_hyperz
= GL_TRUE
;
233 if ( sPriv
->drm_version
.minor
>= 15 )
234 rmesa
->texmicrotile
= GL_TRUE
;
236 /* Init default driver functions then plug in our Radeon-specific functions
237 * (the texture functions are especially important)
239 _mesa_init_driver_functions( &functions
);
240 radeonInitTextureFuncs( &rmesa
->radeon
, &functions
);
241 radeonInitQueryObjFunctions(&functions
);
243 if (!radeonInitContext(&rmesa
->radeon
, &functions
,
244 glVisual
, driContextPriv
,
245 sharedContextPrivate
)) {
247 *error
= __DRI_CTX_ERROR_NO_MEMORY
;
251 rmesa
->radeon
.swtcl
.RenderIndex
= ~0;
252 rmesa
->radeon
.hw
.all_dirty
= GL_TRUE
;
254 /* Set the maximum texture size small enough that we can guarentee that
255 * all texture units can bind a maximal texture and have all of them in
256 * texturable memory at once. Depending on the allow_large_textures driconf
257 * setting allow larger textures.
260 ctx
= rmesa
->radeon
.glCtx
;
261 ctx
->Const
.MaxTextureUnits
= driQueryOptioni (&rmesa
->radeon
.optionCache
,
263 ctx
->Const
.MaxTextureImageUnits
= ctx
->Const
.MaxTextureUnits
;
264 ctx
->Const
.MaxTextureCoordUnits
= ctx
->Const
.MaxTextureUnits
;
265 ctx
->Const
.MaxCombinedTextureImageUnits
= ctx
->Const
.MaxTextureUnits
;
267 ctx
->Const
.StripTextureBorder
= GL_TRUE
;
269 i
= driQueryOptioni( &rmesa
->radeon
.optionCache
, "allow_large_textures");
271 /* FIXME: When no memory manager is available we should set this
272 * to some reasonable value based on texture memory pool size */
273 ctx
->Const
.MaxTextureLevels
= 12;
274 ctx
->Const
.Max3DTextureLevels
= 9;
275 ctx
->Const
.MaxCubeTextureLevels
= 12;
276 ctx
->Const
.MaxTextureRectSize
= 2048;
278 ctx
->Const
.MaxTextureMaxAnisotropy
= 16.0;
282 ctx
->Const
.MinPointSize
= 1.0;
283 ctx
->Const
.MinPointSizeAA
= 1.0;
284 ctx
->Const
.MaxPointSize
= 1.0;
285 ctx
->Const
.MaxPointSizeAA
= 1.0;
287 ctx
->Const
.MinLineWidth
= 1.0;
288 ctx
->Const
.MinLineWidthAA
= 1.0;
289 ctx
->Const
.MaxLineWidth
= 10.0;
290 ctx
->Const
.MaxLineWidthAA
= 10.0;
291 ctx
->Const
.LineWidthGranularity
= 0.0625;
293 /* Set maxlocksize (and hence vb size) small enough to avoid
294 * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
295 * fit in a single dma buffer for indexed rendering of quad strips,
298 ctx
->Const
.MaxArrayLockSize
=
299 MIN2( ctx
->Const
.MaxArrayLockSize
,
300 RADEON_BUFFER_SIZE
/ RADEON_MAX_TCL_VERTSIZE
);
304 ctx
->Const
.MaxDrawBuffers
= 1;
305 ctx
->Const
.MaxColorAttachments
= 1;
306 ctx
->Const
.MaxRenderbufferSize
= 2048;
308 _mesa_set_mvp_with_dp4( ctx
, GL_TRUE
);
310 /* Initialize the software rasterizer and helper modules.
312 _swrast_CreateContext( ctx
);
313 _vbo_CreateContext( ctx
);
314 _tnl_CreateContext( ctx
);
315 _swsetup_CreateContext( ctx
);
316 _ae_create_context( ctx
);
318 /* Install the customized pipeline:
320 _tnl_destroy_pipeline( ctx
);
321 _tnl_install_pipeline( ctx
, radeon_pipeline
);
323 /* Try and keep materials and vertices separate:
325 /* _tnl_isolate_materials( ctx, GL_TRUE ); */
327 /* Configure swrast and T&L to match hardware characteristics:
329 _swrast_allow_pixel_fog( ctx
, GL_FALSE
);
330 _swrast_allow_vertex_fog( ctx
, GL_TRUE
);
331 _tnl_allow_pixel_fog( ctx
, GL_FALSE
);
332 _tnl_allow_vertex_fog( ctx
, GL_TRUE
);
335 for ( i
= 0 ; i
< RADEON_MAX_TEXTURE_UNITS
; i
++ ) {
336 _math_matrix_ctr( &rmesa
->TexGenMatrix
[i
] );
337 _math_matrix_ctr( &rmesa
->tmpmat
[i
] );
338 _math_matrix_set_identity( &rmesa
->TexGenMatrix
[i
] );
339 _math_matrix_set_identity( &rmesa
->tmpmat
[i
] );
342 ctx
->Extensions
.ARB_texture_border_clamp
= true;
343 ctx
->Extensions
.ARB_texture_env_combine
= true;
344 ctx
->Extensions
.ARB_texture_env_crossbar
= true;
345 ctx
->Extensions
.ARB_texture_env_dot3
= true;
346 ctx
->Extensions
.EXT_fog_coord
= true;
347 ctx
->Extensions
.EXT_packed_depth_stencil
= true;
348 ctx
->Extensions
.EXT_secondary_color
= true;
349 ctx
->Extensions
.EXT_texture_env_dot3
= true;
350 ctx
->Extensions
.EXT_texture_filter_anisotropic
= true;
351 ctx
->Extensions
.EXT_texture_mirror_clamp
= true;
352 ctx
->Extensions
.ATI_texture_env_combine3
= true;
353 ctx
->Extensions
.ATI_texture_mirror_once
= true;
354 ctx
->Extensions
.MESA_ycbcr_texture
= true;
355 ctx
->Extensions
.NV_blend_square
= true;
356 #if FEATURE_OES_EGL_image
357 ctx
->Extensions
.OES_EGL_image
= true;
360 ctx
->Extensions
.EXT_framebuffer_object
= true;
362 ctx
->Extensions
.ARB_texture_cube_map
= true;
364 if (rmesa
->radeon
.glCtx
->Mesa_DXTn
) {
365 ctx
->Extensions
.EXT_texture_compression_s3tc
= true;
366 ctx
->Extensions
.S3_s3tc
= true;
368 else if (driQueryOptionb (&rmesa
->radeon
.optionCache
, "force_s3tc_enable")) {
369 ctx
->Extensions
.EXT_texture_compression_s3tc
= true;
372 ctx
->Extensions
.NV_texture_rectangle
= true;
373 ctx
->Extensions
.ARB_occlusion_query
= true;
375 /* XXX these should really go right after _mesa_init_driver_functions() */
376 radeon_fbo_init(&rmesa
->radeon
);
377 radeonInitSpanFuncs( ctx
);
378 radeonInitIoctlFuncs( ctx
);
379 radeonInitStateFuncs( ctx
);
380 radeonInitState( rmesa
);
381 radeonInitSwtcl( ctx
);
383 _mesa_vector4f_alloc( &rmesa
->tcl
.ObjClean
, 0,
384 ctx
->Const
.MaxArrayLockSize
, 32 );
386 fthrottle_mode
= driQueryOptioni(&rmesa
->radeon
.optionCache
, "fthrottle_mode");
387 rmesa
->radeon
.iw
.irq_seq
= -1;
388 rmesa
->radeon
.irqsEmitted
= 0;
389 rmesa
->radeon
.do_irqs
= (rmesa
->radeon
.radeonScreen
->irq
!= 0 &&
390 fthrottle_mode
== DRI_CONF_FTHROTTLE_IRQS
);
392 rmesa
->radeon
.do_usleeps
= (fthrottle_mode
== DRI_CONF_FTHROTTLE_USLEEPS
);
396 RADEON_DEBUG
= driParseDebugString( getenv( "RADEON_DEBUG" ),
400 tcl_mode
= driQueryOptioni(&rmesa
->radeon
.optionCache
, "tcl_mode");
401 if (driQueryOptionb(&rmesa
->radeon
.optionCache
, "no_rast")) {
402 fprintf(stderr
, "disabling 3D acceleration\n");
403 FALLBACK(rmesa
, RADEON_FALLBACK_DISABLE
, 1);
404 } else if (tcl_mode
== DRI_CONF_TCL_SW
||
405 !(rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
)) {
406 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
407 rmesa
->radeon
.radeonScreen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
408 fprintf(stderr
, "Disabling HW TCL support\n");
410 TCL_FALLBACK(rmesa
->radeon
.glCtx
, RADEON_TCL_FALLBACK_TCL_DISABLE
, 1);
413 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
414 /* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
417 _mesa_compute_version(ctx
);
419 *error
= __DRI_CTX_ERROR_SUCCESS
;