src/mesa/drivers/dri/radeon/radeon_ioctl.h

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Kevin E. Martin <martin@valinux.com>
  33  *   Gareth Hughes <gareth@valinux.com>
  34  */
  35
  36 #ifndef __RADEON_IOCTL_H__
  37 #define __RADEON_IOCTL_H__
  38
  39 #include "util/simple_list.h"
  40 #include "radeon_bo_gem.h"
  41 #include "radeon_cs_gem.h"
  42
  43 extern void radeonEmitVertexAOS( r100ContextPtr rmesa,
  44                                  GLuint vertex_size,
  45                                  struct radeon_bo *bo,
  46                                  GLuint offset );
  47
  48 extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
  49                                 GLuint vertex_format,
  50                                 GLuint primitive,
  51                                 GLuint vertex_nr );
  52
  53 extern void radeonFlushElts( struct gl_context *ctx );
  54
  55
  56 extern GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
  57                                            GLuint vertex_format,
  58                                            GLuint primitive,
  59                                            GLuint min_nr );
  60
  61
  62 extern void radeonEmitAOS( r100ContextPtr rmesa,
  63                            GLuint n,
  64                            GLuint offset );
  65
  66 extern void radeonEmitBlit( r100ContextPtr rmesa,
  67                             GLuint color_fmt,
  68                             GLuint src_pitch,
  69                             GLuint src_offset,
  70                             GLuint dst_pitch,
  71                             GLuint dst_offset,
  72                             GLint srcx, GLint srcy,
  73                             GLint dstx, GLint dsty,
  74                             GLuint w, GLuint h );
  75
  76 extern void radeonEmitWait( r100ContextPtr rmesa, GLuint flags );
  77
  78 extern void radeonFlushCmdBuf( r100ContextPtr rmesa, const char * );
  79
  80 extern void radeonFlush( struct gl_context *ctx );
  81 extern void radeonFinish( struct gl_context *ctx );
  82 extern void radeonInitIoctlFuncs( struct gl_context *ctx );
  83 extern void radeonGetAllParams( r100ContextPtr rmesa );
  84 extern void radeonSetUpAtomList( r100ContextPtr rmesa );
  85
  86 /* ================================================================
  87  * Helper macros:
  88  */
  89
  90 /* Close off the last primitive, if it exists.
  91  */
  92 #define RADEON_NEWPRIM( rmesa )                 \
  93 do {                                            \
  94    if ( rmesa->radeon.dma.flush )                       \
  95       rmesa->radeon.dma.flush( &rmesa->radeon.glCtx );  \
  96 } while (0)
  97
  98 /* Can accomodate several state changes and primitive changes without
  99  * actually firing the buffer.
 100  */
 101
 102 #define RADEON_STATECHANGE( rmesa, ATOM )                       \
 103 do {                                                            \
 104    RADEON_NEWPRIM( rmesa );                                     \
 105    rmesa->hw.ATOM.dirty = GL_TRUE;                              \
 106    rmesa->radeon.hw.is_dirty = GL_TRUE;                         \
 107 } while (0)
 108
 109 #define RADEON_DB_STATE( ATOM )                         \
 110    memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd,  \
 111            rmesa->hw.ATOM.cmd_size * 4)
 112
 113 static inline int RADEON_DB_STATECHANGE(r100ContextPtr rmesa,
 114                                         struct radeon_state_atom *atom )
 115 {
 116    if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) {
 117       GLuint *tmp;
 118       RADEON_NEWPRIM( rmesa );
 119       atom->dirty = GL_TRUE;
 120       rmesa->radeon.hw.is_dirty = GL_TRUE;
 121       tmp = atom->cmd;
 122       atom->cmd = atom->lastcmd;
 123       atom->lastcmd = tmp;
 124       return 1;
 125    }
 126    else
 127       return 0;
 128 }
 129
 130 /* Command lengths.  Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ
 131  * are available, you will also be adding an rmesa->state.max_state_size because
 132  * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts.
 133  */
 134 #if RADEON_OLD_PACKETS
 135 #define AOS_BUFSZ(nr)   ((3 + ((nr / 2) * 3) + ((nr & 1) * 2))+nr*2)
 136 #define VERT_AOS_BUFSZ  (0)
 137 #define ELTS_BUFSZ(nr)  (24 + nr * 2)
 138 #define VBUF_BUFSZ      (8)
 139 #else
 140 #define AOS_BUFSZ(nr)   ((3 + ((nr / 2) * 3) + ((nr & 1) * 2) + nr*2))
 141 #define VERT_AOS_BUFSZ  (5)
 142 #define ELTS_BUFSZ(nr)  (16 + nr * 2)
 143 #define VBUF_BUFSZ      (4)
 144 #endif
 145 #define SCISSOR_BUFSZ   (8)
 146 #define INDEX_BUFSZ     (7)
 147
 148
 149 static inline uint32_t cmdpacket3(int cmd_type)
 150 {
 151   drm_radeon_cmd_header_t cmd;
 152
 153   cmd.i = 0;
 154   cmd.header.cmd_type = cmd_type;
 155
 156   return (uint32_t)cmd.i;
 157
 158 }
 159
 160 #define OUT_BATCH_PACKET3(packet, num_extra) do {             \
 161     OUT_BATCH(CP_PACKET2);                                    \
 162     OUT_BATCH(CP_PACKET3((packet), (num_extra)));             \
 163   } while(0)
 164
 165 #define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do {        \
 166     OUT_BATCH(CP_PACKET2);                                    \
 167     OUT_BATCH(CP_PACKET3((packet), (num_extra)));             \
 168   } while(0)
 169
 170
 171 #endif /* __RADEON_IOCTL_H__ */