src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c

   1 /*
   2  * Copyright (C) 2009 Maciej Cencora.
   3  * Copyright (C) 2008 Nicolai Haehnle.
   4  *
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sublicense, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial
  17  * portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  20  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  22  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  23  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  24  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  25  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "radeon_mipmap_tree.h"
  30
  31 #include <errno.h>
  32 #include <unistd.h>
  33
  34 #include "main/simple_list.h"
  35 #include "main/teximage.h"
  36 #include "main/texobj.h"
  37 #include "radeon_texture.h"
  38
  39 static unsigned get_aligned_compressed_row_stride(
  40                 gl_format format,
  41                 unsigned width,
  42                 unsigned minStride)
  43 {
  44         const unsigned blockSize = _mesa_get_format_bytes(format);
  45         unsigned blockWidth, blockHeight, numXBlocks;
  46
  47         _mesa_get_format_block_size(format, &blockWidth, &blockHeight);
  48         numXBlocks = (width + blockWidth - 1) / blockWidth;
  49
  50         while (numXBlocks * blockSize < minStride)
  51         {
  52                 ++numXBlocks;
  53         }
  54
  55         return numXBlocks * blockSize;
  56 }
  57
  58 static unsigned get_compressed_image_size(
  59                 gl_format format,
  60                 unsigned rowStride,
  61                 unsigned height)
  62 {
  63         unsigned blockWidth, blockHeight;
  64
  65         _mesa_get_format_block_size(format, &blockWidth, &blockHeight);
  66
  67         return rowStride * ((height + blockHeight - 1) / blockHeight);
  68 }
  69
  70 static int find_next_power_of_two(GLuint value)
  71 {
  72         int i, tmp;
  73
  74         i = 0;
  75         tmp = value - 1;
  76         while (tmp) {
  77                 tmp >>= 1;
  78                 i++;
  79         }
  80         return (1 << i);
  81 }
  82
  83 /**
  84  * Compute sizes and fill in offset and blit information for the given
  85  * image (determined by \p face and \p level).
  86  *
  87  * \param curOffset points to the offset at which the image is to be stored
  88  * and is updated by this function according to the size of the image.
  89  */
  90 static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt,
  91         GLuint face, GLuint level, GLuint* curOffset)
  92 {
  93         radeon_mipmap_level *lvl = &mt->levels[level];
  94         uint32_t row_align;
  95         GLuint height;
  96
  97         height = find_next_power_of_two(lvl->height);
  98
  99         /* Find image size in bytes */
 100         if (_mesa_is_format_compressed(mt->mesaFormat)) {
 101                 lvl->rowstride = get_aligned_compressed_row_stride(mt->mesaFormat, lvl->width, rmesa->texture_compressed_row_align);
 102                 lvl->size = get_compressed_image_size(mt->mesaFormat, lvl->rowstride, height);
 103         } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
 104                 row_align = rmesa->texture_rect_row_align - 1;
 105                 lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align;
 106                 lvl->size = lvl->rowstride * height;
 107         } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
 108                 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
 109                  * though the actual offset may be different (if texture is less than
 110                  * 32 bytes width) to the untiled case */
 111                 lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) * 2 + 31) & ~31;
 112                 lvl->size = lvl->rowstride * ((height + 1) / 2) * lvl->depth;
 113         } else {
 114                 row_align = rmesa->texture_row_align - 1;
 115                 lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align;
 116                 lvl->size = lvl->rowstride * height * lvl->depth;
 117         }
 118         assert(lvl->size > 0);
 119
 120         /* All images are aligned to a 32-byte offset */
 121         *curOffset = (*curOffset + 0x1f) & ~0x1f;
 122         lvl->faces[face].offset = *curOffset;
 123         *curOffset += lvl->size;
 124
 125         if (RADEON_DEBUG & RADEON_TEXTURE)
 126           fprintf(stderr,
 127                   "level %d, face %d: rs:%d %dx%d at %d\n",
 128                   level, face, lvl->rowstride, lvl->width, height, lvl->faces[face].offset);
 129 }
 130
 131 static GLuint minify(GLuint size, GLuint levels)
 132 {
 133         size = size >> levels;
 134         if (size < 1)
 135                 size = 1;
 136         return size;
 137 }
 138
 139
 140 static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 141 {
 142         GLuint curOffset, i, face, level;
 143
 144         assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
 145
 146         curOffset = 0;
 147         for(face = 0; face < mt->faces; face++) {
 148
 149                 for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
 150                         mt->levels[level].valid = 1;
 151                         mt->levels[level].width = minify(mt->width0, i);
 152                         mt->levels[level].height = minify(mt->height0, i);
 153                         mt->levels[level].depth = minify(mt->depth0, i);
 154                         compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
 155                 }
 156         }
 157
 158         /* Note the required size in memory */
 159         mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
 160 }
 161
 162 static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 163 {
 164         GLuint curOffset, i, level;
 165
 166         assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
 167
 168         curOffset = 0;
 169         for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
 170                 GLuint face;
 171
 172                 mt->levels[level].valid = 1;
 173                 mt->levels[level].width = minify(mt->width0, i);
 174                 mt->levels[level].height = minify(mt->height0, i);
 175                 mt->levels[level].depth = minify(mt->depth0, i);
 176
 177                 for(face = 0; face < mt->faces; face++)
 178                         compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
 179                 /* r600 cube levels seems to be aligned to 8 faces but
 180                  * we have separate register for 1'st level offset so add
 181                  * 2 image alignment after 1'st mip level */
 182                 if(rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R600 &&
 183                    mt->target == GL_TEXTURE_CUBE_MAP && level >= 1)
 184                         curOffset += 2 * mt->levels[level].size;
 185         }
 186
 187         /* Note the required size in memory */
 188         mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
 189 }
 190
 191 /**
 192  * Create a new mipmap tree, calculate its layout and allocate memory.
 193  */
 194 static radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa,
 195                 GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels,
 196                 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
 197 {
 198         radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree);
 199
 200         mt->mesaFormat = mesaFormat;
 201         mt->refcount = 1;
 202         mt->target = target;
 203         mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1;
 204         mt->baseLevel = baseLevel;
 205         mt->numLevels = numLevels;
 206         mt->width0 = width0;
 207         mt->height0 = height0;
 208         mt->depth0 = depth0;
 209         mt->tilebits = tilebits;
 210
 211         if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300)
 212                 calculate_miptree_layout_r300(rmesa, mt);
 213         else
 214                 calculate_miptree_layout_r100(rmesa, mt);
 215
 216         mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
 217                             0, mt->totalsize, 1024,
 218                             RADEON_GEM_DOMAIN_VRAM,
 219                             0);
 220
 221         return mt;
 222 }
 223
 224 void radeon_miptree_reference(radeon_mipmap_tree *mt, radeon_mipmap_tree **ptr)
 225 {
 226         assert(!*ptr);
 227
 228         mt->refcount++;
 229         assert(mt->refcount > 0);
 230
 231         *ptr = mt;
 232 }
 233
 234 void radeon_miptree_unreference(radeon_mipmap_tree **ptr)
 235 {
 236         radeon_mipmap_tree *mt = *ptr;
 237         if (!mt)
 238                 return;
 239
 240         assert(mt->refcount > 0);
 241
 242         mt->refcount--;
 243         if (!mt->refcount) {
 244                 radeon_bo_unref(mt->bo);
 245                 free(mt);
 246         }
 247
 248         *ptr = 0;
 249 }
 250
 251 /**
 252  * Calculate min and max LOD for the given texture object.
 253  * @param[in] tObj texture object whose LOD values to calculate
 254  * @param[out] pminLod minimal LOD
 255  * @param[out] pmaxLod maximal LOD
 256  */
 257 static void calculate_min_max_lod(struct gl_texture_object *tObj,
 258                                        unsigned *pminLod, unsigned *pmaxLod)
 259 {
 260         int minLod, maxLod;
 261         /* Yes, this looks overly complicated, but it's all needed.
 262         */
 263         switch (tObj->Target) {
 264         case GL_TEXTURE_1D:
 265         case GL_TEXTURE_2D:
 266         case GL_TEXTURE_3D:
 267         case GL_TEXTURE_CUBE_MAP:
 268                 if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) {
 269                         /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
 270                         */
 271                         minLod = maxLod = tObj->BaseLevel;
 272                 } else {
 273                         minLod = tObj->BaseLevel + (GLint)(tObj->MinLod);
 274                         minLod = MAX2(minLod, tObj->BaseLevel);
 275                         minLod = MIN2(minLod, tObj->MaxLevel);
 276                         maxLod = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5);
 277                         maxLod = MIN2(maxLod, tObj->MaxLevel);
 278                         maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxLog2 + minLod);
 279                         maxLod = MAX2(maxLod, minLod); /* need at least one level */
 280                 }
 281                 break;
 282         case GL_TEXTURE_RECTANGLE_NV:
 283         case GL_TEXTURE_4D_SGIS:
 284                 minLod = maxLod = 0;
 285                 break;
 286         default:
 287                 return;
 288         }
 289
 290         /* save these values */
 291         *pminLod = minLod;
 292         *pmaxLod = maxLod;
 293 }
 294
 295 /**
 296  * Checks whether the given miptree can hold the given texture image at the
 297  * given face and level.
 298  */
 299 GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
 300                 struct gl_texture_image *texImage, GLuint face, GLuint level)
 301 {
 302         radeon_mipmap_level *lvl;
 303
 304         if (face >= mt->faces)
 305                 return GL_FALSE;
 306
 307         if (texImage->TexFormat != mt->mesaFormat)
 308                 return GL_FALSE;
 309
 310         lvl = &mt->levels[level];
 311         if (!lvl->valid ||
 312             lvl->width != texImage->Width ||
 313             lvl->height != texImage->Height ||
 314             lvl->depth != texImage->Depth)
 315                 return GL_FALSE;
 316
 317         return GL_TRUE;
 318 }
 319
 320 /**
 321  * Checks whether the given miptree has the right format to store the given texture object.
 322  */
 323 static GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj)
 324 {
 325         struct gl_texture_image *firstImage;
 326         unsigned numLevels;
 327         radeon_mipmap_level *mtBaseLevel;
 328
 329         if (texObj->BaseLevel < mt->baseLevel)
 330                 return GL_FALSE;
 331
 332         mtBaseLevel = &mt->levels[texObj->BaseLevel - mt->baseLevel];
 333         firstImage = texObj->Image[0][texObj->BaseLevel];
 334         numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, firstImage->MaxLog2 + 1);
 335
 336         if (RADEON_DEBUG & RADEON_TEXTURE) {
 337                 fprintf(stderr, "Checking if miptree %p matches texObj %p\n", mt, texObj);
 338                 fprintf(stderr, "target %d vs %d\n", mt->target, texObj->Target);
 339                 fprintf(stderr, "format %d vs %d\n", mt->mesaFormat, firstImage->TexFormat);
 340                 fprintf(stderr, "numLevels %d vs %d\n", mt->numLevels, numLevels);
 341                 fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width);
 342                 fprintf(stderr, "height0 %d vs %d\n", mtBaseLevel->height, firstImage->Height);
 343                 fprintf(stderr, "depth0 %d vs %d\n", mtBaseLevel->depth, firstImage->Depth);
 344                 if (mt->target == texObj->Target &&
 345                 mt->mesaFormat == firstImage->TexFormat &&
 346                 mt->numLevels >= numLevels &&
 347                 mtBaseLevel->width == firstImage->Width &&
 348                 mtBaseLevel->height == firstImage->Height &&
 349                 mtBaseLevel->depth == firstImage->Depth) {
 350                         fprintf(stderr, "MATCHED\n");
 351                 } else {
 352                         fprintf(stderr, "NOT MATCHED\n");
 353                 }
 354         }
 355
 356         return (mt->target == texObj->Target &&
 357                 mt->mesaFormat == firstImage->TexFormat &&
 358                 mt->numLevels >= numLevels &&
 359                 mtBaseLevel->width == firstImage->Width &&
 360                 mtBaseLevel->height == firstImage->Height &&
 361                 mtBaseLevel->depth == firstImage->Depth);
 362 }
 363
 364 /**
 365  * Try to allocate a mipmap tree for the given texture object.
 366  * @param[in] rmesa radeon context
 367  * @param[in] t radeon texture object
 368  */
 369 void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t)
 370 {
 371         struct gl_texture_object *texObj = &t->base;
 372         struct gl_texture_image *texImg = texObj->Image[0][texObj->BaseLevel];
 373         GLuint numLevels;
 374
 375         assert(!t->mt);
 376
 377         if (!texImg)
 378                 return;
 379
 380         numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, texImg->MaxLog2 + 1);
 381
 382         t->mt = radeon_miptree_create(rmesa, t->base.Target,
 383                 texImg->TexFormat, texObj->BaseLevel,
 384                 numLevels, texImg->Width, texImg->Height,
 385                 texImg->Depth, t->tile_bits);
 386 }
 387
 388 GLuint
 389 radeon_miptree_image_offset(radeon_mipmap_tree *mt,
 390                             GLuint face, GLuint level)
 391 {
 392         if (mt->target == GL_TEXTURE_CUBE_MAP_ARB)
 393                 return (mt->levels[level].faces[face].offset);
 394         else
 395                 return mt->levels[level].faces[0].offset;
 396 }
 397
 398 /**
 399  * Ensure that the given image is stored in the given miptree from now on.
 400  */
 401 static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
 402                                                                          radeon_texture_image *image,
 403                                                                          int face, int level)
 404 {
 405         radeon_mipmap_level *dstlvl = &mt->levels[level];
 406         unsigned char *dest;
 407
 408         assert(image->mt != mt);
 409         assert(dstlvl->valid);
 410         assert(dstlvl->width == image->base.Width);
 411         assert(dstlvl->height == image->base.Height);
 412         assert(dstlvl->depth == image->base.Depth);
 413
 414         radeon_bo_map(mt->bo, GL_TRUE);
 415         dest = mt->bo->ptr + dstlvl->faces[face].offset;
 416
 417         if (image->mt) {
 418                 /* Format etc. should match, so we really just need a memcpy().
 419                  * In fact, that memcpy() could be done by the hardware in many
 420                  * cases, provided that we have a proper memory manager.
 421                  */
 422                 assert(mt->mesaFormat == image->base.TexFormat);
 423
 424                 radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel];
 425
 426                 /* TODO: bring back these assertions once the FBOs are fixed */
 427 #if 0
 428                 assert(image->mtlevel == level);
 429                 assert(srclvl->size == dstlvl->size);
 430                 assert(srclvl->rowstride == dstlvl->rowstride);
 431 #endif
 432
 433                 radeon_bo_map(image->mt->bo, GL_FALSE);
 434
 435                 memcpy(dest,
 436                         image->mt->bo->ptr + srclvl->faces[face].offset,
 437                         dstlvl->size);
 438                 radeon_bo_unmap(image->mt->bo);
 439
 440                 radeon_miptree_unreference(&image->mt);
 441         } else if (image->base.Data) {
 442                 /* This condition should be removed, it's here to workaround
 443                  * a segfault when mapping textures during software fallbacks.
 444                  */
 445                 const uint32_t srcrowstride = _mesa_format_row_stride(image->base.TexFormat, image->base.Width);
 446                 uint32_t rows = image->base.Height * image->base.Depth;
 447
 448                 if (_mesa_is_format_compressed(image->base.TexFormat)) {
 449                         uint32_t blockWidth, blockHeight;
 450                         _mesa_get_format_block_size(image->base.TexFormat, &blockWidth, &blockHeight);
 451                         rows = (rows + blockHeight - 1) / blockHeight;
 452                 }
 453
 454                 copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride,
 455                                   rows, srcrowstride);
 456
 457                 _mesa_free_texmemory(image->base.Data);
 458                 image->base.Data = 0;
 459         }
 460
 461         radeon_bo_unmap(mt->bo);
 462
 463         radeon_miptree_reference(mt, &image->mt);
 464         image->mtface = face;
 465         image->mtlevel = level;
 466 }
 467
 468 /**
 469  * Filter matching miptrees, and select one with the most of data.
 470  * @param[in] texObj radeon texture object
 471  * @param[in] firstLevel first texture level to check
 472  * @param[in] lastLevel last texture level to check
 473  */
 474 static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj,
 475                                                                                                                  unsigned firstLevel,
 476                                                                                                                  unsigned lastLevel)
 477 {
 478         const unsigned numLevels = lastLevel - firstLevel + 1;
 479         unsigned *mtSizes = calloc(numLevels, sizeof(unsigned));
 480         radeon_mipmap_tree **mts = calloc(numLevels, sizeof(radeon_mipmap_tree *));
 481         unsigned mtCount = 0;
 482         unsigned maxMtIndex = 0;
 483         radeon_mipmap_tree *tmp;
 484
 485         for (unsigned level = firstLevel; level <= lastLevel; ++level) {
 486                 radeon_texture_image *img = get_radeon_texture_image(texObj->base.Image[0][level]);
 487                 unsigned found = 0;
 488                 // TODO: why this hack??
 489                 if (!img)
 490                         break;
 491
 492                 if (!img->mt)
 493                         continue;
 494
 495                 for (int i = 0; i < mtCount; ++i) {
 496                         if (mts[i] == img->mt) {
 497                                 found = 1;
 498                                 mtSizes[i] += img->mt->levels[img->mtlevel].size;
 499                                 break;
 500                         }
 501                 }
 502
 503                 if (!found && radeon_miptree_matches_texture(img->mt, &texObj->base)) {
 504                         mtSizes[mtCount] = img->mt->levels[img->mtlevel].size;
 505                         mts[mtCount] = img->mt;
 506                         mtCount++;
 507                 }
 508         }
 509
 510         if (mtCount == 0) {
 511                 return NULL;
 512         }
 513
 514         for (int i = 1; i < mtCount; ++i) {
 515                 if (mtSizes[i] > mtSizes[maxMtIndex]) {
 516                         maxMtIndex = i;
 517                 }
 518         }
 519
 520         tmp = mts[maxMtIndex];
 521         free(mtSizes);
 522         free(mts);
 523
 524         return tmp;
 525 }
 526
 527 /**
 528  * Validate texture mipmap tree.
 529  * If individual images are stored in different mipmap trees
 530  * use the mipmap tree that has the most of the correct data.
 531  */
 532 int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj)
 533 {
 534         radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 535         radeonTexObj *t = radeon_tex_obj(texObj);
 536
 537         if (t->validated || t->image_override) {
 538                 return GL_TRUE;
 539         }
 540
 541         if (texObj->Image[0][texObj->BaseLevel]->Border > 0)
 542                 return GL_FALSE;
 543
 544         _mesa_test_texobj_completeness(rmesa->glCtx, texObj);
 545         if (!texObj->_Complete) {
 546                 return GL_FALSE;
 547         }
 548
 549         calculate_min_max_lod(&t->base, &t->minLod, &t->maxLod);
 550
 551         if (RADEON_DEBUG & RADEON_TEXTURE)
 552                 fprintf(stderr, "%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
 553                                 __FUNCTION__, texObj ,t->minLod, t->maxLod);
 554
 555         radeon_mipmap_tree *dst_miptree;
 556         dst_miptree = get_biggest_matching_miptree(t, t->minLod, t->maxLod);
 557
 558         if (!dst_miptree) {
 559                 radeon_miptree_unreference(&t->mt);
 560                 radeon_try_alloc_miptree(rmesa, t);
 561                 dst_miptree = t->mt;
 562                 if (RADEON_DEBUG & RADEON_TEXTURE) {
 563                         fprintf(stderr, "%s: No matching miptree found, allocated new one %p\n", __FUNCTION__, t->mt);
 564                 }
 565         } else if (RADEON_DEBUG & RADEON_TEXTURE) {
 566                 fprintf(stderr, "%s: Using miptree %p\n", __FUNCTION__, t->mt);
 567         }
 568
 569         const unsigned faces = texObj->Target == GL_TEXTURE_CUBE_MAP ? 6 : 1;
 570         unsigned face, level;
 571         radeon_texture_image *img;
 572         /* Validate only the levels that will actually be used during rendering */
 573         for (face = 0; face < faces; ++face) {
 574                 for (level = t->minLod; level <= t->maxLod; ++level) {
 575                         img = get_radeon_texture_image(texObj->Image[face][level]);
 576
 577                         if (RADEON_DEBUG & RADEON_TEXTURE) {
 578                                 fprintf(stderr, "Checking image level %d, face %d, mt %p ... ", level, face, img->mt);
 579                         }
 580
 581                         if (img->mt != dst_miptree) {
 582                                 if (RADEON_DEBUG & RADEON_TEXTURE) {
 583                                         fprintf(stderr, "MIGRATING\n");
 584                                 }
 585                                 struct radeon_bo *src_bo = (img->mt) ? img->mt->bo : img->bo;
 586                                 if (src_bo && radeon_bo_is_referenced_by_cs(src_bo, rmesa->cmdbuf.cs)) {
 587                                         radeon_firevertices(rmesa);
 588                                 }
 589                                 migrate_image_to_miptree(dst_miptree, img, face, level);
 590                         } else if (RADEON_DEBUG & RADEON_TEXTURE) {
 591                                 fprintf(stderr, "OK\n");
 592                         }
 593                 }
 594         }
 595
 596         t->validated = GL_TRUE;
 597
 598         return GL_TRUE;
 599 }
 600
 601 uint32_t get_base_teximage_offset(radeonTexObj *texObj)
 602 {
 603         if (!texObj->mt) {
 604                 return 0;
 605         } else {
 606                 return radeon_miptree_image_offset(texObj->mt, 0, texObj->minLod);
 607         }
 608 }