2 * Copyright (C) 2009 Maciej Cencora.
3 * Copyright (C) 2008 Nicolai Haehnle.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sublicense, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon_mipmap_tree.h"
34 #include "main/simple_list.h"
35 #include "main/texcompress.h"
36 #include "main/teximage.h"
37 #include "main/texobj.h"
38 #include "radeon_texture.h"
40 static unsigned get_aligned_compressed_row_stride(
45 const unsigned blockSize
= _mesa_get_format_bytes(format
);
46 unsigned blockWidth
, blockHeight
, numXBlocks
;
48 _mesa_get_format_block_size(format
, &blockWidth
, &blockHeight
);
49 numXBlocks
= (width
+ blockWidth
- 1) / blockWidth
;
51 while (numXBlocks
* blockSize
< minStride
)
56 return numXBlocks
* blockSize
;
59 static unsigned get_compressed_image_size(
64 unsigned blockWidth
, blockHeight
;
66 _mesa_get_format_block_size(format
, &blockWidth
, &blockHeight
);
68 return rowStride
* ((height
+ blockHeight
- 1) / blockHeight
);
71 static int find_next_power_of_two(GLuint value
)
85 * Compute sizes and fill in offset and blit information for the given
86 * image (determined by \p face and \p level).
88 * \param curOffset points to the offset at which the image is to be stored
89 * and is updated by this function according to the size of the image.
91 static void compute_tex_image_offset(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
,
92 GLuint face
, GLuint level
, GLuint
* curOffset
)
94 radeon_mipmap_level
*lvl
= &mt
->levels
[level
];
98 height
= find_next_power_of_two(lvl
->height
);
100 /* Find image size in bytes */
101 if (_mesa_is_format_compressed(mt
->mesaFormat
)) {
102 lvl
->rowstride
= get_aligned_compressed_row_stride(mt
->mesaFormat
, lvl
->width
, rmesa
->texture_compressed_row_align
);
103 lvl
->size
= get_compressed_image_size(mt
->mesaFormat
, lvl
->rowstride
, height
);
104 } else if (mt
->target
== GL_TEXTURE_RECTANGLE_NV
) {
105 row_align
= rmesa
->texture_rect_row_align
- 1;
106 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
107 lvl
->size
= lvl
->rowstride
* height
;
108 } else if (mt
->tilebits
& RADEON_TXO_MICRO_TILE
) {
109 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
110 * though the actual offset may be different (if texture is less than
111 * 32 bytes width) to the untiled case */
112 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) * 2 + 31) & ~31;
113 lvl
->size
= lvl
->rowstride
* ((height
+ 1) / 2) * lvl
->depth
;
115 row_align
= rmesa
->texture_row_align
- 1;
116 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
117 lvl
->size
= lvl
->rowstride
* height
* lvl
->depth
;
119 assert(lvl
->size
> 0);
121 /* All images are aligned to a 32-byte offset */
122 *curOffset
= (*curOffset
+ 0x1f) & ~0x1f;
123 lvl
->faces
[face
].offset
= *curOffset
;
124 *curOffset
+= lvl
->size
;
126 if (RADEON_DEBUG
& RADEON_TEXTURE
)
128 "level %d, face %d: rs:%d %dx%d at %d\n",
129 level
, face
, lvl
->rowstride
, lvl
->width
, height
, lvl
->faces
[face
].offset
);
132 static GLuint
minify(GLuint size
, GLuint levels
)
134 size
= size
>> levels
;
141 static void calculate_miptree_layout_r100(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
)
143 GLuint curOffset
, i
, face
, level
;
145 assert(mt
->numLevels
<= rmesa
->glCtx
->Const
.MaxTextureLevels
);
148 for(face
= 0; face
< mt
->faces
; face
++) {
150 for(i
= 0, level
= mt
->baseLevel
; i
< mt
->numLevels
; i
++, level
++) {
151 mt
->levels
[level
].valid
= 1;
152 mt
->levels
[level
].width
= minify(mt
->width0
, i
);
153 mt
->levels
[level
].height
= minify(mt
->height0
, i
);
154 mt
->levels
[level
].depth
= minify(mt
->depth0
, i
);
155 compute_tex_image_offset(rmesa
, mt
, face
, level
, &curOffset
);
159 /* Note the required size in memory */
160 mt
->totalsize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
163 static void calculate_miptree_layout_r300(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
)
165 GLuint curOffset
, i
, level
;
167 assert(mt
->numLevels
<= rmesa
->glCtx
->Const
.MaxTextureLevels
);
170 for(i
= 0, level
= mt
->baseLevel
; i
< mt
->numLevels
; i
++, level
++) {
173 mt
->levels
[level
].valid
= 1;
174 mt
->levels
[level
].width
= minify(mt
->width0
, i
);
175 mt
->levels
[level
].height
= minify(mt
->height0
, i
);
176 mt
->levels
[level
].depth
= minify(mt
->depth0
, i
);
178 for(face
= 0; face
< mt
->faces
; face
++)
179 compute_tex_image_offset(rmesa
, mt
, face
, level
, &curOffset
);
180 /* r600 cube levels seems to be aligned to 8 faces but
181 * we have separate register for 1'st level offset so add
182 * 2 image alignment after 1'st mip level */
183 if(rmesa
->radeonScreen
->chip_family
>= CHIP_FAMILY_R600
&&
184 mt
->target
== GL_TEXTURE_CUBE_MAP
&& level
>= 1)
185 curOffset
+= 2 * mt
->levels
[level
].size
;
188 /* Note the required size in memory */
189 mt
->totalsize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
193 * Create a new mipmap tree, calculate its layout and allocate memory.
195 static radeon_mipmap_tree
* radeon_miptree_create(radeonContextPtr rmesa
,
196 GLenum target
, gl_format mesaFormat
, GLuint baseLevel
, GLuint numLevels
,
197 GLuint width0
, GLuint height0
, GLuint depth0
, GLuint tilebits
)
199 radeon_mipmap_tree
*mt
= CALLOC_STRUCT(_radeon_mipmap_tree
);
201 mt
->mesaFormat
= mesaFormat
;
204 mt
->faces
= (target
== GL_TEXTURE_CUBE_MAP
) ? 6 : 1;
205 mt
->baseLevel
= baseLevel
;
206 mt
->numLevels
= numLevels
;
208 mt
->height0
= height0
;
210 mt
->tilebits
= tilebits
;
212 if (rmesa
->radeonScreen
->chip_family
>= CHIP_FAMILY_R300
)
213 calculate_miptree_layout_r300(rmesa
, mt
);
215 calculate_miptree_layout_r100(rmesa
, mt
);
217 mt
->bo
= radeon_bo_open(rmesa
->radeonScreen
->bom
,
218 0, mt
->totalsize
, 1024,
219 RADEON_GEM_DOMAIN_VRAM
,
225 void radeon_miptree_reference(radeon_mipmap_tree
*mt
, radeon_mipmap_tree
**ptr
)
230 assert(mt
->refcount
> 0);
235 void radeon_miptree_unreference(radeon_mipmap_tree
**ptr
)
237 radeon_mipmap_tree
*mt
= *ptr
;
241 assert(mt
->refcount
> 0);
245 radeon_bo_unref(mt
->bo
);
253 * Calculate min and max LOD for the given texture object.
254 * @param[in] tObj texture object whose LOD values to calculate
255 * @param[out] pminLod minimal LOD
256 * @param[out] pmaxLod maximal LOD
258 static void calculate_min_max_lod(struct gl_texture_object
*tObj
,
259 unsigned *pminLod
, unsigned *pmaxLod
)
262 /* Yes, this looks overly complicated, but it's all needed.
264 switch (tObj
->Target
) {
268 case GL_TEXTURE_CUBE_MAP
:
269 if (tObj
->MinFilter
== GL_NEAREST
|| tObj
->MinFilter
== GL_LINEAR
) {
270 /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
272 minLod
= maxLod
= tObj
->BaseLevel
;
274 minLod
= tObj
->BaseLevel
+ (GLint
)(tObj
->MinLod
);
275 minLod
= MAX2(minLod
, tObj
->BaseLevel
);
276 minLod
= MIN2(minLod
, tObj
->MaxLevel
);
277 maxLod
= tObj
->BaseLevel
+ (GLint
)(tObj
->MaxLod
+ 0.5);
278 maxLod
= MIN2(maxLod
, tObj
->MaxLevel
);
279 maxLod
= MIN2(maxLod
, tObj
->Image
[0][minLod
]->MaxLog2
+ minLod
);
280 maxLod
= MAX2(maxLod
, minLod
); /* need at least one level */
283 case GL_TEXTURE_RECTANGLE_NV
:
284 case GL_TEXTURE_4D_SGIS
:
291 /* save these values */
297 * Checks whether the given miptree can hold the given texture image at the
298 * given face and level.
300 GLboolean
radeon_miptree_matches_image(radeon_mipmap_tree
*mt
,
301 struct gl_texture_image
*texImage
, GLuint face
, GLuint level
)
303 radeon_mipmap_level
*lvl
;
305 if (face
>= mt
->faces
)
308 if (texImage
->TexFormat
!= mt
->mesaFormat
)
311 lvl
= &mt
->levels
[level
];
313 lvl
->width
!= texImage
->Width
||
314 lvl
->height
!= texImage
->Height
||
315 lvl
->depth
!= texImage
->Depth
)
322 * Checks whether the given miptree has the right format to store the given texture object.
324 static GLboolean
radeon_miptree_matches_texture(radeon_mipmap_tree
*mt
, struct gl_texture_object
*texObj
)
326 struct gl_texture_image
*firstImage
;
328 radeon_mipmap_level
*mtBaseLevel
;
330 if (texObj
->BaseLevel
< mt
->baseLevel
)
333 mtBaseLevel
= &mt
->levels
[texObj
->BaseLevel
- mt
->baseLevel
];
334 firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
335 numLevels
= MIN2(texObj
->MaxLevel
- texObj
->BaseLevel
+ 1, firstImage
->MaxLog2
+ 1);
337 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
338 fprintf(stderr
, "Checking if miptree %p matches texObj %p\n", mt
, texObj
);
339 fprintf(stderr
, "target %d vs %d\n", mt
->target
, texObj
->Target
);
340 fprintf(stderr
, "format %d vs %d\n", mt
->mesaFormat
, firstImage
->TexFormat
);
341 fprintf(stderr
, "numLevels %d vs %d\n", mt
->numLevels
, numLevels
);
342 fprintf(stderr
, "width0 %d vs %d\n", mtBaseLevel
->width
, firstImage
->Width
);
343 fprintf(stderr
, "height0 %d vs %d\n", mtBaseLevel
->height
, firstImage
->Height
);
344 fprintf(stderr
, "depth0 %d vs %d\n", mtBaseLevel
->depth
, firstImage
->Depth
);
345 if (mt
->target
== texObj
->Target
&&
346 mt
->mesaFormat
== firstImage
->TexFormat
&&
347 mt
->numLevels
>= numLevels
&&
348 mtBaseLevel
->width
== firstImage
->Width
&&
349 mtBaseLevel
->height
== firstImage
->Height
&&
350 mtBaseLevel
->depth
== firstImage
->Depth
) {
351 fprintf(stderr
, "MATCHED\n");
353 fprintf(stderr
, "NOT MATCHED\n");
357 return (mt
->target
== texObj
->Target
&&
358 mt
->mesaFormat
== firstImage
->TexFormat
&&
359 mt
->numLevels
>= numLevels
&&
360 mtBaseLevel
->width
== firstImage
->Width
&&
361 mtBaseLevel
->height
== firstImage
->Height
&&
362 mtBaseLevel
->depth
== firstImage
->Depth
);
366 * Try to allocate a mipmap tree for the given texture object.
367 * @param[in] rmesa radeon context
368 * @param[in] t radeon texture object
370 void radeon_try_alloc_miptree(radeonContextPtr rmesa
, radeonTexObj
*t
)
372 struct gl_texture_object
*texObj
= &t
->base
;
373 struct gl_texture_image
*texImg
= texObj
->Image
[0][texObj
->BaseLevel
];
381 numLevels
= MIN2(texObj
->MaxLevel
- texObj
->BaseLevel
+ 1, texImg
->MaxLog2
+ 1);
383 t
->mt
= radeon_miptree_create(rmesa
, t
->base
.Target
,
384 texImg
->TexFormat
, texObj
->BaseLevel
,
385 numLevels
, texImg
->Width
, texImg
->Height
,
386 texImg
->Depth
, t
->tile_bits
);
390 radeon_miptree_image_offset(radeon_mipmap_tree
*mt
,
391 GLuint face
, GLuint level
)
393 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARB
)
394 return (mt
->levels
[level
].faces
[face
].offset
);
396 return mt
->levels
[level
].faces
[0].offset
;
400 * Ensure that the given image is stored in the given miptree from now on.
402 static void migrate_image_to_miptree(radeon_mipmap_tree
*mt
,
403 radeon_texture_image
*image
,
406 radeon_mipmap_level
*dstlvl
= &mt
->levels
[level
];
409 assert(image
->mt
!= mt
);
410 assert(dstlvl
->valid
);
411 assert(dstlvl
->width
== image
->base
.Width
);
412 assert(dstlvl
->height
== image
->base
.Height
);
413 assert(dstlvl
->depth
== image
->base
.Depth
);
415 radeon_bo_map(mt
->bo
, GL_TRUE
);
416 dest
= mt
->bo
->ptr
+ dstlvl
->faces
[face
].offset
;
419 /* Format etc. should match, so we really just need a memcpy().
420 * In fact, that memcpy() could be done by the hardware in many
421 * cases, provided that we have a proper memory manager.
423 assert(mt
->mesaFormat
== image
->base
.TexFormat
);
425 radeon_mipmap_level
*srclvl
= &image
->mt
->levels
[image
->mtlevel
];
427 /* TODO: bring back these assertions once the FBOs are fixed */
429 assert(image
->mtlevel
== level
);
430 assert(srclvl
->size
== dstlvl
->size
);
431 assert(srclvl
->rowstride
== dstlvl
->rowstride
);
434 radeon_bo_map(image
->mt
->bo
, GL_FALSE
);
437 image
->mt
->bo
->ptr
+ srclvl
->faces
[face
].offset
,
439 radeon_bo_unmap(image
->mt
->bo
);
441 radeon_miptree_unreference(&image
->mt
);
442 } else if (image
->base
.Data
) {
443 /* This condition should be removed, it's here to workaround
444 * a segfault when mapping textures during software fallbacks.
446 const uint32_t srcrowstride
= _mesa_format_row_stride(image
->base
.TexFormat
, image
->base
.Width
);
447 uint32_t rows
= image
->base
.Height
* image
->base
.Depth
;
449 if (_mesa_is_format_compressed(image
->base
.TexFormat
)) {
450 uint32_t blockWidth
, blockHeight
;
451 _mesa_get_format_block_size(image
->base
.TexFormat
, &blockWidth
, &blockHeight
);
452 rows
= (rows
+ blockHeight
- 1) / blockHeight
;
455 copy_rows(dest
, dstlvl
->rowstride
, image
->base
.Data
, srcrowstride
,
458 _mesa_free_texmemory(image
->base
.Data
);
459 image
->base
.Data
= 0;
462 radeon_bo_unmap(mt
->bo
);
464 radeon_miptree_reference(mt
, &image
->mt
);
465 image
->mtface
= face
;
466 image
->mtlevel
= level
;
470 * Filter matching miptrees, and select one with the most of data.
471 * @param[in] texObj radeon texture object
472 * @param[in] firstLevel first texture level to check
473 * @param[in] lastLevel last texture level to check
475 static radeon_mipmap_tree
* get_biggest_matching_miptree(radeonTexObj
*texObj
,
479 const unsigned numLevels
= lastLevel
- firstLevel
+ 1;
480 unsigned *mtSizes
= calloc(numLevels
, sizeof(unsigned));
481 radeon_mipmap_tree
**mts
= calloc(numLevels
, sizeof(radeon_mipmap_tree
*));
482 unsigned mtCount
= 0;
483 unsigned maxMtIndex
= 0;
484 radeon_mipmap_tree
*tmp
;
486 for (unsigned level
= firstLevel
; level
<= lastLevel
; ++level
) {
487 radeon_texture_image
*img
= get_radeon_texture_image(texObj
->base
.Image
[0][level
]);
489 // TODO: why this hack??
496 for (int i
= 0; i
< mtCount
; ++i
) {
497 if (mts
[i
] == img
->mt
) {
499 mtSizes
[i
] += img
->mt
->levels
[img
->mtlevel
].size
;
504 if (!found
&& radeon_miptree_matches_texture(img
->mt
, &texObj
->base
)) {
505 mtSizes
[mtCount
] = img
->mt
->levels
[img
->mtlevel
].size
;
506 mts
[mtCount
] = img
->mt
;
515 for (int i
= 1; i
< mtCount
; ++i
) {
516 if (mtSizes
[i
] > mtSizes
[maxMtIndex
]) {
521 tmp
= mts
[maxMtIndex
];
529 * Validate texture mipmap tree.
530 * If individual images are stored in different mipmap trees
531 * use the mipmap tree that has the most of the correct data.
533 int radeon_validate_texture_miptree(GLcontext
* ctx
, struct gl_texture_object
*texObj
)
535 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
536 radeonTexObj
*t
= radeon_tex_obj(texObj
);
538 if (t
->validated
|| t
->image_override
) {
542 if (texObj
->Image
[0][texObj
->BaseLevel
]->Border
> 0)
545 _mesa_test_texobj_completeness(rmesa
->glCtx
, texObj
);
546 if (!texObj
->_Complete
) {
550 calculate_min_max_lod(&t
->base
, &t
->minLod
, &t
->maxLod
);
552 if (RADEON_DEBUG
& RADEON_TEXTURE
)
553 fprintf(stderr
, "%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
554 __FUNCTION__
, texObj
,t
->minLod
, t
->maxLod
);
556 radeon_mipmap_tree
*dst_miptree
;
557 dst_miptree
= get_biggest_matching_miptree(t
, t
->minLod
, t
->maxLod
);
560 radeon_miptree_unreference(&t
->mt
);
561 radeon_try_alloc_miptree(rmesa
, t
);
563 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
564 fprintf(stderr
, "%s: No matching miptree found, allocated new one %p\n", __FUNCTION__
, t
->mt
);
566 } else if (RADEON_DEBUG
& RADEON_TEXTURE
) {
567 fprintf(stderr
, "%s: Using miptree %p\n", __FUNCTION__
, t
->mt
);
570 const unsigned faces
= texObj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 : 1;
571 unsigned face
, level
;
572 radeon_texture_image
*img
;
573 /* Validate only the levels that will actually be used during rendering */
574 for (face
= 0; face
< faces
; ++face
) {
575 for (level
= t
->minLod
; level
<= t
->maxLod
; ++level
) {
576 img
= get_radeon_texture_image(texObj
->Image
[face
][level
]);
578 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
579 fprintf(stderr
, "Checking image level %d, face %d, mt %p ... ", level
, face
, img
->mt
);
582 if (img
->mt
!= dst_miptree
) {
583 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
584 fprintf(stderr
, "MIGRATING\n");
586 struct radeon_bo
*src_bo
= (img
->mt
) ? img
->mt
->bo
: img
->bo
;
587 if (src_bo
&& radeon_bo_is_referenced_by_cs(src_bo
, rmesa
->cmdbuf
.cs
)) {
588 radeon_firevertices(rmesa
);
590 migrate_image_to_miptree(dst_miptree
, img
, face
, level
);
591 } else if (RADEON_DEBUG
& RADEON_TEXTURE
) {
592 fprintf(stderr
, "OK\n");
597 t
->validated
= GL_TRUE
;
602 uint32_t get_base_teximage_offset(radeonTexObj
*texObj
)
607 return radeon_miptree_image_offset(texObj
->mt
, 0, texObj
->minLod
);