2 * Copyright (C) 2009 Maciej Cencora.
3 * Copyright (C) 2008 Nicolai Haehnle.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sublicense, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon_mipmap_tree.h"
34 #include "main/simple_list.h"
35 #include "main/texcompress.h"
36 #include "main/teximage.h"
37 #include "main/texobj.h"
38 #include "radeon_texture.h"
40 static unsigned get_aligned_compressed_row_stride(
45 const unsigned blockSize
= _mesa_get_format_bytes(format
);
46 unsigned blockWidth
, blockHeight
, numXBlocks
;
48 _mesa_get_format_block_size(format
, &blockWidth
, &blockHeight
);
49 numXBlocks
= (width
+ blockWidth
- 1) / blockWidth
;
51 while (numXBlocks
* blockSize
< minStride
)
56 return numXBlocks
* blockSize
;
59 static unsigned get_compressed_image_size(
64 unsigned blockWidth
, blockHeight
;
66 _mesa_get_format_block_size(format
, &blockWidth
, &blockHeight
);
68 return rowStride
* ((height
+ blockHeight
- 1) / blockHeight
);
71 static int find_next_power_of_two(GLuint value
)
85 * Compute sizes and fill in offset and blit information for the given
86 * image (determined by \p face and \p level).
88 * \param curOffset points to the offset at which the image is to be stored
89 * and is updated by this function according to the size of the image.
91 static void compute_tex_image_offset(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
,
92 GLuint face
, GLuint level
, GLuint
* curOffset
)
94 radeon_mipmap_level
*lvl
= &mt
->levels
[level
];
98 height
= find_next_power_of_two(lvl
->height
);
100 /* Find image size in bytes */
101 if (_mesa_is_format_compressed(mt
->mesaFormat
)) {
102 lvl
->rowstride
= get_aligned_compressed_row_stride(mt
->mesaFormat
, lvl
->width
, rmesa
->texture_compressed_row_align
);
103 lvl
->size
= get_compressed_image_size(mt
->mesaFormat
, lvl
->rowstride
, height
);
104 } else if (mt
->target
== GL_TEXTURE_RECTANGLE_NV
) {
105 row_align
= rmesa
->texture_rect_row_align
- 1;
106 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
107 lvl
->size
= lvl
->rowstride
* height
;
108 } else if (mt
->tilebits
& RADEON_TXO_MICRO_TILE
) {
109 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
110 * though the actual offset may be different (if texture is less than
111 * 32 bytes width) to the untiled case */
112 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) * 2 + 31) & ~31;
113 lvl
->size
= lvl
->rowstride
* ((height
+ 1) / 2) * lvl
->depth
;
115 row_align
= rmesa
->texture_row_align
- 1;
116 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
117 lvl
->size
= lvl
->rowstride
* height
* lvl
->depth
;
119 assert(lvl
->size
> 0);
121 /* All images are aligned to a 32-byte offset */
122 *curOffset
= (*curOffset
+ 0x1f) & ~0x1f;
123 lvl
->faces
[face
].offset
= *curOffset
;
124 *curOffset
+= lvl
->size
;
126 if (RADEON_DEBUG
& RADEON_TEXTURE
)
128 "level %d, face %d: rs:%d %dx%d at %d\n",
129 level
, face
, lvl
->rowstride
, lvl
->width
, height
, lvl
->faces
[face
].offset
);
132 static GLuint
minify(GLuint size
, GLuint levels
)
134 size
= size
>> levels
;
141 static void calculate_miptree_layout_r100(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
)
147 assert(mt
->numLevels
<= rmesa
->glCtx
->Const
.MaxTextureLevels
);
150 for(face
= 0; face
< mt
->faces
; face
++) {
152 for(i
= 0; i
< mt
->numLevels
; i
++) {
153 mt
->levels
[i
].width
= minify(mt
->width0
, i
);
154 mt
->levels
[i
].height
= minify(mt
->height0
, i
);
155 mt
->levels
[i
].depth
= minify(mt
->depth0
, i
);
156 compute_tex_image_offset(rmesa
, mt
, face
, i
, &curOffset
);
160 /* Note the required size in memory */
161 mt
->totalsize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
164 static void calculate_miptree_layout_r300(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
)
169 assert(mt
->numLevels
<= rmesa
->glCtx
->Const
.MaxTextureLevels
);
172 for(i
= 0; i
< mt
->numLevels
; i
++) {
175 mt
->levels
[i
].width
= minify(mt
->width0
, i
);
176 mt
->levels
[i
].height
= minify(mt
->height0
, i
);
177 mt
->levels
[i
].depth
= minify(mt
->depth0
, i
);
179 for(face
= 0; face
< mt
->faces
; face
++)
180 compute_tex_image_offset(rmesa
, mt
, face
, i
, &curOffset
);
183 /* Note the required size in memory */
184 mt
->totalsize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
188 * Create a new mipmap tree, calculate its layout and allocate memory.
190 static radeon_mipmap_tree
* radeon_miptree_create(radeonContextPtr rmesa
,
191 GLenum target
, gl_format mesaFormat
, GLuint baseLevel
, GLuint numLevels
,
192 GLuint width0
, GLuint height0
, GLuint depth0
, GLuint tilebits
)
194 radeon_mipmap_tree
*mt
= CALLOC_STRUCT(_radeon_mipmap_tree
);
196 mt
->mesaFormat
= mesaFormat
;
199 mt
->faces
= (target
== GL_TEXTURE_CUBE_MAP
) ? 6 : 1;
200 mt
->baseLevel
= baseLevel
;
201 mt
->numLevels
= numLevels
;
203 mt
->height0
= height0
;
205 mt
->tilebits
= tilebits
;
207 if (rmesa
->radeonScreen
->chip_family
>= CHIP_FAMILY_R300
)
208 calculate_miptree_layout_r300(rmesa
, mt
);
210 calculate_miptree_layout_r100(rmesa
, mt
);
212 mt
->bo
= radeon_bo_open(rmesa
->radeonScreen
->bom
,
213 0, mt
->totalsize
, 1024,
214 RADEON_GEM_DOMAIN_VRAM
,
220 void radeon_miptree_reference(radeon_mipmap_tree
*mt
, radeon_mipmap_tree
**ptr
)
225 assert(mt
->refcount
> 0);
230 void radeon_miptree_unreference(radeon_mipmap_tree
**ptr
)
232 radeon_mipmap_tree
*mt
= *ptr
;
236 assert(mt
->refcount
> 0);
240 radeon_bo_unref(mt
->bo
);
248 * Calculate min and max LOD for the given texture object.
249 * @param[in] tObj texture object whose LOD values to calculate
250 * @param[out] pminLod minimal LOD
251 * @param[out] pmaxLod maximal LOD
253 static void calculate_min_max_lod(struct gl_texture_object
*tObj
,
254 unsigned *pminLod
, unsigned *pmaxLod
)
257 /* Yes, this looks overly complicated, but it's all needed.
259 switch (tObj
->Target
) {
263 case GL_TEXTURE_CUBE_MAP
:
264 if (tObj
->MinFilter
== GL_NEAREST
|| tObj
->MinFilter
== GL_LINEAR
) {
265 /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
267 minLod
= maxLod
= tObj
->BaseLevel
;
269 minLod
= tObj
->BaseLevel
+ (GLint
)(tObj
->MinLod
);
270 minLod
= MAX2(minLod
, tObj
->BaseLevel
);
271 minLod
= MIN2(minLod
, tObj
->MaxLevel
);
272 maxLod
= tObj
->BaseLevel
+ (GLint
)(tObj
->MaxLod
+ 0.5);
273 maxLod
= MIN2(maxLod
, tObj
->MaxLevel
);
274 maxLod
= MIN2(maxLod
, tObj
->Image
[0][minLod
]->MaxLog2
+ minLod
);
275 maxLod
= MAX2(maxLod
, minLod
); /* need at least one level */
278 case GL_TEXTURE_RECTANGLE_NV
:
279 case GL_TEXTURE_4D_SGIS
:
286 /* save these values */
292 * Checks whether the given miptree can hold the given texture image at the
293 * given face and level.
295 GLboolean
radeon_miptree_matches_image(radeon_mipmap_tree
*mt
,
296 struct gl_texture_image
*texImage
, GLuint face
, GLuint mtLevel
)
298 radeon_mipmap_level
*lvl
;
300 if (face
>= mt
->faces
|| mtLevel
> mt
->numLevels
)
303 if (texImage
->TexFormat
!= mt
->mesaFormat
)
306 lvl
= &mt
->levels
[mtLevel
];
307 if (lvl
->width
!= texImage
->Width
||
308 lvl
->height
!= texImage
->Height
||
309 lvl
->depth
!= texImage
->Depth
)
316 * Checks whether the given miptree has the right format to store the given texture object.
318 static GLboolean
radeon_miptree_matches_texture(radeon_mipmap_tree
*mt
, struct gl_texture_object
*texObj
)
320 struct gl_texture_image
*firstImage
;
322 radeon_mipmap_level
*mtBaseLevel
;
324 if (texObj
->BaseLevel
< mt
->baseLevel
)
327 mtBaseLevel
= &mt
->levels
[texObj
->BaseLevel
- mt
->baseLevel
];
328 firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
329 numLevels
= MIN2(texObj
->MaxLevel
- texObj
->BaseLevel
+ 1, firstImage
->MaxLog2
+ 1);
331 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
332 fprintf(stderr
, "Checking if miptree %p matches texObj %p\n", mt
, texObj
);
333 fprintf(stderr
, "target %d vs %d\n", mt
->target
, texObj
->Target
);
334 fprintf(stderr
, "format %d vs %d\n", mt
->mesaFormat
, firstImage
->TexFormat
);
335 fprintf(stderr
, "numLevels %d vs %d\n", mt
->numLevels
, numLevels
);
336 fprintf(stderr
, "width0 %d vs %d\n", mtBaseLevel
->width
, firstImage
->Width
);
337 fprintf(stderr
, "height0 %d vs %d\n", mtBaseLevel
->height
, firstImage
->Height
);
338 fprintf(stderr
, "depth0 %d vs %d\n", mtBaseLevel
->depth
, firstImage
->Depth
);
339 if (mt
->target
== texObj
->Target
&&
340 mt
->mesaFormat
== firstImage
->TexFormat
&&
341 mt
->numLevels
>= numLevels
&&
342 mtBaseLevel
->width
== firstImage
->Width
&&
343 mtBaseLevel
->height
== firstImage
->Height
&&
344 mtBaseLevel
->depth
== firstImage
->Depth
) {
345 fprintf(stderr
, "MATCHED\n");
347 fprintf(stderr
, "NOT MATCHED\n");
351 return (mt
->target
== texObj
->Target
&&
352 mt
->mesaFormat
== firstImage
->TexFormat
&&
353 mt
->numLevels
>= numLevels
&&
354 mtBaseLevel
->width
== firstImage
->Width
&&
355 mtBaseLevel
->height
== firstImage
->Height
&&
356 mtBaseLevel
->depth
== firstImage
->Depth
);
360 * Try to allocate a mipmap tree for the given texture object.
361 * @param[in] rmesa radeon context
362 * @param[in] t radeon texture object
364 void radeon_try_alloc_miptree(radeonContextPtr rmesa
, radeonTexObj
*t
)
366 struct gl_texture_object
*texObj
= &t
->base
;
367 struct gl_texture_image
*texImg
= texObj
->Image
[0][texObj
->BaseLevel
];
375 numLevels
= MIN2(texObj
->MaxLevel
- texObj
->BaseLevel
+ 1, texImg
->MaxLog2
+ 1);
377 t
->mt
= radeon_miptree_create(rmesa
, t
->base
.Target
,
378 texImg
->TexFormat
, texObj
->BaseLevel
,
379 numLevels
, texImg
->Width
, texImg
->Height
,
380 texImg
->Depth
, t
->tile_bits
);
383 /* Although we use the image_offset[] array to store relative offsets
384 * to cube faces, Mesa doesn't know anything about this and expects
385 * each cube face to be treated as a separate image.
387 * These functions present that view to mesa:
390 radeon_miptree_depth_offsets(radeon_mipmap_tree
*mt
, GLuint level
, GLuint
*offsets
)
392 if (mt
->target
!= GL_TEXTURE_3D
|| mt
->faces
== 1) {
396 for (i
= 0; i
< 6; i
++) {
397 offsets
[i
] = mt
->levels
[level
].faces
[i
].offset
;
403 radeon_miptree_image_offset(radeon_mipmap_tree
*mt
,
404 GLuint face
, GLuint level
)
406 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARB
)
407 return (mt
->levels
[level
].faces
[face
].offset
);
409 return mt
->levels
[level
].faces
[0].offset
;
413 * Convert radeon miptree texture level to GL texture level
414 * @param[in] tObj texture object whom level is to be converted
415 * @param[in] level radeon miptree texture level
416 * @return GL texture level
418 unsigned radeon_miptree_level_to_gl_level(struct gl_texture_object
*tObj
, unsigned level
)
420 return level
+ tObj
->BaseLevel
;
424 * Convert GL texture level to radeon miptree texture level
425 * @param[in] tObj texture object whom level is to be converted
426 * @param[in] level GL texture level
427 * @return radeon miptree texture level
429 unsigned radeon_gl_level_to_miptree_level(struct gl_texture_object
*tObj
, unsigned level
)
431 return level
- tObj
->BaseLevel
;
435 * Ensure that the given image is stored in the given miptree from now on.
437 static void migrate_image_to_miptree(radeon_mipmap_tree
*mt
,
438 radeon_texture_image
*image
,
439 int face
, int mtLevel
)
441 radeon_mipmap_level
*dstlvl
= &mt
->levels
[mtLevel
];
444 assert(image
->mt
!= mt
);
445 assert(dstlvl
->width
== image
->base
.Width
);
446 assert(dstlvl
->height
== image
->base
.Height
);
447 assert(dstlvl
->depth
== image
->base
.Depth
);
449 radeon_bo_map(mt
->bo
, GL_TRUE
);
450 dest
= mt
->bo
->ptr
+ dstlvl
->faces
[face
].offset
;
453 /* Format etc. should match, so we really just need a memcpy().
454 * In fact, that memcpy() could be done by the hardware in many
455 * cases, provided that we have a proper memory manager.
457 assert(mt
->mesaFormat
== image
->base
.TexFormat
);
459 radeon_mipmap_level
*srclvl
= &image
->mt
->levels
[image
->mtlevel
];
461 assert(srclvl
->size
== dstlvl
->size
);
462 assert(srclvl
->rowstride
== dstlvl
->rowstride
);
464 radeon_bo_map(image
->mt
->bo
, GL_FALSE
);
467 image
->mt
->bo
->ptr
+ srclvl
->faces
[face
].offset
,
469 radeon_bo_unmap(image
->mt
->bo
);
471 radeon_miptree_unreference(&image
->mt
);
473 /* need to confirm this value is correct */
474 if (_mesa_is_format_compressed(image
->base
.TexFormat
)) {
475 unsigned size
= _mesa_format_image_size(image
->base
.TexFormat
,
479 memcpy(dest
, image
->base
.Data
, size
);
481 uint32_t srcrowstride
;
484 height
= image
->base
.Height
* image
->base
.Depth
;
485 srcrowstride
= image
->base
.Width
* _mesa_get_format_bytes(image
->base
.TexFormat
);
486 copy_rows(dest
, dstlvl
->rowstride
, image
->base
.Data
, srcrowstride
,
487 height
, srcrowstride
);
490 _mesa_free_texmemory(image
->base
.Data
);
491 image
->base
.Data
= 0;
494 radeon_bo_unmap(mt
->bo
);
496 radeon_miptree_reference(mt
, &image
->mt
);
497 image
->mtface
= face
;
498 image
->mtlevel
= mtLevel
;
502 * Filter matching miptrees, and select one with the most of data.
503 * @param[in] texObj radeon texture object
504 * @param[in] firstLevel first texture level to check
505 * @param[in] lastLevel last texture level to check
507 static radeon_mipmap_tree
* get_biggest_matching_miptree(radeonTexObj
*texObj
,
511 const unsigned numLevels
= lastLevel
- firstLevel
+ 1;
512 unsigned *mtSizes
= calloc(numLevels
, sizeof(unsigned));
513 radeon_mipmap_tree
**mts
= calloc(numLevels
, sizeof(radeon_mipmap_tree
*));
514 unsigned mtCount
= 0;
515 unsigned maxMtIndex
= 0;
516 radeon_mipmap_tree
*tmp
;
518 for (unsigned level
= firstLevel
; level
<= lastLevel
; ++level
) {
519 radeon_texture_image
*img
= get_radeon_texture_image(texObj
->base
.Image
[0][level
]);
521 // TODO: why this hack??
525 if (!img
->mt
|| !radeon_miptree_matches_texture(img
->mt
, &texObj
->base
))
528 for (int i
= 0; i
< mtCount
; ++i
) {
529 if (mts
[i
] == img
->mt
) {
531 mtSizes
[i
] += img
->mt
->levels
[img
->mtlevel
].size
;
537 mtSizes
[mtCount
] += img
->mt
->levels
[img
->mtlevel
].size
;
538 mts
[mtCount
] = img
->mt
;
547 for (int i
= 1; i
< mtCount
; ++i
) {
548 if (mtSizes
[i
] > mtSizes
[maxMtIndex
]) {
553 tmp
= mts
[maxMtIndex
];
561 * Validate texture mipmap tree.
562 * If individual images are stored in different mipmap trees
563 * use the mipmap tree that has the most of the correct data.
565 int radeon_validate_texture_miptree(GLcontext
* ctx
, struct gl_texture_object
*texObj
)
567 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
568 radeonTexObj
*t
= radeon_tex_obj(texObj
);
570 if (t
->validated
|| t
->image_override
) {
574 if (texObj
->Image
[0][texObj
->BaseLevel
]->Border
> 0)
577 _mesa_test_texobj_completeness(rmesa
->glCtx
, texObj
);
578 if (!texObj
->_Complete
) {
582 calculate_min_max_lod(&t
->base
, &t
->minLod
, &t
->maxLod
);
584 if (RADEON_DEBUG
& RADEON_TEXTURE
)
585 fprintf(stderr
, "%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
586 __FUNCTION__
, texObj
,t
->minLod
, t
->maxLod
);
588 radeon_mipmap_tree
*dst_miptree
;
589 dst_miptree
= get_biggest_matching_miptree(t
, t
->minLod
, t
->maxLod
);
592 radeon_miptree_unreference(&t
->mt
);
593 radeon_try_alloc_miptree(rmesa
, t
);
597 const unsigned faces
= texObj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 : 1;
598 unsigned face
, level
;
599 radeon_texture_image
*img
;
600 /* Validate only the levels that will actually be used during rendering */
601 for (face
= 0; face
< faces
; ++face
) {
602 for (level
= t
->minLod
; level
<= t
->maxLod
; ++level
) {
603 img
= get_radeon_texture_image(texObj
->Image
[face
][level
]);
605 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
606 fprintf(stderr
, "Checking image level %d, face %d, mt %p ... ", level
, face
, img
->mt
);
609 if (img
->mt
!= dst_miptree
) {
610 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
611 fprintf(stderr
, "MIGRATING\n");
613 migrate_image_to_miptree(dst_miptree
, img
, face
, radeon_gl_level_to_miptree_level(texObj
, level
));
614 } else if (RADEON_DEBUG
& RADEON_TEXTURE
) {
615 fprintf(stderr
, "OK\n");
620 t
->validated
= GL_TRUE
;
625 uint32_t get_base_teximage_offset(radeonTexObj
*texObj
)
630 return radeon_miptree_image_offset(texObj
->mt
, 0, texObj
->minLod
);