src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c

   1 /*
   2  * Copyright (C) 2009 Maciej Cencora.
   3  * Copyright (C) 2008 Nicolai Haehnle.
   4  *
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining
   8  * a copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sublicense, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial
  17  * portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  20  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  22  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  23  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  24  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  25  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "radeon_mipmap_tree.h"
  30
  31 #include <errno.h>
  32 #include <unistd.h>
  33
  34 #include "main/simple_list.h"
  35 #include "main/teximage.h"
  36 #include "main/texobj.h"
  37 #include "main/enums.h"
  38 #include "radeon_texture.h"
  39
  40 static unsigned get_aligned_compressed_row_stride(
  41                 gl_format format,
  42                 unsigned width,
  43                 unsigned minStride)
  44 {
  45         const unsigned blockBytes = _mesa_get_format_bytes(format);
  46         unsigned blockWidth, blockHeight;
  47         unsigned stride;
  48
  49         _mesa_get_format_block_size(format, &blockWidth, &blockHeight);
  50
  51         /* Count number of blocks required to store the given width.
  52          * And then multiple it with bytes required to store a block.
  53          */
  54         stride = (width + blockWidth - 1) / blockWidth * blockBytes;
  55
  56         /* Round the given minimum stride to the next full blocksize.
  57          * (minStride + blockBytes - 1) / blockBytes * blockBytes
  58          */
  59         if ( stride < minStride )
  60                 stride = (minStride + blockBytes - 1) / blockBytes * blockBytes;
  61
  62         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
  63                         "%s width %u, minStride %u, block(bytes %u, width %u):"
  64                         "stride %u\n",
  65                         __func__, width, minStride,
  66                         blockBytes, blockWidth,
  67                         stride);
  68
  69         return stride;
  70 }
  71
  72 static unsigned get_compressed_image_size(
  73                 gl_format format,
  74                 unsigned rowStride,
  75                 unsigned height)
  76 {
  77         unsigned blockWidth, blockHeight;
  78
  79         _mesa_get_format_block_size(format, &blockWidth, &blockHeight);
  80
  81         return rowStride * ((height + blockHeight - 1) / blockHeight);
  82 }
  83
  84 static int find_next_power_of_two(GLuint value)
  85 {
  86         int i, tmp;
  87
  88         i = 0;
  89         tmp = value - 1;
  90         while (tmp) {
  91                 tmp >>= 1;
  92                 i++;
  93         }
  94         return (1 << i);
  95 }
  96
  97 /**
  98  * Compute sizes and fill in offset and blit information for the given
  99  * image (determined by \p face and \p level).
 100  *
 101  * \param curOffset points to the offset at which the image is to be stored
 102  * and is updated by this function according to the size of the image.
 103  */
 104 static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt,
 105         GLuint face, GLuint level, GLuint* curOffset)
 106 {
 107         radeon_mipmap_level *lvl = &mt->levels[level];
 108         uint32_t row_align;
 109         GLuint height;
 110
 111         height = find_next_power_of_two(lvl->height);
 112
 113         /* Find image size in bytes */
 114         if (_mesa_is_format_compressed(mt->mesaFormat)) {
 115                 lvl->rowstride = get_aligned_compressed_row_stride(mt->mesaFormat, lvl->width, rmesa->texture_compressed_row_align);
 116                 lvl->size = get_compressed_image_size(mt->mesaFormat, lvl->rowstride, height);
 117         } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) {
 118                 row_align = rmesa->texture_rect_row_align - 1;
 119                 lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align;
 120                 lvl->size = lvl->rowstride * height;
 121         } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) {
 122                 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
 123                  * though the actual offset may be different (if texture is less than
 124                  * 32 bytes width) to the untiled case */
 125                 lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) * 2 + 31) & ~31;
 126                 lvl->size = lvl->rowstride * ((height + 1) / 2) * lvl->depth;
 127         } else {
 128                 row_align = rmesa->texture_row_align - 1;
 129                 lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align;
 130                 lvl->size = lvl->rowstride * height * lvl->depth;
 131         }
 132         assert(lvl->size > 0);
 133
 134         /* All images are aligned to a 32-byte offset */
 135         *curOffset = (*curOffset + 0x1f) & ~0x1f;
 136         lvl->faces[face].offset = *curOffset;
 137         *curOffset += lvl->size;
 138
 139         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 140                         "%s(%p) level %d, face %d: rs:%d %dx%d at %d\n",
 141                         __func__, rmesa,
 142                         level, face,
 143                         lvl->rowstride, lvl->width, height, lvl->faces[face].offset);
 144 }
 145
 146 static GLuint minify(GLuint size, GLuint levels)
 147 {
 148         size = size >> levels;
 149         if (size < 1)
 150                 size = 1;
 151         return size;
 152 }
 153
 154
 155 static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 156 {
 157         GLuint curOffset, i, face, level;
 158
 159         assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
 160
 161         curOffset = 0;
 162         for(face = 0; face < mt->faces; face++) {
 163
 164                 for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
 165                         mt->levels[level].valid = 1;
 166                         mt->levels[level].width = minify(mt->width0, i);
 167                         mt->levels[level].height = minify(mt->height0, i);
 168                         mt->levels[level].depth = minify(mt->depth0, i);
 169                         compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
 170                 }
 171         }
 172
 173         /* Note the required size in memory */
 174         mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
 175
 176         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 177                         "%s(%p, %p) total size %d\n",
 178                         __func__, rmesa, mt, mt->totalsize);
 179 }
 180
 181 static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 182 {
 183         GLuint curOffset, i, level;
 184
 185         assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
 186
 187         curOffset = 0;
 188         for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
 189                 GLuint face;
 190
 191                 mt->levels[level].valid = 1;
 192                 mt->levels[level].width = minify(mt->width0, i);
 193                 mt->levels[level].height = minify(mt->height0, i);
 194                 mt->levels[level].depth = minify(mt->depth0, i);
 195
 196                 for(face = 0; face < mt->faces; face++)
 197                         compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
 198                 /* r600 cube levels seems to be aligned to 8 faces but
 199                  * we have separate register for 1'st level offset so add
 200                  * 2 image alignment after 1'st mip level */
 201                 if(rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R600 &&
 202                    mt->target == GL_TEXTURE_CUBE_MAP && level >= 1)
 203                         curOffset += 2 * mt->levels[level].size;
 204         }
 205
 206         /* Note the required size in memory */
 207         mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
 208
 209         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 210                         "%s(%p, %p) total size %d\n",
 211                         __func__, rmesa, mt, mt->totalsize);
 212 }
 213
 214 /**
 215  * Create a new mipmap tree, calculate its layout and allocate memory.
 216  */
 217 static radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa,
 218                 GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels,
 219                 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
 220 {
 221         radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree);
 222
 223         radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
 224                 "%s(%p) new tree is %p.\n",
 225                 __func__, rmesa, mt);
 226
 227         mt->mesaFormat = mesaFormat;
 228         mt->refcount = 1;
 229         mt->target = target;
 230         mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1;
 231         mt->baseLevel = baseLevel;
 232         mt->numLevels = numLevels;
 233         mt->width0 = width0;
 234         mt->height0 = height0;
 235         mt->depth0 = depth0;
 236         mt->tilebits = tilebits;
 237
 238         if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300)
 239                 calculate_miptree_layout_r300(rmesa, mt);
 240         else
 241                 calculate_miptree_layout_r100(rmesa, mt);
 242
 243         mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
 244                             0, mt->totalsize, 1024,
 245                             RADEON_GEM_DOMAIN_VRAM,
 246                             0);
 247
 248         return mt;
 249 }
 250
 251 void radeon_miptree_reference(radeon_mipmap_tree *mt, radeon_mipmap_tree **ptr)
 252 {
 253         assert(!*ptr);
 254
 255         mt->refcount++;
 256         assert(mt->refcount > 0);
 257
 258         *ptr = mt;
 259 }
 260
 261 void radeon_miptree_unreference(radeon_mipmap_tree **ptr)
 262 {
 263         radeon_mipmap_tree *mt = *ptr;
 264         if (!mt)
 265                 return;
 266
 267         assert(mt->refcount > 0);
 268
 269         mt->refcount--;
 270         if (!mt->refcount) {
 271                 radeon_bo_unref(mt->bo);
 272                 free(mt);
 273         }
 274
 275         *ptr = 0;
 276 }
 277
 278 /**
 279  * Calculate min and max LOD for the given texture object.
 280  * @param[in] tObj texture object whose LOD values to calculate
 281  * @param[out] pminLod minimal LOD
 282  * @param[out] pmaxLod maximal LOD
 283  */
 284 static void calculate_min_max_lod(struct gl_texture_object *tObj,
 285                                        unsigned *pminLod, unsigned *pmaxLod)
 286 {
 287         int minLod, maxLod;
 288         /* Yes, this looks overly complicated, but it's all needed.
 289         */
 290         switch (tObj->Target) {
 291         case GL_TEXTURE_1D:
 292         case GL_TEXTURE_2D:
 293         case GL_TEXTURE_3D:
 294         case GL_TEXTURE_CUBE_MAP:
 295                 if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) {
 296                         /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
 297                         */
 298                         minLod = maxLod = tObj->BaseLevel;
 299                 } else {
 300                         minLod = tObj->BaseLevel + (GLint)(tObj->MinLod);
 301                         minLod = MAX2(minLod, tObj->BaseLevel);
 302                         minLod = MIN2(minLod, tObj->MaxLevel);
 303                         maxLod = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5);
 304                         maxLod = MIN2(maxLod, tObj->MaxLevel);
 305                         maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxLog2 + minLod);
 306                         maxLod = MAX2(maxLod, minLod); /* need at least one level */
 307                 }
 308                 break;
 309         case GL_TEXTURE_RECTANGLE_NV:
 310         case GL_TEXTURE_4D_SGIS:
 311                 minLod = maxLod = 0;
 312                 break;
 313         default:
 314                 return;
 315         }
 316
 317         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 318                         "%s(%p) target %s, min %d, max %d.\n",
 319                         __func__, tObj,
 320                         _mesa_lookup_enum_by_nr(tObj->Target),
 321                         minLod, maxLod);
 322
 323         /* save these values */
 324         *pminLod = minLod;
 325         *pmaxLod = maxLod;
 326 }
 327
 328 /**
 329  * Checks whether the given miptree can hold the given texture image at the
 330  * given face and level.
 331  */
 332 GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
 333                 struct gl_texture_image *texImage, GLuint face, GLuint level)
 334 {
 335         radeon_mipmap_level *lvl;
 336
 337         if (face >= mt->faces)
 338                 return GL_FALSE;
 339
 340         if (texImage->TexFormat != mt->mesaFormat)
 341                 return GL_FALSE;
 342
 343         lvl = &mt->levels[level];
 344         if (!lvl->valid ||
 345             lvl->width != texImage->Width ||
 346             lvl->height != texImage->Height ||
 347             lvl->depth != texImage->Depth)
 348                 return GL_FALSE;
 349
 350         return GL_TRUE;
 351 }
 352
 353 /**
 354  * Checks whether the given miptree has the right format to store the given texture object.
 355  */
 356 static GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj)
 357 {
 358         struct gl_texture_image *firstImage;
 359         unsigned numLevels;
 360         radeon_mipmap_level *mtBaseLevel;
 361
 362         if (texObj->BaseLevel < mt->baseLevel)
 363                 return GL_FALSE;
 364
 365         mtBaseLevel = &mt->levels[texObj->BaseLevel - mt->baseLevel];
 366         firstImage = texObj->Image[0][texObj->BaseLevel];
 367         numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, firstImage->MaxLog2 + 1);
 368
 369         if (radeon_is_debug_enabled(RADEON_TEXTURE,RADEON_TRACE)) {
 370                 fprintf(stderr, "Checking if miptree %p matches texObj %p\n", mt, texObj);
 371                 fprintf(stderr, "target %d vs %d\n", mt->target, texObj->Target);
 372                 fprintf(stderr, "format %d vs %d\n", mt->mesaFormat, firstImage->TexFormat);
 373                 fprintf(stderr, "numLevels %d vs %d\n", mt->numLevels, numLevels);
 374                 fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width);
 375                 fprintf(stderr, "height0 %d vs %d\n", mtBaseLevel->height, firstImage->Height);
 376                 fprintf(stderr, "depth0 %d vs %d\n", mtBaseLevel->depth, firstImage->Depth);
 377                 if (mt->target == texObj->Target &&
 378                 mt->mesaFormat == firstImage->TexFormat &&
 379                 mt->numLevels >= numLevels &&
 380                 mtBaseLevel->width == firstImage->Width &&
 381                 mtBaseLevel->height == firstImage->Height &&
 382                 mtBaseLevel->depth == firstImage->Depth) {
 383                         fprintf(stderr, "MATCHED\n");
 384                 } else {
 385                         fprintf(stderr, "NOT MATCHED\n");
 386                 }
 387         }
 388
 389         return (mt->target == texObj->Target &&
 390                 mt->mesaFormat == firstImage->TexFormat &&
 391                 mt->numLevels >= numLevels &&
 392                 mtBaseLevel->width == firstImage->Width &&
 393                 mtBaseLevel->height == firstImage->Height &&
 394                 mtBaseLevel->depth == firstImage->Depth);
 395 }
 396
 397 /**
 398  * Try to allocate a mipmap tree for the given texture object.
 399  * @param[in] rmesa radeon context
 400  * @param[in] t radeon texture object
 401  */
 402 void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t)
 403 {
 404         struct gl_texture_object *texObj = &t->base;
 405         struct gl_texture_image *texImg = texObj->Image[0][texObj->BaseLevel];
 406         GLuint numLevels;
 407
 408         assert(!t->mt);
 409
 410         if (!texImg) {
 411                 radeon_warning("%s(%p) No image in given texture object(%p).\n",
 412                                 __func__, rmesa, t);
 413                 return;
 414         }
 415
 416
 417         numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, texImg->MaxLog2 + 1);
 418
 419         t->mt = radeon_miptree_create(rmesa, t->base.Target,
 420                 texImg->TexFormat, texObj->BaseLevel,
 421                 numLevels, texImg->Width, texImg->Height,
 422                 texImg->Depth, t->tile_bits);
 423 }
 424
 425 GLuint
 426 radeon_miptree_image_offset(radeon_mipmap_tree *mt,
 427                             GLuint face, GLuint level)
 428 {
 429         if (mt->target == GL_TEXTURE_CUBE_MAP_ARB)
 430                 return (mt->levels[level].faces[face].offset);
 431         else
 432                 return mt->levels[level].faces[0].offset;
 433 }
 434
 435 /**
 436  * Ensure that the given image is stored in the given miptree from now on.
 437  */
 438 static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
 439                                                                          radeon_texture_image *image,
 440                                                                          int face, int level)
 441 {
 442         radeon_mipmap_level *dstlvl = &mt->levels[level];
 443         unsigned char *dest;
 444
 445         assert(image->mt != mt);
 446         assert(dstlvl->valid);
 447         assert(dstlvl->width == image->base.Width);
 448         assert(dstlvl->height == image->base.Height);
 449         assert(dstlvl->depth == image->base.Depth);
 450
 451         radeon_print(RADEON_TEXTURE, RADEON_VERBOSE,
 452                         "%s miptree %p, image %p, face %d, level %d.\n",
 453                         __func__, mt, image, face, level);
 454
 455         radeon_bo_map(mt->bo, GL_TRUE);
 456         dest = mt->bo->ptr + dstlvl->faces[face].offset;
 457
 458         if (image->mt) {
 459                 /* Format etc. should match, so we really just need a memcpy().
 460                  * In fact, that memcpy() could be done by the hardware in many
 461                  * cases, provided that we have a proper memory manager.
 462                  */
 463                 assert(mt->mesaFormat == image->base.TexFormat);
 464
 465                 radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel];
 466
 467                 /* TODO: bring back these assertions once the FBOs are fixed */
 468 #if 0
 469                 assert(image->mtlevel == level);
 470                 assert(srclvl->size == dstlvl->size);
 471                 assert(srclvl->rowstride == dstlvl->rowstride);
 472 #endif
 473
 474                 radeon_bo_map(image->mt->bo, GL_FALSE);
 475
 476                 memcpy(dest,
 477                         image->mt->bo->ptr + srclvl->faces[face].offset,
 478                         dstlvl->size);
 479                 radeon_bo_unmap(image->mt->bo);
 480
 481                 radeon_miptree_unreference(&image->mt);
 482         } else if (image->base.Data) {
 483                 /* This condition should be removed, it's here to workaround
 484                  * a segfault when mapping textures during software fallbacks.
 485                  */
 486                 radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
 487                                 "%s Trying to map texture in sowftware fallback.\n",
 488                                 __func__);
 489                 const uint32_t srcrowstride = _mesa_format_row_stride(image->base.TexFormat, image->base.Width);
 490                 uint32_t rows = image->base.Height * image->base.Depth;
 491
 492                 if (_mesa_is_format_compressed(image->base.TexFormat)) {
 493                         uint32_t blockWidth, blockHeight;
 494                         _mesa_get_format_block_size(image->base.TexFormat, &blockWidth, &blockHeight);
 495                         rows = (rows + blockHeight - 1) / blockHeight;
 496                 }
 497
 498                 copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride,
 499                                   rows, srcrowstride);
 500
 501                 _mesa_free_texmemory(image->base.Data);
 502                 image->base.Data = 0;
 503         }
 504
 505         radeon_bo_unmap(mt->bo);
 506
 507         radeon_miptree_reference(mt, &image->mt);
 508         image->mtface = face;
 509         image->mtlevel = level;
 510 }
 511
 512 /**
 513  * Filter matching miptrees, and select one with the most of data.
 514  * @param[in] texObj radeon texture object
 515  * @param[in] firstLevel first texture level to check
 516  * @param[in] lastLevel last texture level to check
 517  */
 518 static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj,
 519                                                                                                                  unsigned firstLevel,
 520                                                                                                                  unsigned lastLevel)
 521 {
 522         const unsigned numLevels = lastLevel - firstLevel + 1;
 523         unsigned *mtSizes = calloc(numLevels, sizeof(unsigned));
 524         radeon_mipmap_tree **mts = calloc(numLevels, sizeof(radeon_mipmap_tree *));
 525         unsigned mtCount = 0;
 526         unsigned maxMtIndex = 0;
 527         radeon_mipmap_tree *tmp;
 528
 529         for (unsigned level = firstLevel; level <= lastLevel; ++level) {
 530                 radeon_texture_image *img = get_radeon_texture_image(texObj->base.Image[0][level]);
 531                 unsigned found = 0;
 532                 // TODO: why this hack??
 533                 if (!img)
 534                         break;
 535
 536                 if (!img->mt)
 537                         continue;
 538
 539                 for (int i = 0; i < mtCount; ++i) {
 540                         if (mts[i] == img->mt) {
 541                                 found = 1;
 542                                 mtSizes[i] += img->mt->levels[img->mtlevel].size;
 543                                 break;
 544                         }
 545                 }
 546
 547                 if (!found && radeon_miptree_matches_texture(img->mt, &texObj->base)) {
 548                         mtSizes[mtCount] = img->mt->levels[img->mtlevel].size;
 549                         mts[mtCount] = img->mt;
 550                         mtCount++;
 551                 }
 552         }
 553
 554         if (mtCount == 0) {
 555                 return NULL;
 556         }
 557
 558         for (int i = 1; i < mtCount; ++i) {
 559                 if (mtSizes[i] > mtSizes[maxMtIndex]) {
 560                         maxMtIndex = i;
 561                 }
 562         }
 563
 564         tmp = mts[maxMtIndex];
 565         free(mtSizes);
 566         free(mts);
 567
 568         return tmp;
 569 }
 570
 571 /**
 572  * Validate texture mipmap tree.
 573  * If individual images are stored in different mipmap trees
 574  * use the mipmap tree that has the most of the correct data.
 575  */
 576 int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj)
 577 {
 578         radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 579         radeonTexObj *t = radeon_tex_obj(texObj);
 580
 581         if (t->validated || t->image_override) {
 582                 return GL_TRUE;
 583         }
 584
 585         if (texObj->Image[0][texObj->BaseLevel]->Border > 0)
 586                 return GL_FALSE;
 587
 588         _mesa_test_texobj_completeness(rmesa->glCtx, texObj);
 589         if (!texObj->_Complete) {
 590                 return GL_FALSE;
 591         }
 592
 593         calculate_min_max_lod(&t->base, &t->minLod, &t->maxLod);
 594
 595         radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
 596                         "%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
 597                         __FUNCTION__, texObj ,t->minLod, t->maxLod);
 598
 599         radeon_mipmap_tree *dst_miptree;
 600         dst_miptree = get_biggest_matching_miptree(t, t->minLod, t->maxLod);
 601
 602         if (!dst_miptree) {
 603                 radeon_miptree_unreference(&t->mt);
 604                 radeon_try_alloc_miptree(rmesa, t);
 605                 dst_miptree = t->mt;
 606                 radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
 607                         "%s: No matching miptree found, allocated new one %p\n",
 608                         __FUNCTION__, t->mt);
 609
 610         } else {
 611                 radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
 612                         "%s: Using miptree %p\n", __FUNCTION__, t->mt);
 613         }
 614
 615         const unsigned faces = texObj->Target == GL_TEXTURE_CUBE_MAP ? 6 : 1;
 616         unsigned face, level;
 617         radeon_texture_image *img;
 618         /* Validate only the levels that will actually be used during rendering */
 619         for (face = 0; face < faces; ++face) {
 620                 for (level = t->minLod; level <= t->maxLod; ++level) {
 621                         img = get_radeon_texture_image(texObj->Image[face][level]);
 622
 623                         radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 624                                 "Checking image level %d, face %d, mt %p ... ",
 625                                 level, face, img->mt);
 626
 627                         if (img->mt != dst_miptree) {
 628                                 radeon_print(RADEON_TEXTURE, RADEON_TRACE,
 629                                         "MIGRATING\n");
 630
 631                                 struct radeon_bo *src_bo = (img->mt) ? img->mt->bo : img->bo;
 632                                 if (src_bo && radeon_bo_is_referenced_by_cs(src_bo, rmesa->cmdbuf.cs)) {
 633                                         radeon_firevertices(rmesa);
 634                                 }
 635                                 migrate_image_to_miptree(dst_miptree, img, face, level);
 636                         } else
 637                                 radeon_print(RADEON_TEXTURE, RADEON_TRACE, "OK\n");
 638                 }
 639         }
 640
 641         t->validated = GL_TRUE;
 642
 643         return GL_TRUE;
 644 }
 645
 646 uint32_t get_base_teximage_offset(radeonTexObj *texObj)
 647 {
 648         if (!texObj->mt) {
 649                 return 0;
 650         } else {
 651                 return radeon_miptree_image_offset(texObj->mt, 0, texObj->minLod);
 652         }
 653 }