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Merge commit 'origin/7.8'
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #if defined(RADEON_R100)
51 #include "radeon_context.h"
52 #include "radeon_tex.h"
53 #elif defined(RADEON_R200)
54 #include "r200_context.h"
55 #include "r200_ioctl.h"
56 #include "r200_tex.h"
57 #elif defined(RADEON_R300)
58 #include "r300_context.h"
59 #include "r300_tex.h"
60 #elif defined(RADEON_R600)
61 #include "r600_context.h"
62 #include "r700_driconf.h" /* +r6/r7 */
63 #include "r600_tex.h" /* +r6/r7 */
64 #endif
65
66 #include "utils.h"
67 #include "vblank.h"
68
69 #include "radeon_bocs_wrapper.h"
70
71 #include "GL/internal/dri_interface.h"
72
73 /* Radeon configuration
74 */
75 #include "xmlpool.h"
76
77 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
78 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
79 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
80 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
81 DRI_CONF_OPT_END
82
83 #if defined(RADEON_R100) /* R100 */
84 PUBLIC const char __driConfigOptions[] =
85 DRI_CONF_BEGIN
86 DRI_CONF_SECTION_PERFORMANCE
87 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
88 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
89 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
90 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
91 DRI_CONF_HYPERZ(false)
92 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
93 DRI_CONF_SECTION_END
94 DRI_CONF_SECTION_QUALITY
95 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
96 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
97 DRI_CONF_NO_NEG_LOD_BIAS(false)
98 DRI_CONF_FORCE_S3TC_ENABLE(false)
99 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
100 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
101 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
102 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
103 DRI_CONF_SECTION_END
104 DRI_CONF_SECTION_DEBUG
105 DRI_CONF_NO_RAST(false)
106 DRI_CONF_SECTION_END
107 DRI_CONF_END;
108 static const GLuint __driNConfigOptions = 15;
109
110 #elif defined(RADEON_R200)
111
112 PUBLIC const char __driConfigOptions[] =
113 DRI_CONF_BEGIN
114 DRI_CONF_SECTION_PERFORMANCE
115 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
116 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
117 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
118 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
119 DRI_CONF_HYPERZ(false)
120 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
121 DRI_CONF_SECTION_END
122 DRI_CONF_SECTION_QUALITY
123 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
124 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
125 DRI_CONF_NO_NEG_LOD_BIAS(false)
126 DRI_CONF_FORCE_S3TC_ENABLE(false)
127 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
128 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
129 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
130 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
131 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
132 DRI_CONF_SECTION_END
133 DRI_CONF_SECTION_DEBUG
134 DRI_CONF_NO_RAST(false)
135 DRI_CONF_SECTION_END
136 DRI_CONF_SECTION_SOFTWARE
137 DRI_CONF_NV_VERTEX_PROGRAM(false)
138 DRI_CONF_SECTION_END
139 DRI_CONF_END;
140 static const GLuint __driNConfigOptions = 17;
141
142 #elif defined(RADEON_R300) || defined(RADEON_R600)
143
144 #define DRI_CONF_FP_OPTIMIZATION_SPEED 0
145 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
146
147 /* TODO: integrate these into xmlpool.h! */
148 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
149 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
150 DRI_CONF_DESC(en,"Number of texture image units") \
151 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
152 DRI_CONF_OPT_END
153
154 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
155 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
156 DRI_CONF_DESC(en,"Number of texture coordinate units") \
157 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
158 DRI_CONF_OPT_END
159
160
161
162 #define DRI_CONF_DISABLE_S3TC(def) \
163 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
164 DRI_CONF_DESC(en,"Disable S3TC compression") \
165 DRI_CONF_OPT_END
166
167 #define DRI_CONF_DISABLE_FALLBACK(def) \
168 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
169 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
170 DRI_CONF_OPT_END
171
172 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
173 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
174 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
175 DRI_CONF_OPT_END
176
177 #define DRI_CONF_FP_OPTIMIZATION(def) \
178 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
179 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
180 DRI_CONF_ENUM(0,"Optimize for Speed") \
181 DRI_CONF_ENUM(1,"Optimize for Quality") \
182 DRI_CONF_DESC_END \
183 DRI_CONF_OPT_END
184
185 PUBLIC const char __driConfigOptions[] =
186 DRI_CONF_BEGIN
187 DRI_CONF_SECTION_PERFORMANCE
188 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
189 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
190 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
191 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
192 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
193 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
194 DRI_CONF_DISABLE_FALLBACK(true)
195 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
196 DRI_CONF_SECTION_END
197 DRI_CONF_SECTION_QUALITY
198 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
199 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
200 DRI_CONF_FORCE_S3TC_ENABLE(false)
201 DRI_CONF_DISABLE_S3TC(false)
202 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
203 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
204 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
205 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
206 DRI_CONF_SECTION_END
207 DRI_CONF_SECTION_DEBUG
208 DRI_CONF_NO_RAST(false)
209 DRI_CONF_SECTION_END
210 DRI_CONF_END;
211 static const GLuint __driNConfigOptions = 17;
212
213 #endif
214
215 static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo );
216
217 static int
218 radeonGetParam(__DRIscreen *sPriv, int param, void *value)
219 {
220 int ret;
221 drm_radeon_getparam_t gp = { 0 };
222 struct drm_radeon_info info = { 0 };
223
224 if (sPriv->drm_version.major >= 2) {
225 info.value = (uint64_t)(uintptr_t)value;
226 switch (param) {
227 case RADEON_PARAM_DEVICE_ID:
228 info.request = RADEON_INFO_DEVICE_ID;
229 break;
230 case RADEON_PARAM_NUM_GB_PIPES:
231 info.request = RADEON_INFO_NUM_GB_PIPES;
232 break;
233 case RADEON_PARAM_NUM_Z_PIPES:
234 info.request = RADEON_INFO_NUM_Z_PIPES;
235 break;
236 default:
237 return -EINVAL;
238 }
239 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
240 } else {
241 gp.param = param;
242 gp.value = value;
243
244 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
245 }
246 return ret;
247 }
248
249 static const __DRIconfig **
250 radeonFillInModes( __DRIscreen *psp,
251 unsigned pixel_bits, unsigned depth_bits,
252 unsigned stencil_bits, GLboolean have_back_buffer )
253 {
254 __DRIconfig **configs;
255 __GLcontextModes *m;
256 unsigned depth_buffer_factor;
257 unsigned back_buffer_factor;
258 int i;
259
260 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
261 * enough to add support. Basically, if a context is created with an
262 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
263 * will never be used.
264 */
265 static const GLenum back_buffer_modes[] = {
266 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
267 };
268
269 uint8_t depth_bits_array[2];
270 uint8_t stencil_bits_array[2];
271 uint8_t msaa_samples_array[1];
272
273 depth_bits_array[0] = depth_bits;
274 depth_bits_array[1] = depth_bits;
275
276 /* Just like with the accumulation buffer, always provide some modes
277 * with a stencil buffer. It will be a sw fallback, but some apps won't
278 * care about that.
279 */
280 stencil_bits_array[0] = stencil_bits;
281 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
282
283 msaa_samples_array[0] = 0;
284
285 depth_buffer_factor = (stencil_bits == 0) ? 2 : 1;
286 back_buffer_factor = (have_back_buffer) ? 2 : 1;
287
288 if (pixel_bits == 16) {
289 __DRIconfig **configs_a8r8g8b8;
290 __DRIconfig **configs_r5g6b5;
291
292 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
293 depth_bits_array, stencil_bits_array,
294 depth_buffer_factor, back_buffer_modes,
295 back_buffer_factor, msaa_samples_array,
296 1, GL_TRUE);
297 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
298 depth_bits_array, stencil_bits_array,
299 1, back_buffer_modes, 1,
300 msaa_samples_array, 1, GL_TRUE);
301 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
302 } else
303 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
304 depth_bits_array, stencil_bits_array,
305 depth_buffer_factor,
306 back_buffer_modes, back_buffer_factor,
307 msaa_samples_array, 1, GL_TRUE);
308
309 if (configs == NULL) {
310 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
311 __func__, __LINE__ );
312 return NULL;
313 }
314
315 /* Mark the visual as slow if there are "fake" stencil bits.
316 */
317 for (i = 0; configs[i]; i++) {
318 m = &configs[i]->modes;
319 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
320 m->visualRating = GLX_SLOW_CONFIG;
321 }
322 }
323
324 return (const __DRIconfig **) configs;
325 }
326
327 #if defined(RADEON_R100)
328 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
329 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
330 radeonSetTexOffset,
331 };
332
333 static const __DRItexBufferExtension radeonTexBufferExtension = {
334 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
335 radeonSetTexBuffer,
336 radeonSetTexBuffer2,
337 };
338 #endif
339
340 #if defined(RADEON_R200)
341 static const __DRIallocateExtension r200AllocateExtension = {
342 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
343 r200AllocateMemoryMESA,
344 r200FreeMemoryMESA,
345 r200GetMemoryOffsetMESA
346 };
347
348 static const __DRItexOffsetExtension r200texOffsetExtension = {
349 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
350 r200SetTexOffset,
351 };
352
353 static const __DRItexBufferExtension r200TexBufferExtension = {
354 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
355 r200SetTexBuffer,
356 r200SetTexBuffer2,
357 };
358 #endif
359
360 #if defined(RADEON_R300)
361 static const __DRItexOffsetExtension r300texOffsetExtension = {
362 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
363 r300SetTexOffset,
364 };
365
366 static const __DRItexBufferExtension r300TexBufferExtension = {
367 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
368 r300SetTexBuffer,
369 r300SetTexBuffer2,
370 };
371 #endif
372
373 #if defined(RADEON_R600)
374 static const __DRItexOffsetExtension r600texOffsetExtension = {
375 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
376 r600SetTexOffset, /* +r6/r7 */
377 };
378
379 static const __DRItexBufferExtension r600TexBufferExtension = {
380 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
381 r600SetTexBuffer, /* +r6/r7 */
382 r600SetTexBuffer2, /* +r6/r7 */
383 };
384 #endif
385
386 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
387 {
388 screen->device_id = device_id;
389 screen->chip_flags = 0;
390 switch ( device_id ) {
391 case PCI_CHIP_RN50_515E:
392 case PCI_CHIP_RN50_5969:
393 return -1;
394
395 case PCI_CHIP_RADEON_LY:
396 case PCI_CHIP_RADEON_LZ:
397 case PCI_CHIP_RADEON_QY:
398 case PCI_CHIP_RADEON_QZ:
399 screen->chip_family = CHIP_FAMILY_RV100;
400 break;
401
402 case PCI_CHIP_RS100_4136:
403 case PCI_CHIP_RS100_4336:
404 screen->chip_family = CHIP_FAMILY_RS100;
405 break;
406
407 case PCI_CHIP_RS200_4137:
408 case PCI_CHIP_RS200_4337:
409 case PCI_CHIP_RS250_4237:
410 case PCI_CHIP_RS250_4437:
411 screen->chip_family = CHIP_FAMILY_RS200;
412 break;
413
414 case PCI_CHIP_RADEON_QD:
415 case PCI_CHIP_RADEON_QE:
416 case PCI_CHIP_RADEON_QF:
417 case PCI_CHIP_RADEON_QG:
418 /* all original radeons (7200) presumably have a stencil op bug */
419 screen->chip_family = CHIP_FAMILY_R100;
420 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
421 break;
422
423 case PCI_CHIP_RV200_QW:
424 case PCI_CHIP_RV200_QX:
425 case PCI_CHIP_RADEON_LW:
426 case PCI_CHIP_RADEON_LX:
427 screen->chip_family = CHIP_FAMILY_RV200;
428 screen->chip_flags = RADEON_CHIPSET_TCL;
429 break;
430
431 case PCI_CHIP_R200_BB:
432 case PCI_CHIP_R200_BC:
433 case PCI_CHIP_R200_QH:
434 case PCI_CHIP_R200_QL:
435 case PCI_CHIP_R200_QM:
436 screen->chip_family = CHIP_FAMILY_R200;
437 screen->chip_flags = RADEON_CHIPSET_TCL;
438 break;
439
440 case PCI_CHIP_RV250_If:
441 case PCI_CHIP_RV250_Ig:
442 case PCI_CHIP_RV250_Ld:
443 case PCI_CHIP_RV250_Lf:
444 case PCI_CHIP_RV250_Lg:
445 screen->chip_family = CHIP_FAMILY_RV250;
446 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
447 break;
448
449 case PCI_CHIP_RV280_5960:
450 case PCI_CHIP_RV280_5961:
451 case PCI_CHIP_RV280_5962:
452 case PCI_CHIP_RV280_5964:
453 case PCI_CHIP_RV280_5965:
454 case PCI_CHIP_RV280_5C61:
455 case PCI_CHIP_RV280_5C63:
456 screen->chip_family = CHIP_FAMILY_RV280;
457 screen->chip_flags = RADEON_CHIPSET_TCL;
458 break;
459
460 case PCI_CHIP_RS300_5834:
461 case PCI_CHIP_RS300_5835:
462 case PCI_CHIP_RS350_7834:
463 case PCI_CHIP_RS350_7835:
464 screen->chip_family = CHIP_FAMILY_RS300;
465 break;
466
467 case PCI_CHIP_R300_AD:
468 case PCI_CHIP_R300_AE:
469 case PCI_CHIP_R300_AF:
470 case PCI_CHIP_R300_AG:
471 case PCI_CHIP_R300_ND:
472 case PCI_CHIP_R300_NE:
473 case PCI_CHIP_R300_NF:
474 case PCI_CHIP_R300_NG:
475 screen->chip_family = CHIP_FAMILY_R300;
476 screen->chip_flags = RADEON_CHIPSET_TCL;
477 break;
478
479 case PCI_CHIP_RV350_AP:
480 case PCI_CHIP_RV350_AQ:
481 case PCI_CHIP_RV350_AR:
482 case PCI_CHIP_RV350_AS:
483 case PCI_CHIP_RV350_AT:
484 case PCI_CHIP_RV350_AV:
485 case PCI_CHIP_RV350_AU:
486 case PCI_CHIP_RV350_NP:
487 case PCI_CHIP_RV350_NQ:
488 case PCI_CHIP_RV350_NR:
489 case PCI_CHIP_RV350_NS:
490 case PCI_CHIP_RV350_NT:
491 case PCI_CHIP_RV350_NV:
492 screen->chip_family = CHIP_FAMILY_RV350;
493 screen->chip_flags = RADEON_CHIPSET_TCL;
494 break;
495
496 case PCI_CHIP_R350_AH:
497 case PCI_CHIP_R350_AI:
498 case PCI_CHIP_R350_AJ:
499 case PCI_CHIP_R350_AK:
500 case PCI_CHIP_R350_NH:
501 case PCI_CHIP_R350_NI:
502 case PCI_CHIP_R360_NJ:
503 case PCI_CHIP_R350_NK:
504 screen->chip_family = CHIP_FAMILY_R350;
505 screen->chip_flags = RADEON_CHIPSET_TCL;
506 break;
507
508 case PCI_CHIP_RV370_5460:
509 case PCI_CHIP_RV370_5462:
510 case PCI_CHIP_RV370_5464:
511 case PCI_CHIP_RV370_5B60:
512 case PCI_CHIP_RV370_5B62:
513 case PCI_CHIP_RV370_5B63:
514 case PCI_CHIP_RV370_5B64:
515 case PCI_CHIP_RV370_5B65:
516 case PCI_CHIP_RV380_3150:
517 case PCI_CHIP_RV380_3152:
518 case PCI_CHIP_RV380_3154:
519 case PCI_CHIP_RV380_3E50:
520 case PCI_CHIP_RV380_3E54:
521 screen->chip_family = CHIP_FAMILY_RV380;
522 screen->chip_flags = RADEON_CHIPSET_TCL;
523 break;
524
525 case PCI_CHIP_R420_JN:
526 case PCI_CHIP_R420_JH:
527 case PCI_CHIP_R420_JI:
528 case PCI_CHIP_R420_JJ:
529 case PCI_CHIP_R420_JK:
530 case PCI_CHIP_R420_JL:
531 case PCI_CHIP_R420_JM:
532 case PCI_CHIP_R420_JO:
533 case PCI_CHIP_R420_JP:
534 case PCI_CHIP_R420_JT:
535 case PCI_CHIP_R481_4B49:
536 case PCI_CHIP_R481_4B4A:
537 case PCI_CHIP_R481_4B4B:
538 case PCI_CHIP_R481_4B4C:
539 case PCI_CHIP_R423_UH:
540 case PCI_CHIP_R423_UI:
541 case PCI_CHIP_R423_UJ:
542 case PCI_CHIP_R423_UK:
543 case PCI_CHIP_R430_554C:
544 case PCI_CHIP_R430_554D:
545 case PCI_CHIP_R430_554E:
546 case PCI_CHIP_R430_554F:
547 case PCI_CHIP_R423_5550:
548 case PCI_CHIP_R423_UQ:
549 case PCI_CHIP_R423_UR:
550 case PCI_CHIP_R423_UT:
551 case PCI_CHIP_R430_5D48:
552 case PCI_CHIP_R430_5D49:
553 case PCI_CHIP_R430_5D4A:
554 case PCI_CHIP_R480_5D4C:
555 case PCI_CHIP_R480_5D4D:
556 case PCI_CHIP_R480_5D4E:
557 case PCI_CHIP_R480_5D4F:
558 case PCI_CHIP_R480_5D50:
559 case PCI_CHIP_R480_5D52:
560 case PCI_CHIP_R423_5D57:
561 screen->chip_family = CHIP_FAMILY_R420;
562 screen->chip_flags = RADEON_CHIPSET_TCL;
563 break;
564
565 case PCI_CHIP_RV410_5E4C:
566 case PCI_CHIP_RV410_5E4F:
567 case PCI_CHIP_RV410_564A:
568 case PCI_CHIP_RV410_564B:
569 case PCI_CHIP_RV410_564F:
570 case PCI_CHIP_RV410_5652:
571 case PCI_CHIP_RV410_5653:
572 case PCI_CHIP_RV410_5657:
573 case PCI_CHIP_RV410_5E48:
574 case PCI_CHIP_RV410_5E4A:
575 case PCI_CHIP_RV410_5E4B:
576 case PCI_CHIP_RV410_5E4D:
577 screen->chip_family = CHIP_FAMILY_RV410;
578 screen->chip_flags = RADEON_CHIPSET_TCL;
579 break;
580
581 case PCI_CHIP_RS480_5954:
582 case PCI_CHIP_RS480_5955:
583 case PCI_CHIP_RS482_5974:
584 case PCI_CHIP_RS482_5975:
585 case PCI_CHIP_RS400_5A41:
586 case PCI_CHIP_RS400_5A42:
587 case PCI_CHIP_RC410_5A61:
588 case PCI_CHIP_RC410_5A62:
589 screen->chip_family = CHIP_FAMILY_RS400;
590 break;
591
592 case PCI_CHIP_RS600_793F:
593 case PCI_CHIP_RS600_7941:
594 case PCI_CHIP_RS600_7942:
595 screen->chip_family = CHIP_FAMILY_RS600;
596 break;
597
598 case PCI_CHIP_RS690_791E:
599 case PCI_CHIP_RS690_791F:
600 screen->chip_family = CHIP_FAMILY_RS690;
601 break;
602 case PCI_CHIP_RS740_796C:
603 case PCI_CHIP_RS740_796D:
604 case PCI_CHIP_RS740_796E:
605 case PCI_CHIP_RS740_796F:
606 screen->chip_family = CHIP_FAMILY_RS740;
607 break;
608
609 case PCI_CHIP_R520_7100:
610 case PCI_CHIP_R520_7101:
611 case PCI_CHIP_R520_7102:
612 case PCI_CHIP_R520_7103:
613 case PCI_CHIP_R520_7104:
614 case PCI_CHIP_R520_7105:
615 case PCI_CHIP_R520_7106:
616 case PCI_CHIP_R520_7108:
617 case PCI_CHIP_R520_7109:
618 case PCI_CHIP_R520_710A:
619 case PCI_CHIP_R520_710B:
620 case PCI_CHIP_R520_710C:
621 case PCI_CHIP_R520_710E:
622 case PCI_CHIP_R520_710F:
623 screen->chip_family = CHIP_FAMILY_R520;
624 screen->chip_flags = RADEON_CHIPSET_TCL;
625 break;
626
627 case PCI_CHIP_RV515_7140:
628 case PCI_CHIP_RV515_7141:
629 case PCI_CHIP_RV515_7142:
630 case PCI_CHIP_RV515_7143:
631 case PCI_CHIP_RV515_7144:
632 case PCI_CHIP_RV515_7145:
633 case PCI_CHIP_RV515_7146:
634 case PCI_CHIP_RV515_7147:
635 case PCI_CHIP_RV515_7149:
636 case PCI_CHIP_RV515_714A:
637 case PCI_CHIP_RV515_714B:
638 case PCI_CHIP_RV515_714C:
639 case PCI_CHIP_RV515_714D:
640 case PCI_CHIP_RV515_714E:
641 case PCI_CHIP_RV515_714F:
642 case PCI_CHIP_RV515_7151:
643 case PCI_CHIP_RV515_7152:
644 case PCI_CHIP_RV515_7153:
645 case PCI_CHIP_RV515_715E:
646 case PCI_CHIP_RV515_715F:
647 case PCI_CHIP_RV515_7180:
648 case PCI_CHIP_RV515_7181:
649 case PCI_CHIP_RV515_7183:
650 case PCI_CHIP_RV515_7186:
651 case PCI_CHIP_RV515_7187:
652 case PCI_CHIP_RV515_7188:
653 case PCI_CHIP_RV515_718A:
654 case PCI_CHIP_RV515_718B:
655 case PCI_CHIP_RV515_718C:
656 case PCI_CHIP_RV515_718D:
657 case PCI_CHIP_RV515_718F:
658 case PCI_CHIP_RV515_7193:
659 case PCI_CHIP_RV515_7196:
660 case PCI_CHIP_RV515_719B:
661 case PCI_CHIP_RV515_719F:
662 case PCI_CHIP_RV515_7200:
663 case PCI_CHIP_RV515_7210:
664 case PCI_CHIP_RV515_7211:
665 screen->chip_family = CHIP_FAMILY_RV515;
666 screen->chip_flags = RADEON_CHIPSET_TCL;
667 break;
668
669 case PCI_CHIP_RV530_71C0:
670 case PCI_CHIP_RV530_71C1:
671 case PCI_CHIP_RV530_71C2:
672 case PCI_CHIP_RV530_71C3:
673 case PCI_CHIP_RV530_71C4:
674 case PCI_CHIP_RV530_71C5:
675 case PCI_CHIP_RV530_71C6:
676 case PCI_CHIP_RV530_71C7:
677 case PCI_CHIP_RV530_71CD:
678 case PCI_CHIP_RV530_71CE:
679 case PCI_CHIP_RV530_71D2:
680 case PCI_CHIP_RV530_71D4:
681 case PCI_CHIP_RV530_71D5:
682 case PCI_CHIP_RV530_71D6:
683 case PCI_CHIP_RV530_71DA:
684 case PCI_CHIP_RV530_71DE:
685 screen->chip_family = CHIP_FAMILY_RV530;
686 screen->chip_flags = RADEON_CHIPSET_TCL;
687 break;
688
689 case PCI_CHIP_R580_7240:
690 case PCI_CHIP_R580_7243:
691 case PCI_CHIP_R580_7244:
692 case PCI_CHIP_R580_7245:
693 case PCI_CHIP_R580_7246:
694 case PCI_CHIP_R580_7247:
695 case PCI_CHIP_R580_7248:
696 case PCI_CHIP_R580_7249:
697 case PCI_CHIP_R580_724A:
698 case PCI_CHIP_R580_724B:
699 case PCI_CHIP_R580_724C:
700 case PCI_CHIP_R580_724D:
701 case PCI_CHIP_R580_724E:
702 case PCI_CHIP_R580_724F:
703 case PCI_CHIP_R580_7284:
704 screen->chip_family = CHIP_FAMILY_R580;
705 screen->chip_flags = RADEON_CHIPSET_TCL;
706 break;
707
708 case PCI_CHIP_RV570_7280:
709 case PCI_CHIP_RV560_7281:
710 case PCI_CHIP_RV560_7283:
711 case PCI_CHIP_RV560_7287:
712 case PCI_CHIP_RV570_7288:
713 case PCI_CHIP_RV570_7289:
714 case PCI_CHIP_RV570_728B:
715 case PCI_CHIP_RV570_728C:
716 case PCI_CHIP_RV560_7290:
717 case PCI_CHIP_RV560_7291:
718 case PCI_CHIP_RV560_7293:
719 case PCI_CHIP_RV560_7297:
720 screen->chip_family = CHIP_FAMILY_RV560;
721 screen->chip_flags = RADEON_CHIPSET_TCL;
722 break;
723
724 case PCI_CHIP_R600_9400:
725 case PCI_CHIP_R600_9401:
726 case PCI_CHIP_R600_9402:
727 case PCI_CHIP_R600_9403:
728 case PCI_CHIP_R600_9405:
729 case PCI_CHIP_R600_940A:
730 case PCI_CHIP_R600_940B:
731 case PCI_CHIP_R600_940F:
732 screen->chip_family = CHIP_FAMILY_R600;
733 screen->chip_flags = RADEON_CHIPSET_TCL;
734 break;
735
736 case PCI_CHIP_RV610_94C0:
737 case PCI_CHIP_RV610_94C1:
738 case PCI_CHIP_RV610_94C3:
739 case PCI_CHIP_RV610_94C4:
740 case PCI_CHIP_RV610_94C5:
741 case PCI_CHIP_RV610_94C6:
742 case PCI_CHIP_RV610_94C7:
743 case PCI_CHIP_RV610_94C8:
744 case PCI_CHIP_RV610_94C9:
745 case PCI_CHIP_RV610_94CB:
746 case PCI_CHIP_RV610_94CC:
747 case PCI_CHIP_RV610_94CD:
748 screen->chip_family = CHIP_FAMILY_RV610;
749 screen->chip_flags = RADEON_CHIPSET_TCL;
750 break;
751
752 case PCI_CHIP_RV630_9580:
753 case PCI_CHIP_RV630_9581:
754 case PCI_CHIP_RV630_9583:
755 case PCI_CHIP_RV630_9586:
756 case PCI_CHIP_RV630_9587:
757 case PCI_CHIP_RV630_9588:
758 case PCI_CHIP_RV630_9589:
759 case PCI_CHIP_RV630_958A:
760 case PCI_CHIP_RV630_958B:
761 case PCI_CHIP_RV630_958C:
762 case PCI_CHIP_RV630_958D:
763 case PCI_CHIP_RV630_958E:
764 case PCI_CHIP_RV630_958F:
765 screen->chip_family = CHIP_FAMILY_RV630;
766 screen->chip_flags = RADEON_CHIPSET_TCL;
767 break;
768
769 case PCI_CHIP_RV670_9500:
770 case PCI_CHIP_RV670_9501:
771 case PCI_CHIP_RV670_9504:
772 case PCI_CHIP_RV670_9505:
773 case PCI_CHIP_RV670_9506:
774 case PCI_CHIP_RV670_9507:
775 case PCI_CHIP_RV670_9508:
776 case PCI_CHIP_RV670_9509:
777 case PCI_CHIP_RV670_950F:
778 case PCI_CHIP_RV670_9511:
779 case PCI_CHIP_RV670_9515:
780 case PCI_CHIP_RV670_9517:
781 case PCI_CHIP_RV670_9519:
782 screen->chip_family = CHIP_FAMILY_RV670;
783 screen->chip_flags = RADEON_CHIPSET_TCL;
784 break;
785
786 case PCI_CHIP_RV620_95C0:
787 case PCI_CHIP_RV620_95C2:
788 case PCI_CHIP_RV620_95C4:
789 case PCI_CHIP_RV620_95C5:
790 case PCI_CHIP_RV620_95C6:
791 case PCI_CHIP_RV620_95C7:
792 case PCI_CHIP_RV620_95C9:
793 case PCI_CHIP_RV620_95CC:
794 case PCI_CHIP_RV620_95CD:
795 case PCI_CHIP_RV620_95CE:
796 case PCI_CHIP_RV620_95CF:
797 screen->chip_family = CHIP_FAMILY_RV620;
798 screen->chip_flags = RADEON_CHIPSET_TCL;
799 break;
800
801 case PCI_CHIP_RV635_9590:
802 case PCI_CHIP_RV635_9591:
803 case PCI_CHIP_RV635_9593:
804 case PCI_CHIP_RV635_9595:
805 case PCI_CHIP_RV635_9596:
806 case PCI_CHIP_RV635_9597:
807 case PCI_CHIP_RV635_9598:
808 case PCI_CHIP_RV635_9599:
809 case PCI_CHIP_RV635_959B:
810 screen->chip_family = CHIP_FAMILY_RV635;
811 screen->chip_flags = RADEON_CHIPSET_TCL;
812 break;
813
814 case PCI_CHIP_RS780_9610:
815 case PCI_CHIP_RS780_9611:
816 case PCI_CHIP_RS780_9612:
817 case PCI_CHIP_RS780_9613:
818 case PCI_CHIP_RS780_9614:
819 case PCI_CHIP_RS780_9615:
820 case PCI_CHIP_RS780_9616:
821 screen->chip_family = CHIP_FAMILY_RS780;
822 screen->chip_flags = RADEON_CHIPSET_TCL;
823 break;
824 case PCI_CHIP_RS880_9710:
825 case PCI_CHIP_RS880_9711:
826 case PCI_CHIP_RS880_9712:
827 case PCI_CHIP_RS880_9713:
828 case PCI_CHIP_RS880_9714:
829 case PCI_CHIP_RS880_9715:
830 screen->chip_family = CHIP_FAMILY_RS880;
831 screen->chip_flags = RADEON_CHIPSET_TCL;
832 break;
833
834 case PCI_CHIP_RV770_9440:
835 case PCI_CHIP_RV770_9441:
836 case PCI_CHIP_RV770_9442:
837 case PCI_CHIP_RV770_9443:
838 case PCI_CHIP_RV770_9444:
839 case PCI_CHIP_RV770_9446:
840 case PCI_CHIP_RV770_944A:
841 case PCI_CHIP_RV770_944B:
842 case PCI_CHIP_RV770_944C:
843 case PCI_CHIP_RV770_944E:
844 case PCI_CHIP_RV770_9450:
845 case PCI_CHIP_RV770_9452:
846 case PCI_CHIP_RV770_9456:
847 case PCI_CHIP_RV770_945A:
848 case PCI_CHIP_RV770_945B:
849 case PCI_CHIP_RV770_945E:
850 case PCI_CHIP_RV790_9460:
851 case PCI_CHIP_RV790_9462:
852 case PCI_CHIP_RV770_946A:
853 case PCI_CHIP_RV770_946B:
854 case PCI_CHIP_RV770_947A:
855 case PCI_CHIP_RV770_947B:
856 screen->chip_family = CHIP_FAMILY_RV770;
857 screen->chip_flags = RADEON_CHIPSET_TCL;
858 break;
859
860 case PCI_CHIP_RV730_9480:
861 case PCI_CHIP_RV730_9487:
862 case PCI_CHIP_RV730_9488:
863 case PCI_CHIP_RV730_9489:
864 case PCI_CHIP_RV730_948A:
865 case PCI_CHIP_RV730_948F:
866 case PCI_CHIP_RV730_9490:
867 case PCI_CHIP_RV730_9491:
868 case PCI_CHIP_RV730_9495:
869 case PCI_CHIP_RV730_9498:
870 case PCI_CHIP_RV730_949C:
871 case PCI_CHIP_RV730_949E:
872 case PCI_CHIP_RV730_949F:
873 screen->chip_family = CHIP_FAMILY_RV730;
874 screen->chip_flags = RADEON_CHIPSET_TCL;
875 break;
876
877 case PCI_CHIP_RV710_9540:
878 case PCI_CHIP_RV710_9541:
879 case PCI_CHIP_RV710_9542:
880 case PCI_CHIP_RV710_954E:
881 case PCI_CHIP_RV710_954F:
882 case PCI_CHIP_RV710_9552:
883 case PCI_CHIP_RV710_9553:
884 case PCI_CHIP_RV710_9555:
885 case PCI_CHIP_RV710_9557:
886 case PCI_CHIP_RV710_955F:
887 screen->chip_family = CHIP_FAMILY_RV710;
888 screen->chip_flags = RADEON_CHIPSET_TCL;
889 break;
890
891 case PCI_CHIP_RV740_94A0:
892 case PCI_CHIP_RV740_94A1:
893 case PCI_CHIP_RV740_94A3:
894 case PCI_CHIP_RV740_94B1:
895 case PCI_CHIP_RV740_94B3:
896 case PCI_CHIP_RV740_94B4:
897 case PCI_CHIP_RV740_94B5:
898 case PCI_CHIP_RV740_94B9:
899 screen->chip_family = CHIP_FAMILY_RV740;
900 screen->chip_flags = RADEON_CHIPSET_TCL;
901 break;
902
903 default:
904 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
905 device_id);
906 return -1;
907 }
908
909 return 0;
910 }
911
912
913 /* Create the device specific screen private data struct.
914 */
915 static radeonScreenPtr
916 radeonCreateScreen( __DRIscreen *sPriv )
917 {
918 radeonScreenPtr screen;
919 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
920 unsigned char *RADEONMMIO = NULL;
921 int i;
922 int ret;
923 uint32_t temp = 0;
924
925 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
926 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
927 return GL_FALSE;
928 }
929
930 /* Allocate the private area */
931 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
932 if ( !screen ) {
933 __driUtilMessage("%s: Could not allocate memory for screen structure",
934 __FUNCTION__);
935 return NULL;
936 }
937
938 radeon_init_debug();
939
940 /* parse information in __driConfigOptions */
941 driParseOptionInfo (&screen->optionCache,
942 __driConfigOptions, __driNConfigOptions);
943
944 /* This is first since which regions we map depends on whether or
945 * not we are using a PCI card.
946 */
947 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
948 {
949 int ret;
950
951 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
952 &screen->gart_buffer_offset);
953
954 if (ret) {
955 FREE( screen );
956 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
957 return NULL;
958 }
959
960 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
961 &screen->gart_base);
962 if (ret) {
963 FREE( screen );
964 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
965 return NULL;
966 }
967
968 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
969 &screen->irq);
970 if (ret) {
971 FREE( screen );
972 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
973 return NULL;
974 }
975 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
976 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
977 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
978 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
979 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
980 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
981 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
982 screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30);
983 }
984
985 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
986 if (ret == -1)
987 return NULL;
988
989 screen->mmio.handle = dri_priv->registerHandle;
990 screen->mmio.size = dri_priv->registerSize;
991 if ( drmMap( sPriv->fd,
992 screen->mmio.handle,
993 screen->mmio.size,
994 &screen->mmio.map ) ) {
995 FREE( screen );
996 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
997 return NULL;
998 }
999
1000 RADEONMMIO = screen->mmio.map;
1001
1002 screen->status.handle = dri_priv->statusHandle;
1003 screen->status.size = dri_priv->statusSize;
1004 if ( drmMap( sPriv->fd,
1005 screen->status.handle,
1006 screen->status.size,
1007 &screen->status.map ) ) {
1008 drmUnmap( screen->mmio.map, screen->mmio.size );
1009 FREE( screen );
1010 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
1011 return NULL;
1012 }
1013 if (screen->chip_family < CHIP_FAMILY_R600)
1014 screen->scratch = (__volatile__ uint32_t *)
1015 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
1016 else
1017 screen->scratch = (__volatile__ uint32_t *)
1018 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET);
1019
1020 screen->buffers = drmMapBufs( sPriv->fd );
1021 if ( !screen->buffers ) {
1022 drmUnmap( screen->status.map, screen->status.size );
1023 drmUnmap( screen->mmio.map, screen->mmio.size );
1024 FREE( screen );
1025 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
1026 return NULL;
1027 }
1028
1029 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
1030 screen->gartTextures.handle = dri_priv->gartTexHandle;
1031 screen->gartTextures.size = dri_priv->gartTexMapSize;
1032 if ( drmMap( sPriv->fd,
1033 screen->gartTextures.handle,
1034 screen->gartTextures.size,
1035 (drmAddressPtr)&screen->gartTextures.map ) ) {
1036 drmUnmapBufs( screen->buffers );
1037 drmUnmap( screen->status.map, screen->status.size );
1038 drmUnmap( screen->mmio.map, screen->mmio.size );
1039 FREE( screen );
1040 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
1041 return NULL;
1042 }
1043
1044 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
1045 }
1046
1047 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
1048 sPriv->ddx_version.minor < 2) {
1049 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1050 return NULL;
1051 }
1052
1053 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
1054 fprintf(stderr, "R500 support requires a newer drm.\n");
1055 return NULL;
1056 }
1057
1058 if (getenv("R300_NO_TCL"))
1059 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1060
1061 if (screen->chip_family <= CHIP_FAMILY_RS200)
1062 screen->chip_flags |= RADEON_CLASS_R100;
1063 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1064 screen->chip_flags |= RADEON_CLASS_R200;
1065 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1066 screen->chip_flags |= RADEON_CLASS_R300;
1067 else
1068 screen->chip_flags |= RADEON_CLASS_R600;
1069
1070 screen->cpp = dri_priv->bpp / 8;
1071 screen->AGPMode = dri_priv->AGPMode;
1072
1073 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
1074
1075 /* +r6/r7 */
1076 if(screen->chip_family >= CHIP_FAMILY_R600)
1077 {
1078 if (ret)
1079 {
1080 FREE( screen );
1081 fprintf(stderr, "Unable to get fb location need newer drm\n");
1082 return NULL;
1083 }
1084 else
1085 {
1086 screen->fbLocation = (temp & 0xffff) << 24;
1087 }
1088 }
1089 else
1090 {
1091 if (ret)
1092 {
1093 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
1094 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
1095 else
1096 {
1097 FREE( screen );
1098 fprintf(stderr, "Unable to get fb location need newer drm\n");
1099 return NULL;
1100 }
1101 }
1102 else
1103 {
1104 screen->fbLocation = (temp & 0xffff) << 16;
1105 }
1106 }
1107
1108 if (IS_R300_CLASS(screen)) {
1109 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1110 if (ret) {
1111 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1112 switch (screen->chip_family) {
1113 case CHIP_FAMILY_R300:
1114 case CHIP_FAMILY_R350:
1115 screen->num_gb_pipes = 2;
1116 break;
1117 case CHIP_FAMILY_R420:
1118 case CHIP_FAMILY_R520:
1119 case CHIP_FAMILY_R580:
1120 case CHIP_FAMILY_RV560:
1121 case CHIP_FAMILY_RV570:
1122 screen->num_gb_pipes = 4;
1123 break;
1124 case CHIP_FAMILY_RV350:
1125 case CHIP_FAMILY_RV515:
1126 case CHIP_FAMILY_RV530:
1127 case CHIP_FAMILY_RV410:
1128 default:
1129 screen->num_gb_pipes = 1;
1130 break;
1131 }
1132 } else {
1133 screen->num_gb_pipes = temp;
1134 }
1135
1136 /* pipe overrides */
1137 switch (dri_priv->deviceID) {
1138 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1139 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1140 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1141 screen->num_gb_pipes = 1;
1142 break;
1143 default:
1144 break;
1145 }
1146
1147 if ( sPriv->drm_version.minor >= 31 ) {
1148 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1149 if (ret)
1150 screen->num_z_pipes = 2;
1151 else
1152 screen->num_z_pipes = temp;
1153 } else
1154 screen->num_z_pipes = 2;
1155 }
1156
1157 if ( sPriv->drm_version.minor >= 10 ) {
1158 drm_radeon_setparam_t sp;
1159
1160 sp.param = RADEON_SETPARAM_FB_LOCATION;
1161 sp.value = screen->fbLocation;
1162
1163 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
1164 &sp, sizeof( sp ) );
1165 }
1166
1167 screen->frontOffset = dri_priv->frontOffset;
1168 screen->frontPitch = dri_priv->frontPitch;
1169 screen->backOffset = dri_priv->backOffset;
1170 screen->backPitch = dri_priv->backPitch;
1171 screen->depthOffset = dri_priv->depthOffset;
1172 screen->depthPitch = dri_priv->depthPitch;
1173
1174 /* Check if ddx has set up a surface reg to cover depth buffer */
1175 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
1176 /* these chips don't use tiled z without hyperz. So always pretend
1177 we have set up a surface which will cause linear reads/writes */
1178 (IS_R100_CLASS(screen) &&
1179 !(screen->chip_flags & RADEON_CHIPSET_TCL));
1180
1181 if ( dri_priv->textureSize == 0 ) {
1182 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
1183 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
1184 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1185 dri_priv->log2GARTTexGran;
1186 } else {
1187 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
1188 + screen->fbLocation;
1189 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
1190 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1191 dri_priv->log2TexGran;
1192 }
1193
1194 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
1195 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1196 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
1197 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
1198 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
1199 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
1200 } else {
1201 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
1202 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
1203 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
1204 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
1205 dri_priv->log2GARTTexGran;
1206 }
1207
1208 i = 0;
1209 screen->extensions[i++] = &driCopySubBufferExtension.base;
1210 screen->extensions[i++] = &driFrameTrackingExtension.base;
1211 screen->extensions[i++] = &driReadDrawableExtension;
1212
1213 if ( screen->irq != 0 ) {
1214 screen->extensions[i++] = &driSwapControlExtension.base;
1215 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1216 }
1217
1218 #if defined(RADEON_R100)
1219 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1220 #endif
1221
1222 #if defined(RADEON_R200)
1223 if (IS_R200_CLASS(screen))
1224 screen->extensions[i++] = &r200AllocateExtension.base;
1225
1226 screen->extensions[i++] = &r200texOffsetExtension.base;
1227 #endif
1228
1229 #if defined(RADEON_R300)
1230 screen->extensions[i++] = &r300texOffsetExtension.base;
1231 #endif
1232
1233 #if defined(RADEON_R600)
1234 screen->extensions[i++] = &r600texOffsetExtension.base;
1235 #endif
1236
1237 screen->extensions[i++] = NULL;
1238 sPriv->extensions = screen->extensions;
1239
1240 screen->driScreen = sPriv;
1241 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1242 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1243 screen->sarea_priv_offset);
1244
1245 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1246 if (screen->bom == NULL) {
1247 free(screen);
1248 return NULL;
1249 }
1250
1251 return screen;
1252 }
1253
1254 static radeonScreenPtr
1255 radeonCreateScreen2(__DRIscreen *sPriv)
1256 {
1257 radeonScreenPtr screen;
1258 int i;
1259 int ret;
1260 uint32_t device_id = 0;
1261 uint32_t temp = 0;
1262
1263 /* Allocate the private area */
1264 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1265 if ( !screen ) {
1266 __driUtilMessage("%s: Could not allocate memory for screen structure",
1267 __FUNCTION__);
1268 fprintf(stderr, "leaving here\n");
1269 return NULL;
1270 }
1271
1272 radeon_init_debug();
1273
1274 /* parse information in __driConfigOptions */
1275 driParseOptionInfo (&screen->optionCache,
1276 __driConfigOptions, __driNConfigOptions);
1277
1278 screen->kernel_mm = 1;
1279 screen->chip_flags = 0;
1280
1281 /* if we have kms we can support all of these */
1282 screen->drmSupportsCubeMapsR200 = 1;
1283 screen->drmSupportsBlendColor = 1;
1284 screen->drmSupportsTriPerf = 1;
1285 screen->drmSupportsFragShader = 1;
1286 screen->drmSupportsPointSprites = 1;
1287 screen->drmSupportsCubeMapsR100 = 1;
1288 screen->drmSupportsVertexProgram = 1;
1289 screen->drmSupportsOcclusionQueries = 1;
1290 screen->irq = 1;
1291
1292 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1293 if (ret) {
1294 FREE( screen );
1295 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1296 return NULL;
1297 }
1298
1299 ret = radeon_set_screen_flags(screen, device_id);
1300 if (ret == -1)
1301 return NULL;
1302
1303 if (getenv("R300_NO_TCL"))
1304 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1305
1306 if (screen->chip_family <= CHIP_FAMILY_RS200)
1307 screen->chip_flags |= RADEON_CLASS_R100;
1308 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1309 screen->chip_flags |= RADEON_CLASS_R200;
1310 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1311 screen->chip_flags |= RADEON_CLASS_R300;
1312 else
1313 screen->chip_flags |= RADEON_CLASS_R600;
1314
1315 if (IS_R300_CLASS(screen)) {
1316 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1317 if (ret) {
1318 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1319 switch (screen->chip_family) {
1320 case CHIP_FAMILY_R300:
1321 case CHIP_FAMILY_R350:
1322 screen->num_gb_pipes = 2;
1323 break;
1324 case CHIP_FAMILY_R420:
1325 case CHIP_FAMILY_R520:
1326 case CHIP_FAMILY_R580:
1327 case CHIP_FAMILY_RV560:
1328 case CHIP_FAMILY_RV570:
1329 screen->num_gb_pipes = 4;
1330 break;
1331 case CHIP_FAMILY_RV350:
1332 case CHIP_FAMILY_RV515:
1333 case CHIP_FAMILY_RV530:
1334 case CHIP_FAMILY_RV410:
1335 default:
1336 screen->num_gb_pipes = 1;
1337 break;
1338 }
1339 } else {
1340 screen->num_gb_pipes = temp;
1341 }
1342
1343 /* pipe overrides */
1344 switch (device_id) {
1345 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1346 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1347 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1348 screen->num_gb_pipes = 1;
1349 break;
1350 default:
1351 break;
1352 }
1353
1354 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1355 if (ret)
1356 screen->num_z_pipes = 2;
1357 else
1358 screen->num_z_pipes = temp;
1359
1360 }
1361
1362 i = 0;
1363 screen->extensions[i++] = &driCopySubBufferExtension.base;
1364 screen->extensions[i++] = &driFrameTrackingExtension.base;
1365 screen->extensions[i++] = &driReadDrawableExtension;
1366
1367 if ( screen->irq != 0 ) {
1368 screen->extensions[i++] = &driSwapControlExtension.base;
1369 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1370 }
1371
1372 #if defined(RADEON_R100)
1373 screen->extensions[i++] = &radeonTexBufferExtension.base;
1374 #endif
1375
1376 #if defined(RADEON_R200)
1377 if (IS_R200_CLASS(screen))
1378 screen->extensions[i++] = &r200AllocateExtension.base;
1379
1380 screen->extensions[i++] = &r200TexBufferExtension.base;
1381 #endif
1382
1383 #if defined(RADEON_R300)
1384 screen->extensions[i++] = &r300TexBufferExtension.base;
1385 #endif
1386
1387 #if defined(RADEON_R600)
1388 screen->extensions[i++] = &r600TexBufferExtension.base;
1389 #endif
1390
1391 screen->extensions[i++] = NULL;
1392 sPriv->extensions = screen->extensions;
1393
1394 screen->driScreen = sPriv;
1395 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1396 if (screen->bom == NULL) {
1397 free(screen);
1398 return NULL;
1399 }
1400 return screen;
1401 }
1402
1403 /* Destroy the device specific screen private data struct.
1404 */
1405 static void
1406 radeonDestroyScreen( __DRIscreen *sPriv )
1407 {
1408 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1409
1410 if (!screen)
1411 return;
1412
1413 if (screen->kernel_mm) {
1414 #ifdef RADEON_BO_TRACK
1415 radeon_tracker_print(&screen->bom->tracker, stderr);
1416 #endif
1417 radeon_bo_manager_gem_dtor(screen->bom);
1418 } else {
1419 radeon_bo_manager_legacy_dtor(screen->bom);
1420
1421 if ( screen->gartTextures.map ) {
1422 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1423 }
1424 drmUnmapBufs( screen->buffers );
1425 drmUnmap( screen->status.map, screen->status.size );
1426 drmUnmap( screen->mmio.map, screen->mmio.size );
1427 }
1428
1429 /* free all option information */
1430 driDestroyOptionInfo (&screen->optionCache);
1431
1432 FREE( screen );
1433 sPriv->private = NULL;
1434 }
1435
1436
1437 /* Initialize the driver specific screen private data.
1438 */
1439 static GLboolean
1440 radeonInitDriver( __DRIscreen *sPriv )
1441 {
1442 if (sPriv->dri2.enabled) {
1443 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1444 } else {
1445 sPriv->private = (void *) radeonCreateScreen( sPriv );
1446 }
1447 if ( !sPriv->private ) {
1448 radeonDestroyScreen( sPriv );
1449 return GL_FALSE;
1450 }
1451
1452 return GL_TRUE;
1453 }
1454
1455
1456
1457 /**
1458 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1459 *
1460 * \todo This function (and its interface) will need to be updated to support
1461 * pbuffers.
1462 */
1463 static GLboolean
1464 radeonCreateBuffer( __DRIscreen *driScrnPriv,
1465 __DRIdrawable *driDrawPriv,
1466 const __GLcontextModes *mesaVis,
1467 GLboolean isPixmap )
1468 {
1469 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1470
1471 const GLboolean swDepth = GL_FALSE;
1472 const GLboolean swAlpha = GL_FALSE;
1473 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1474 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1475 mesaVis->depthBits != 24;
1476 gl_format rgbFormat;
1477 struct radeon_framebuffer *rfb;
1478
1479 if (isPixmap)
1480 return GL_FALSE; /* not implemented */
1481
1482 rfb = CALLOC_STRUCT(radeon_framebuffer);
1483 if (!rfb)
1484 return GL_FALSE;
1485
1486 _mesa_initialize_window_framebuffer(&rfb->base, mesaVis);
1487
1488 if (mesaVis->redBits == 5)
1489 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV;
1490 else if (mesaVis->alphaBits == 0)
1491 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV;
1492 else
1493 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV;
1494
1495 /* front color renderbuffer */
1496 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1497 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1498 rfb->color_rb[0]->has_surface = 1;
1499
1500 /* back color renderbuffer */
1501 if (mesaVis->doubleBufferMode) {
1502 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1503 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1504 rfb->color_rb[1]->has_surface = 1;
1505 }
1506
1507 if (mesaVis->depthBits == 24) {
1508 if (mesaVis->stencilBits == 8) {
1509 struct radeon_renderbuffer *depthStencilRb =
1510 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv);
1511 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1512 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1513 depthStencilRb->has_surface = screen->depthHasSurface;
1514 } else {
1515 /* depth renderbuffer */
1516 struct radeon_renderbuffer *depth =
1517 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv);
1518 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1519 depth->has_surface = screen->depthHasSurface;
1520 }
1521 } else if (mesaVis->depthBits == 16) {
1522 /* just 16-bit depth buffer, no hw stencil */
1523 struct radeon_renderbuffer *depth =
1524 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv);
1525 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1526 depth->has_surface = screen->depthHasSurface;
1527 }
1528
1529 _mesa_add_soft_renderbuffers(&rfb->base,
1530 GL_FALSE, /* color */
1531 swDepth,
1532 swStencil,
1533 swAccum,
1534 swAlpha,
1535 GL_FALSE /* aux */);
1536 driDrawPriv->driverPrivate = (void *) rfb;
1537
1538 return (driDrawPriv->driverPrivate != NULL);
1539 }
1540
1541
1542 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1543 {
1544 struct radeon_renderbuffer *rb;
1545
1546 rb = rfb->color_rb[0];
1547 if (rb && rb->bo) {
1548 radeon_bo_unref(rb->bo);
1549 rb->bo = NULL;
1550 }
1551 rb = rfb->color_rb[1];
1552 if (rb && rb->bo) {
1553 radeon_bo_unref(rb->bo);
1554 rb->bo = NULL;
1555 }
1556 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1557 if (rb && rb->bo) {
1558 radeon_bo_unref(rb->bo);
1559 rb->bo = NULL;
1560 }
1561 }
1562
1563 void
1564 radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
1565 {
1566 struct radeon_framebuffer *rfb;
1567 if (!driDrawPriv)
1568 return;
1569
1570 rfb = (void*)driDrawPriv->driverPrivate;
1571 if (!rfb)
1572 return;
1573 radeon_cleanup_renderbuffers(rfb);
1574 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1575 }
1576
1577
1578 /**
1579 * This is the driver specific part of the createNewScreen entry point.
1580 *
1581 * \todo maybe fold this into intelInitDriver
1582 *
1583 * \return the __GLcontextModes supported by this driver
1584 */
1585 static const __DRIconfig **
1586 radeonInitScreen(__DRIscreen *psp)
1587 {
1588 #if defined(RADEON_R100)
1589 static const char *driver_name = "Radeon";
1590 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1591 static const __DRIversion dri_expected = { 4, 0, 0 };
1592 static const __DRIversion drm_expected = { 1, 6, 0 };
1593 #elif defined(RADEON_R200)
1594 static const char *driver_name = "R200";
1595 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1596 static const __DRIversion dri_expected = { 4, 0, 0 };
1597 static const __DRIversion drm_expected = { 1, 6, 0 };
1598 #elif defined(RADEON_R300)
1599 static const char *driver_name = "R300";
1600 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1601 static const __DRIversion dri_expected = { 4, 0, 0 };
1602 static const __DRIversion drm_expected = { 1, 24, 0 };
1603 #elif defined(RADEON_R600)
1604 static const char *driver_name = "R600";
1605 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1606 static const __DRIversion dri_expected = { 4, 0, 0 };
1607 static const __DRIversion drm_expected = { 1, 24, 0 };
1608 #endif
1609 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1610
1611 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1612 &psp->dri_version, & dri_expected,
1613 &psp->ddx_version, & ddx_expected,
1614 &psp->drm_version, & drm_expected ) ) {
1615 return NULL;
1616 }
1617
1618 if (!radeonInitDriver(psp))
1619 return NULL;
1620
1621 /* for now fill in all modes */
1622 return radeonFillInModes( psp,
1623 dri_priv->bpp,
1624 (dri_priv->bpp == 16) ? 16 : 24,
1625 (dri_priv->bpp == 16) ? 0 : 8, 1);
1626 }
1627 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1628
1629 /**
1630 * This is the driver specific part of the createNewScreen entry point.
1631 * Called when using DRI2.
1632 *
1633 * \return the __GLcontextModes supported by this driver
1634 */
1635 static const
1636 __DRIconfig **radeonInitScreen2(__DRIscreen *psp)
1637 {
1638 GLenum fb_format[3];
1639 GLenum fb_type[3];
1640 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1641 * support pageflipping at all.
1642 */
1643 static const GLenum back_buffer_modes[] = {
1644 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1645 };
1646 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1647 int color;
1648 __DRIconfig **configs = NULL;
1649
1650 if (!radeonInitDriver(psp)) {
1651 return NULL;
1652 }
1653 depth_bits[0] = 0;
1654 stencil_bits[0] = 0;
1655 depth_bits[1] = 16;
1656 stencil_bits[1] = 0;
1657 depth_bits[2] = 24;
1658 stencil_bits[2] = 0;
1659 depth_bits[3] = 24;
1660 stencil_bits[3] = 8;
1661
1662 msaa_samples_array[0] = 0;
1663
1664 fb_format[0] = GL_RGB;
1665 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1666
1667 fb_format[1] = GL_BGR;
1668 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1669
1670 fb_format[2] = GL_BGRA;
1671 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1672
1673 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1674 __DRIconfig **new_configs;
1675
1676 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1677 depth_bits,
1678 stencil_bits,
1679 ARRAY_SIZE(depth_bits),
1680 back_buffer_modes,
1681 ARRAY_SIZE(back_buffer_modes),
1682 msaa_samples_array,
1683 ARRAY_SIZE(msaa_samples_array),
1684 GL_TRUE);
1685 if (configs == NULL)
1686 configs = new_configs;
1687 else
1688 configs = driConcatConfigs(configs, new_configs);
1689 }
1690
1691 if (configs == NULL) {
1692 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1693 __LINE__);
1694 return NULL;
1695 }
1696
1697 return (const __DRIconfig **)configs;
1698 }
1699
1700 /**
1701 * Get information about previous buffer swaps.
1702 */
1703 static int
1704 getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo )
1705 {
1706 struct radeon_framebuffer *rfb;
1707
1708 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1709 || (dPriv->driContextPriv->driverPrivate == NULL)
1710 || (sInfo == NULL) ) {
1711 return -1;
1712 }
1713
1714 rfb = dPriv->driverPrivate;
1715 sInfo->swap_count = rfb->swap_count;
1716 sInfo->swap_ust = rfb->swap_ust;
1717 sInfo->swap_missed_count = rfb->swap_missed_count;
1718
1719 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1720 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
1721 : 0.0;
1722
1723 return 0;
1724 }
1725
1726 const struct __DriverAPIRec driDriverAPI = {
1727 .InitScreen = radeonInitScreen,
1728 .DestroyScreen = radeonDestroyScreen,
1729 #if defined(RADEON_R200)
1730 .CreateContext = r200CreateContext,
1731 .DestroyContext = r200DestroyContext,
1732 #elif defined(RADEON_R600)
1733 .CreateContext = r600CreateContext,
1734 .DestroyContext = radeonDestroyContext,
1735 #elif defined(RADEON_R300)
1736 .CreateContext = r300CreateContext,
1737 .DestroyContext = radeonDestroyContext,
1738 #else
1739 .CreateContext = r100CreateContext,
1740 .DestroyContext = radeonDestroyContext,
1741 #endif
1742 .CreateBuffer = radeonCreateBuffer,
1743 .DestroyBuffer = radeonDestroyBuffer,
1744 .SwapBuffers = radeonSwapBuffers,
1745 .MakeCurrent = radeonMakeCurrent,
1746 .UnbindContext = radeonUnbindContext,
1747 .GetSwapInfo = getSwapInfo,
1748 .GetDrawableMSC = driDrawableGetMSC32,
1749 .WaitForMSC = driWaitForMSC32,
1750 .WaitForSBC = NULL,
1751 .SwapBuffersMSC = NULL,
1752 .CopySubBuffer = radeonCopySubBuffer,
1753 /* DRI2 */
1754 .InitScreen2 = radeonInitScreen2,
1755 };
1756
1757 /* This is the table of extensions that the loader will dlsym() for. */
1758 PUBLIC const __DRIextension *__driDriverExtensions[] = {
1759 &driCoreExtension.base,
1760 &driLegacyExtension.base,
1761 &driDRI2Extension.base,
1762 NULL
1763 };