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nv50: fix texture relocs
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #if defined(RADEON_R100)
51 #include "radeon_context.h"
52 #include "radeon_tex.h"
53 #elif defined(RADEON_R200)
54 #include "r200_context.h"
55 #include "r200_ioctl.h"
56 #include "r200_tex.h"
57 #elif defined(RADEON_R300)
58 #include "r300_context.h"
59 #include "r300_tex.h"
60 #elif defined(RADEON_R600)
61 #include "r600_context.h"
62 #include "r700_driconf.h" /* +r6/r7 */
63 #include "r600_tex.h" /* +r6/r7 */
64 #endif
65
66 #include "utils.h"
67 #include "vblank.h"
68
69 #include "radeon_bocs_wrapper.h"
70
71 #include "GL/internal/dri_interface.h"
72
73 /* Radeon configuration
74 */
75 #include "xmlpool.h"
76
77 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
78 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
79 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
80 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
81 DRI_CONF_OPT_END
82
83 #if defined(RADEON_R100) /* R100 */
84 PUBLIC const char __driConfigOptions[] =
85 DRI_CONF_BEGIN
86 DRI_CONF_SECTION_PERFORMANCE
87 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
88 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
89 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
90 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
91 DRI_CONF_HYPERZ(false)
92 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
93 DRI_CONF_SECTION_END
94 DRI_CONF_SECTION_QUALITY
95 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
96 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
97 DRI_CONF_NO_NEG_LOD_BIAS(false)
98 DRI_CONF_FORCE_S3TC_ENABLE(false)
99 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
100 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
101 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
102 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
103 DRI_CONF_SECTION_END
104 DRI_CONF_SECTION_DEBUG
105 DRI_CONF_NO_RAST(false)
106 DRI_CONF_SECTION_END
107 DRI_CONF_END;
108 static const GLuint __driNConfigOptions = 15;
109
110 #elif defined(RADEON_R200)
111
112 PUBLIC const char __driConfigOptions[] =
113 DRI_CONF_BEGIN
114 DRI_CONF_SECTION_PERFORMANCE
115 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
116 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
117 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
118 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
119 DRI_CONF_HYPERZ(false)
120 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
121 DRI_CONF_SECTION_END
122 DRI_CONF_SECTION_QUALITY
123 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
124 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
125 DRI_CONF_NO_NEG_LOD_BIAS(false)
126 DRI_CONF_FORCE_S3TC_ENABLE(false)
127 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
128 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
129 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
130 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
131 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
132 DRI_CONF_SECTION_END
133 DRI_CONF_SECTION_DEBUG
134 DRI_CONF_NO_RAST(false)
135 DRI_CONF_SECTION_END
136 DRI_CONF_SECTION_SOFTWARE
137 DRI_CONF_NV_VERTEX_PROGRAM(false)
138 DRI_CONF_SECTION_END
139 DRI_CONF_END;
140 static const GLuint __driNConfigOptions = 17;
141
142 #elif defined(RADEON_R300) || defined(RADEON_R600)
143
144 #define DRI_CONF_FP_OPTIMIZATION_SPEED 0
145 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
146
147 /* TODO: integrate these into xmlpool.h! */
148 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
149 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
150 DRI_CONF_DESC(en,"Number of texture image units") \
151 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
152 DRI_CONF_OPT_END
153
154 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
155 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
156 DRI_CONF_DESC(en,"Number of texture coordinate units") \
157 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
158 DRI_CONF_OPT_END
159
160
161
162 #define DRI_CONF_DISABLE_S3TC(def) \
163 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
164 DRI_CONF_DESC(en,"Disable S3TC compression") \
165 DRI_CONF_OPT_END
166
167 #define DRI_CONF_DISABLE_FALLBACK(def) \
168 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
169 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
170 DRI_CONF_OPT_END
171
172 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
173 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
174 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
175 DRI_CONF_OPT_END
176
177 #define DRI_CONF_FP_OPTIMIZATION(def) \
178 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
179 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
180 DRI_CONF_ENUM(0,"Optimize for Speed") \
181 DRI_CONF_ENUM(1,"Optimize for Quality") \
182 DRI_CONF_DESC_END \
183 DRI_CONF_OPT_END
184
185 PUBLIC const char __driConfigOptions[] =
186 DRI_CONF_BEGIN
187 DRI_CONF_SECTION_PERFORMANCE
188 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
189 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
190 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
191 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
192 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
193 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
194 DRI_CONF_DISABLE_FALLBACK(true)
195 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
196 DRI_CONF_SECTION_END
197 DRI_CONF_SECTION_QUALITY
198 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
199 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
200 DRI_CONF_FORCE_S3TC_ENABLE(false)
201 DRI_CONF_DISABLE_S3TC(false)
202 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
203 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
204 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
205 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
206 DRI_CONF_SECTION_END
207 DRI_CONF_SECTION_DEBUG
208 DRI_CONF_NO_RAST(false)
209 DRI_CONF_SECTION_END
210 DRI_CONF_END;
211 static const GLuint __driNConfigOptions = 17;
212
213 #endif
214
215 static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo );
216
217 static int
218 radeonGetParam(__DRIscreen *sPriv, int param, void *value)
219 {
220 int ret;
221 drm_radeon_getparam_t gp = { 0 };
222 struct drm_radeon_info info = { 0 };
223
224 if (sPriv->drm_version.major >= 2) {
225 info.value = (uint64_t)(uintptr_t)value;
226 switch (param) {
227 case RADEON_PARAM_DEVICE_ID:
228 info.request = RADEON_INFO_DEVICE_ID;
229 break;
230 case RADEON_PARAM_NUM_GB_PIPES:
231 info.request = RADEON_INFO_NUM_GB_PIPES;
232 break;
233 case RADEON_PARAM_NUM_Z_PIPES:
234 info.request = RADEON_INFO_NUM_Z_PIPES;
235 break;
236 default:
237 return -EINVAL;
238 }
239 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
240 } else {
241 gp.param = param;
242 gp.value = value;
243
244 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
245 }
246 return ret;
247 }
248
249 static const __DRIconfig **
250 radeonFillInModes( __DRIscreen *psp,
251 unsigned pixel_bits, unsigned depth_bits,
252 unsigned stencil_bits, GLboolean have_back_buffer )
253 {
254 __DRIconfig **configs;
255 __GLcontextModes *m;
256 unsigned depth_buffer_factor;
257 unsigned back_buffer_factor;
258 int i;
259
260 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
261 * enough to add support. Basically, if a context is created with an
262 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
263 * will never be used.
264 */
265 static const GLenum back_buffer_modes[] = {
266 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
267 };
268
269 uint8_t depth_bits_array[2];
270 uint8_t stencil_bits_array[2];
271 uint8_t msaa_samples_array[1];
272
273 depth_bits_array[0] = depth_bits;
274 depth_bits_array[1] = depth_bits;
275
276 /* Just like with the accumulation buffer, always provide some modes
277 * with a stencil buffer. It will be a sw fallback, but some apps won't
278 * care about that.
279 */
280 stencil_bits_array[0] = stencil_bits;
281 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
282
283 msaa_samples_array[0] = 0;
284
285 depth_buffer_factor = (stencil_bits == 0) ? 2 : 1;
286 back_buffer_factor = (have_back_buffer) ? 2 : 1;
287
288 if (pixel_bits == 16) {
289 __DRIconfig **configs_a8r8g8b8;
290 __DRIconfig **configs_r5g6b5;
291
292 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
293 depth_bits_array, stencil_bits_array,
294 depth_buffer_factor, back_buffer_modes,
295 back_buffer_factor, msaa_samples_array,
296 1, GL_TRUE);
297 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
298 depth_bits_array, stencil_bits_array,
299 1, back_buffer_modes, 1,
300 msaa_samples_array, 1, GL_TRUE);
301 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
302 } else
303 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
304 depth_bits_array, stencil_bits_array,
305 depth_buffer_factor,
306 back_buffer_modes, back_buffer_factor,
307 msaa_samples_array, 1, GL_TRUE);
308
309 if (configs == NULL) {
310 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
311 __func__, __LINE__ );
312 return NULL;
313 }
314
315 /* Mark the visual as slow if there are "fake" stencil bits.
316 */
317 for (i = 0; configs[i]; i++) {
318 m = &configs[i]->modes;
319 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
320 m->visualRating = GLX_SLOW_CONFIG;
321 }
322 }
323
324 return (const __DRIconfig **) configs;
325 }
326
327 #if defined(RADEON_R100)
328 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
329 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
330 radeonSetTexOffset,
331 };
332
333 static const __DRItexBufferExtension radeonTexBufferExtension = {
334 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
335 radeonSetTexBuffer,
336 radeonSetTexBuffer2,
337 };
338 #endif
339
340 #if defined(RADEON_R200)
341 static const __DRIallocateExtension r200AllocateExtension = {
342 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
343 r200AllocateMemoryMESA,
344 r200FreeMemoryMESA,
345 r200GetMemoryOffsetMESA
346 };
347
348 static const __DRItexOffsetExtension r200texOffsetExtension = {
349 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
350 r200SetTexOffset,
351 };
352
353 static const __DRItexBufferExtension r200TexBufferExtension = {
354 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
355 r200SetTexBuffer,
356 r200SetTexBuffer2,
357 };
358 #endif
359
360 #if defined(RADEON_R300)
361 static const __DRItexOffsetExtension r300texOffsetExtension = {
362 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
363 r300SetTexOffset,
364 };
365
366 static const __DRItexBufferExtension r300TexBufferExtension = {
367 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
368 r300SetTexBuffer,
369 r300SetTexBuffer2,
370 };
371 #endif
372
373 #if defined(RADEON_R600)
374 static const __DRItexOffsetExtension r600texOffsetExtension = {
375 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
376 r600SetTexOffset, /* +r6/r7 */
377 };
378
379 static const __DRItexBufferExtension r600TexBufferExtension = {
380 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
381 r600SetTexBuffer, /* +r6/r7 */
382 r600SetTexBuffer2, /* +r6/r7 */
383 };
384 #endif
385
386 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
387 {
388 screen->device_id = device_id;
389 screen->chip_flags = 0;
390 switch ( device_id ) {
391 case PCI_CHIP_RN50_515E:
392 case PCI_CHIP_RN50_5969:
393 return -1;
394
395 case PCI_CHIP_RADEON_LY:
396 case PCI_CHIP_RADEON_LZ:
397 case PCI_CHIP_RADEON_QY:
398 case PCI_CHIP_RADEON_QZ:
399 screen->chip_family = CHIP_FAMILY_RV100;
400 break;
401
402 case PCI_CHIP_RS100_4136:
403 case PCI_CHIP_RS100_4336:
404 screen->chip_family = CHIP_FAMILY_RS100;
405 break;
406
407 case PCI_CHIP_RS200_4137:
408 case PCI_CHIP_RS200_4337:
409 case PCI_CHIP_RS250_4237:
410 case PCI_CHIP_RS250_4437:
411 screen->chip_family = CHIP_FAMILY_RS200;
412 break;
413
414 case PCI_CHIP_RADEON_QD:
415 case PCI_CHIP_RADEON_QE:
416 case PCI_CHIP_RADEON_QF:
417 case PCI_CHIP_RADEON_QG:
418 /* all original radeons (7200) presumably have a stencil op bug */
419 screen->chip_family = CHIP_FAMILY_R100;
420 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
421 break;
422
423 case PCI_CHIP_RV200_QW:
424 case PCI_CHIP_RV200_QX:
425 case PCI_CHIP_RADEON_LW:
426 case PCI_CHIP_RADEON_LX:
427 screen->chip_family = CHIP_FAMILY_RV200;
428 screen->chip_flags = RADEON_CHIPSET_TCL;
429 break;
430
431 case PCI_CHIP_R200_BB:
432 case PCI_CHIP_R200_BC:
433 case PCI_CHIP_R200_QH:
434 case PCI_CHIP_R200_QL:
435 case PCI_CHIP_R200_QM:
436 screen->chip_family = CHIP_FAMILY_R200;
437 screen->chip_flags = RADEON_CHIPSET_TCL;
438 break;
439
440 case PCI_CHIP_RV250_If:
441 case PCI_CHIP_RV250_Ig:
442 case PCI_CHIP_RV250_Ld:
443 case PCI_CHIP_RV250_Lf:
444 case PCI_CHIP_RV250_Lg:
445 screen->chip_family = CHIP_FAMILY_RV250;
446 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
447 break;
448
449 case PCI_CHIP_RV280_5960:
450 case PCI_CHIP_RV280_5961:
451 case PCI_CHIP_RV280_5962:
452 case PCI_CHIP_RV280_5964:
453 case PCI_CHIP_RV280_5965:
454 case PCI_CHIP_RV280_5C61:
455 case PCI_CHIP_RV280_5C63:
456 screen->chip_family = CHIP_FAMILY_RV280;
457 screen->chip_flags = RADEON_CHIPSET_TCL;
458 break;
459
460 case PCI_CHIP_RS300_5834:
461 case PCI_CHIP_RS300_5835:
462 case PCI_CHIP_RS350_7834:
463 case PCI_CHIP_RS350_7835:
464 screen->chip_family = CHIP_FAMILY_RS300;
465 break;
466
467 case PCI_CHIP_R300_AD:
468 case PCI_CHIP_R300_AE:
469 case PCI_CHIP_R300_AF:
470 case PCI_CHIP_R300_AG:
471 case PCI_CHIP_R300_ND:
472 case PCI_CHIP_R300_NE:
473 case PCI_CHIP_R300_NF:
474 case PCI_CHIP_R300_NG:
475 screen->chip_family = CHIP_FAMILY_R300;
476 screen->chip_flags = RADEON_CHIPSET_TCL;
477 break;
478
479 case PCI_CHIP_RV350_AP:
480 case PCI_CHIP_RV350_AQ:
481 case PCI_CHIP_RV350_AR:
482 case PCI_CHIP_RV350_AS:
483 case PCI_CHIP_RV350_AT:
484 case PCI_CHIP_RV350_AV:
485 case PCI_CHIP_RV350_AU:
486 case PCI_CHIP_RV350_NP:
487 case PCI_CHIP_RV350_NQ:
488 case PCI_CHIP_RV350_NR:
489 case PCI_CHIP_RV350_NS:
490 case PCI_CHIP_RV350_NT:
491 case PCI_CHIP_RV350_NV:
492 screen->chip_family = CHIP_FAMILY_RV350;
493 screen->chip_flags = RADEON_CHIPSET_TCL;
494 break;
495
496 case PCI_CHIP_R350_AH:
497 case PCI_CHIP_R350_AI:
498 case PCI_CHIP_R350_AJ:
499 case PCI_CHIP_R350_AK:
500 case PCI_CHIP_R350_NH:
501 case PCI_CHIP_R350_NI:
502 case PCI_CHIP_R360_NJ:
503 case PCI_CHIP_R350_NK:
504 screen->chip_family = CHIP_FAMILY_R350;
505 screen->chip_flags = RADEON_CHIPSET_TCL;
506 break;
507
508 case PCI_CHIP_RV370_5460:
509 case PCI_CHIP_RV370_5462:
510 case PCI_CHIP_RV370_5464:
511 case PCI_CHIP_RV370_5B60:
512 case PCI_CHIP_RV370_5B62:
513 case PCI_CHIP_RV370_5B63:
514 case PCI_CHIP_RV370_5B64:
515 case PCI_CHIP_RV370_5B65:
516 case PCI_CHIP_RV380_3150:
517 case PCI_CHIP_RV380_3152:
518 case PCI_CHIP_RV380_3154:
519 case PCI_CHIP_RV380_3E50:
520 case PCI_CHIP_RV380_3E54:
521 screen->chip_family = CHIP_FAMILY_RV380;
522 screen->chip_flags = RADEON_CHIPSET_TCL;
523 break;
524
525 case PCI_CHIP_R420_JN:
526 case PCI_CHIP_R420_JH:
527 case PCI_CHIP_R420_JI:
528 case PCI_CHIP_R420_JJ:
529 case PCI_CHIP_R420_JK:
530 case PCI_CHIP_R420_JL:
531 case PCI_CHIP_R420_JM:
532 case PCI_CHIP_R420_JO:
533 case PCI_CHIP_R420_JP:
534 case PCI_CHIP_R420_JT:
535 case PCI_CHIP_R481_4B49:
536 case PCI_CHIP_R481_4B4A:
537 case PCI_CHIP_R481_4B4B:
538 case PCI_CHIP_R481_4B4C:
539 case PCI_CHIP_R423_UH:
540 case PCI_CHIP_R423_UI:
541 case PCI_CHIP_R423_UJ:
542 case PCI_CHIP_R423_UK:
543 case PCI_CHIP_R430_554C:
544 case PCI_CHIP_R430_554D:
545 case PCI_CHIP_R430_554E:
546 case PCI_CHIP_R430_554F:
547 case PCI_CHIP_R423_5550:
548 case PCI_CHIP_R423_UQ:
549 case PCI_CHIP_R423_UR:
550 case PCI_CHIP_R423_UT:
551 case PCI_CHIP_R430_5D48:
552 case PCI_CHIP_R430_5D49:
553 case PCI_CHIP_R430_5D4A:
554 case PCI_CHIP_R480_5D4C:
555 case PCI_CHIP_R480_5D4D:
556 case PCI_CHIP_R480_5D4E:
557 case PCI_CHIP_R480_5D4F:
558 case PCI_CHIP_R480_5D50:
559 case PCI_CHIP_R480_5D52:
560 case PCI_CHIP_R423_5D57:
561 screen->chip_family = CHIP_FAMILY_R420;
562 screen->chip_flags = RADEON_CHIPSET_TCL;
563 break;
564
565 case PCI_CHIP_RV410_5E4C:
566 case PCI_CHIP_RV410_5E4F:
567 case PCI_CHIP_RV410_564A:
568 case PCI_CHIP_RV410_564B:
569 case PCI_CHIP_RV410_564F:
570 case PCI_CHIP_RV410_5652:
571 case PCI_CHIP_RV410_5653:
572 case PCI_CHIP_RV410_5657:
573 case PCI_CHIP_RV410_5E48:
574 case PCI_CHIP_RV410_5E4A:
575 case PCI_CHIP_RV410_5E4B:
576 case PCI_CHIP_RV410_5E4D:
577 screen->chip_family = CHIP_FAMILY_RV410;
578 screen->chip_flags = RADEON_CHIPSET_TCL;
579 break;
580
581 case PCI_CHIP_RS480_5954:
582 case PCI_CHIP_RS480_5955:
583 case PCI_CHIP_RS482_5974:
584 case PCI_CHIP_RS482_5975:
585 case PCI_CHIP_RS400_5A41:
586 case PCI_CHIP_RS400_5A42:
587 case PCI_CHIP_RC410_5A61:
588 case PCI_CHIP_RC410_5A62:
589 screen->chip_family = CHIP_FAMILY_RS400;
590 break;
591
592 case PCI_CHIP_RS600_793F:
593 case PCI_CHIP_RS600_7941:
594 case PCI_CHIP_RS600_7942:
595 screen->chip_family = CHIP_FAMILY_RS600;
596 break;
597
598 case PCI_CHIP_RS690_791E:
599 case PCI_CHIP_RS690_791F:
600 screen->chip_family = CHIP_FAMILY_RS690;
601 break;
602 case PCI_CHIP_RS740_796C:
603 case PCI_CHIP_RS740_796D:
604 case PCI_CHIP_RS740_796E:
605 case PCI_CHIP_RS740_796F:
606 screen->chip_family = CHIP_FAMILY_RS740;
607 break;
608
609 case PCI_CHIP_R520_7100:
610 case PCI_CHIP_R520_7101:
611 case PCI_CHIP_R520_7102:
612 case PCI_CHIP_R520_7103:
613 case PCI_CHIP_R520_7104:
614 case PCI_CHIP_R520_7105:
615 case PCI_CHIP_R520_7106:
616 case PCI_CHIP_R520_7108:
617 case PCI_CHIP_R520_7109:
618 case PCI_CHIP_R520_710A:
619 case PCI_CHIP_R520_710B:
620 case PCI_CHIP_R520_710C:
621 case PCI_CHIP_R520_710E:
622 case PCI_CHIP_R520_710F:
623 screen->chip_family = CHIP_FAMILY_R520;
624 screen->chip_flags = RADEON_CHIPSET_TCL;
625 break;
626
627 case PCI_CHIP_RV515_7140:
628 case PCI_CHIP_RV515_7141:
629 case PCI_CHIP_RV515_7142:
630 case PCI_CHIP_RV515_7143:
631 case PCI_CHIP_RV515_7144:
632 case PCI_CHIP_RV515_7145:
633 case PCI_CHIP_RV515_7146:
634 case PCI_CHIP_RV515_7147:
635 case PCI_CHIP_RV515_7149:
636 case PCI_CHIP_RV515_714A:
637 case PCI_CHIP_RV515_714B:
638 case PCI_CHIP_RV515_714C:
639 case PCI_CHIP_RV515_714D:
640 case PCI_CHIP_RV515_714E:
641 case PCI_CHIP_RV515_714F:
642 case PCI_CHIP_RV515_7151:
643 case PCI_CHIP_RV515_7152:
644 case PCI_CHIP_RV515_7153:
645 case PCI_CHIP_RV515_715E:
646 case PCI_CHIP_RV515_715F:
647 case PCI_CHIP_RV515_7180:
648 case PCI_CHIP_RV515_7181:
649 case PCI_CHIP_RV515_7183:
650 case PCI_CHIP_RV515_7186:
651 case PCI_CHIP_RV515_7187:
652 case PCI_CHIP_RV515_7188:
653 case PCI_CHIP_RV515_718A:
654 case PCI_CHIP_RV515_718B:
655 case PCI_CHIP_RV515_718C:
656 case PCI_CHIP_RV515_718D:
657 case PCI_CHIP_RV515_718F:
658 case PCI_CHIP_RV515_7193:
659 case PCI_CHIP_RV515_7196:
660 case PCI_CHIP_RV515_719B:
661 case PCI_CHIP_RV515_719F:
662 case PCI_CHIP_RV515_7200:
663 case PCI_CHIP_RV515_7210:
664 case PCI_CHIP_RV515_7211:
665 screen->chip_family = CHIP_FAMILY_RV515;
666 screen->chip_flags = RADEON_CHIPSET_TCL;
667 break;
668
669 case PCI_CHIP_RV530_71C0:
670 case PCI_CHIP_RV530_71C1:
671 case PCI_CHIP_RV530_71C2:
672 case PCI_CHIP_RV530_71C3:
673 case PCI_CHIP_RV530_71C4:
674 case PCI_CHIP_RV530_71C5:
675 case PCI_CHIP_RV530_71C6:
676 case PCI_CHIP_RV530_71C7:
677 case PCI_CHIP_RV530_71CD:
678 case PCI_CHIP_RV530_71CE:
679 case PCI_CHIP_RV530_71D2:
680 case PCI_CHIP_RV530_71D4:
681 case PCI_CHIP_RV530_71D5:
682 case PCI_CHIP_RV530_71D6:
683 case PCI_CHIP_RV530_71DA:
684 case PCI_CHIP_RV530_71DE:
685 screen->chip_family = CHIP_FAMILY_RV530;
686 screen->chip_flags = RADEON_CHIPSET_TCL;
687 break;
688
689 case PCI_CHIP_R580_7240:
690 case PCI_CHIP_R580_7243:
691 case PCI_CHIP_R580_7244:
692 case PCI_CHIP_R580_7245:
693 case PCI_CHIP_R580_7246:
694 case PCI_CHIP_R580_7247:
695 case PCI_CHIP_R580_7248:
696 case PCI_CHIP_R580_7249:
697 case PCI_CHIP_R580_724A:
698 case PCI_CHIP_R580_724B:
699 case PCI_CHIP_R580_724C:
700 case PCI_CHIP_R580_724D:
701 case PCI_CHIP_R580_724E:
702 case PCI_CHIP_R580_724F:
703 case PCI_CHIP_R580_7284:
704 screen->chip_family = CHIP_FAMILY_R580;
705 screen->chip_flags = RADEON_CHIPSET_TCL;
706 break;
707
708 case PCI_CHIP_RV570_7280:
709 case PCI_CHIP_RV560_7281:
710 case PCI_CHIP_RV560_7283:
711 case PCI_CHIP_RV560_7287:
712 case PCI_CHIP_RV570_7288:
713 case PCI_CHIP_RV570_7289:
714 case PCI_CHIP_RV570_728B:
715 case PCI_CHIP_RV570_728C:
716 case PCI_CHIP_RV560_7290:
717 case PCI_CHIP_RV560_7291:
718 case PCI_CHIP_RV560_7293:
719 case PCI_CHIP_RV560_7297:
720 screen->chip_family = CHIP_FAMILY_RV560;
721 screen->chip_flags = RADEON_CHIPSET_TCL;
722 break;
723
724 case PCI_CHIP_R600_9400:
725 case PCI_CHIP_R600_9401:
726 case PCI_CHIP_R600_9402:
727 case PCI_CHIP_R600_9403:
728 case PCI_CHIP_R600_9405:
729 case PCI_CHIP_R600_940A:
730 case PCI_CHIP_R600_940B:
731 case PCI_CHIP_R600_940F:
732 screen->chip_family = CHIP_FAMILY_R600;
733 screen->chip_flags = RADEON_CHIPSET_TCL;
734 break;
735
736 case PCI_CHIP_RV610_94C0:
737 case PCI_CHIP_RV610_94C1:
738 case PCI_CHIP_RV610_94C3:
739 case PCI_CHIP_RV610_94C4:
740 case PCI_CHIP_RV610_94C5:
741 case PCI_CHIP_RV610_94C6:
742 case PCI_CHIP_RV610_94C7:
743 case PCI_CHIP_RV610_94C8:
744 case PCI_CHIP_RV610_94C9:
745 case PCI_CHIP_RV610_94CB:
746 case PCI_CHIP_RV610_94CC:
747 case PCI_CHIP_RV610_94CD:
748 screen->chip_family = CHIP_FAMILY_RV610;
749 screen->chip_flags = RADEON_CHIPSET_TCL;
750 break;
751
752 case PCI_CHIP_RV630_9580:
753 case PCI_CHIP_RV630_9581:
754 case PCI_CHIP_RV630_9583:
755 case PCI_CHIP_RV630_9586:
756 case PCI_CHIP_RV630_9587:
757 case PCI_CHIP_RV630_9588:
758 case PCI_CHIP_RV630_9589:
759 case PCI_CHIP_RV630_958A:
760 case PCI_CHIP_RV630_958B:
761 case PCI_CHIP_RV630_958C:
762 case PCI_CHIP_RV630_958D:
763 case PCI_CHIP_RV630_958E:
764 case PCI_CHIP_RV630_958F:
765 screen->chip_family = CHIP_FAMILY_RV630;
766 screen->chip_flags = RADEON_CHIPSET_TCL;
767 break;
768
769 case PCI_CHIP_RV670_9500:
770 case PCI_CHIP_RV670_9501:
771 case PCI_CHIP_RV670_9504:
772 case PCI_CHIP_RV670_9505:
773 case PCI_CHIP_RV670_9506:
774 case PCI_CHIP_RV670_9507:
775 case PCI_CHIP_RV670_9508:
776 case PCI_CHIP_RV670_9509:
777 case PCI_CHIP_RV670_950F:
778 case PCI_CHIP_RV670_9511:
779 case PCI_CHIP_RV670_9515:
780 case PCI_CHIP_RV670_9517:
781 case PCI_CHIP_RV670_9519:
782 screen->chip_family = CHIP_FAMILY_RV670;
783 screen->chip_flags = RADEON_CHIPSET_TCL;
784 break;
785
786 case PCI_CHIP_RV620_95C0:
787 case PCI_CHIP_RV620_95C2:
788 case PCI_CHIP_RV620_95C4:
789 case PCI_CHIP_RV620_95C5:
790 case PCI_CHIP_RV620_95C6:
791 case PCI_CHIP_RV620_95C7:
792 case PCI_CHIP_RV620_95C9:
793 case PCI_CHIP_RV620_95CC:
794 case PCI_CHIP_RV620_95CD:
795 case PCI_CHIP_RV620_95CE:
796 case PCI_CHIP_RV620_95CF:
797 screen->chip_family = CHIP_FAMILY_RV620;
798 screen->chip_flags = RADEON_CHIPSET_TCL;
799 break;
800
801 case PCI_CHIP_RV635_9590:
802 case PCI_CHIP_RV635_9591:
803 case PCI_CHIP_RV635_9593:
804 case PCI_CHIP_RV635_9595:
805 case PCI_CHIP_RV635_9596:
806 case PCI_CHIP_RV635_9597:
807 case PCI_CHIP_RV635_9598:
808 case PCI_CHIP_RV635_9599:
809 case PCI_CHIP_RV635_959B:
810 screen->chip_family = CHIP_FAMILY_RV635;
811 screen->chip_flags = RADEON_CHIPSET_TCL;
812 break;
813
814 case PCI_CHIP_RS780_9610:
815 case PCI_CHIP_RS780_9611:
816 case PCI_CHIP_RS780_9612:
817 case PCI_CHIP_RS780_9613:
818 case PCI_CHIP_RS780_9614:
819 case PCI_CHIP_RS780_9615:
820 case PCI_CHIP_RS780_9616:
821 screen->chip_family = CHIP_FAMILY_RS780;
822 screen->chip_flags = RADEON_CHIPSET_TCL;
823 break;
824 case PCI_CHIP_RS880_9710:
825 case PCI_CHIP_RS880_9711:
826 case PCI_CHIP_RS880_9712:
827 case PCI_CHIP_RS880_9713:
828 case PCI_CHIP_RS880_9714:
829 case PCI_CHIP_RS880_9715:
830 screen->chip_family = CHIP_FAMILY_RS880;
831 screen->chip_flags = RADEON_CHIPSET_TCL;
832 break;
833
834 case PCI_CHIP_RV770_9440:
835 case PCI_CHIP_RV770_9441:
836 case PCI_CHIP_RV770_9442:
837 case PCI_CHIP_RV770_9443:
838 case PCI_CHIP_RV770_9444:
839 case PCI_CHIP_RV770_9446:
840 case PCI_CHIP_RV770_944A:
841 case PCI_CHIP_RV770_944B:
842 case PCI_CHIP_RV770_944C:
843 case PCI_CHIP_RV770_944E:
844 case PCI_CHIP_RV770_9450:
845 case PCI_CHIP_RV770_9452:
846 case PCI_CHIP_RV770_9456:
847 case PCI_CHIP_RV770_945A:
848 case PCI_CHIP_RV770_945B:
849 case PCI_CHIP_RV790_9460:
850 case PCI_CHIP_RV790_9462:
851 case PCI_CHIP_RV770_946A:
852 case PCI_CHIP_RV770_946B:
853 case PCI_CHIP_RV770_947A:
854 case PCI_CHIP_RV770_947B:
855 screen->chip_family = CHIP_FAMILY_RV770;
856 screen->chip_flags = RADEON_CHIPSET_TCL;
857 break;
858
859 case PCI_CHIP_RV730_9480:
860 case PCI_CHIP_RV730_9487:
861 case PCI_CHIP_RV730_9488:
862 case PCI_CHIP_RV730_9489:
863 case PCI_CHIP_RV730_948F:
864 case PCI_CHIP_RV730_9490:
865 case PCI_CHIP_RV730_9491:
866 case PCI_CHIP_RV730_9495:
867 case PCI_CHIP_RV730_9498:
868 case PCI_CHIP_RV730_949C:
869 case PCI_CHIP_RV730_949E:
870 case PCI_CHIP_RV730_949F:
871 screen->chip_family = CHIP_FAMILY_RV730;
872 screen->chip_flags = RADEON_CHIPSET_TCL;
873 break;
874
875 case PCI_CHIP_RV710_9540:
876 case PCI_CHIP_RV710_9541:
877 case PCI_CHIP_RV710_9542:
878 case PCI_CHIP_RV710_954E:
879 case PCI_CHIP_RV710_954F:
880 case PCI_CHIP_RV710_9552:
881 case PCI_CHIP_RV710_9553:
882 case PCI_CHIP_RV710_9555:
883 case PCI_CHIP_RV710_9557:
884 screen->chip_family = CHIP_FAMILY_RV710;
885 screen->chip_flags = RADEON_CHIPSET_TCL;
886 break;
887
888 case PCI_CHIP_RV740_94A0:
889 case PCI_CHIP_RV740_94A1:
890 case PCI_CHIP_RV740_94A3:
891 case PCI_CHIP_RV740_94B1:
892 case PCI_CHIP_RV740_94B3:
893 case PCI_CHIP_RV740_94B4:
894 case PCI_CHIP_RV740_94B5:
895 case PCI_CHIP_RV740_94B9:
896 screen->chip_family = CHIP_FAMILY_RV740;
897 screen->chip_flags = RADEON_CHIPSET_TCL;
898 break;
899
900 default:
901 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
902 device_id);
903 return -1;
904 }
905
906 return 0;
907 }
908
909
910 /* Create the device specific screen private data struct.
911 */
912 static radeonScreenPtr
913 radeonCreateScreen( __DRIscreen *sPriv )
914 {
915 radeonScreenPtr screen;
916 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
917 unsigned char *RADEONMMIO = NULL;
918 int i;
919 int ret;
920 uint32_t temp = 0;
921
922 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
923 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
924 return GL_FALSE;
925 }
926
927 /* Allocate the private area */
928 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
929 if ( !screen ) {
930 __driUtilMessage("%s: Could not allocate memory for screen structure",
931 __FUNCTION__);
932 return NULL;
933 }
934
935 radeon_init_debug();
936
937 /* parse information in __driConfigOptions */
938 driParseOptionInfo (&screen->optionCache,
939 __driConfigOptions, __driNConfigOptions);
940
941 /* This is first since which regions we map depends on whether or
942 * not we are using a PCI card.
943 */
944 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
945 {
946 int ret;
947
948 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
949 &screen->gart_buffer_offset);
950
951 if (ret) {
952 FREE( screen );
953 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
954 return NULL;
955 }
956
957 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
958 &screen->gart_base);
959 if (ret) {
960 FREE( screen );
961 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
962 return NULL;
963 }
964
965 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
966 &screen->irq);
967 if (ret) {
968 FREE( screen );
969 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
970 return NULL;
971 }
972 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
973 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
974 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
975 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
976 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
977 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
978 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
979 screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30);
980 }
981
982 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
983 if (ret == -1)
984 return NULL;
985
986 screen->mmio.handle = dri_priv->registerHandle;
987 screen->mmio.size = dri_priv->registerSize;
988 if ( drmMap( sPriv->fd,
989 screen->mmio.handle,
990 screen->mmio.size,
991 &screen->mmio.map ) ) {
992 FREE( screen );
993 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
994 return NULL;
995 }
996
997 RADEONMMIO = screen->mmio.map;
998
999 screen->status.handle = dri_priv->statusHandle;
1000 screen->status.size = dri_priv->statusSize;
1001 if ( drmMap( sPriv->fd,
1002 screen->status.handle,
1003 screen->status.size,
1004 &screen->status.map ) ) {
1005 drmUnmap( screen->mmio.map, screen->mmio.size );
1006 FREE( screen );
1007 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
1008 return NULL;
1009 }
1010 if (screen->chip_family < CHIP_FAMILY_R600)
1011 screen->scratch = (__volatile__ uint32_t *)
1012 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
1013 else
1014 screen->scratch = (__volatile__ uint32_t *)
1015 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET);
1016
1017 screen->buffers = drmMapBufs( sPriv->fd );
1018 if ( !screen->buffers ) {
1019 drmUnmap( screen->status.map, screen->status.size );
1020 drmUnmap( screen->mmio.map, screen->mmio.size );
1021 FREE( screen );
1022 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
1023 return NULL;
1024 }
1025
1026 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
1027 screen->gartTextures.handle = dri_priv->gartTexHandle;
1028 screen->gartTextures.size = dri_priv->gartTexMapSize;
1029 if ( drmMap( sPriv->fd,
1030 screen->gartTextures.handle,
1031 screen->gartTextures.size,
1032 (drmAddressPtr)&screen->gartTextures.map ) ) {
1033 drmUnmapBufs( screen->buffers );
1034 drmUnmap( screen->status.map, screen->status.size );
1035 drmUnmap( screen->mmio.map, screen->mmio.size );
1036 FREE( screen );
1037 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
1038 return NULL;
1039 }
1040
1041 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
1042 }
1043
1044 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
1045 sPriv->ddx_version.minor < 2) {
1046 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1047 return NULL;
1048 }
1049
1050 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
1051 fprintf(stderr, "R500 support requires a newer drm.\n");
1052 return NULL;
1053 }
1054
1055 if (getenv("R300_NO_TCL"))
1056 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1057
1058 if (screen->chip_family <= CHIP_FAMILY_RS200)
1059 screen->chip_flags |= RADEON_CLASS_R100;
1060 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1061 screen->chip_flags |= RADEON_CLASS_R200;
1062 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1063 screen->chip_flags |= RADEON_CLASS_R300;
1064 else
1065 screen->chip_flags |= RADEON_CLASS_R600;
1066
1067 screen->cpp = dri_priv->bpp / 8;
1068 screen->AGPMode = dri_priv->AGPMode;
1069
1070 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
1071
1072 /* +r6/r7 */
1073 if(screen->chip_family >= CHIP_FAMILY_R600)
1074 {
1075 if (ret)
1076 {
1077 FREE( screen );
1078 fprintf(stderr, "Unable to get fb location need newer drm\n");
1079 return NULL;
1080 }
1081 else
1082 {
1083 screen->fbLocation = (temp & 0xffff) << 24;
1084 }
1085 }
1086 else
1087 {
1088 if (ret)
1089 {
1090 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
1091 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
1092 else
1093 {
1094 FREE( screen );
1095 fprintf(stderr, "Unable to get fb location need newer drm\n");
1096 return NULL;
1097 }
1098 }
1099 else
1100 {
1101 screen->fbLocation = (temp & 0xffff) << 16;
1102 }
1103 }
1104
1105 if (IS_R300_CLASS(screen)) {
1106 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1107 if (ret) {
1108 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1109 switch (screen->chip_family) {
1110 case CHIP_FAMILY_R300:
1111 case CHIP_FAMILY_R350:
1112 screen->num_gb_pipes = 2;
1113 break;
1114 case CHIP_FAMILY_R420:
1115 case CHIP_FAMILY_R520:
1116 case CHIP_FAMILY_R580:
1117 case CHIP_FAMILY_RV560:
1118 case CHIP_FAMILY_RV570:
1119 screen->num_gb_pipes = 4;
1120 break;
1121 case CHIP_FAMILY_RV350:
1122 case CHIP_FAMILY_RV515:
1123 case CHIP_FAMILY_RV530:
1124 case CHIP_FAMILY_RV410:
1125 default:
1126 screen->num_gb_pipes = 1;
1127 break;
1128 }
1129 } else {
1130 screen->num_gb_pipes = temp;
1131 }
1132
1133 /* pipe overrides */
1134 switch (dri_priv->deviceID) {
1135 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1136 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1137 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1138 screen->num_gb_pipes = 1;
1139 break;
1140 default:
1141 break;
1142 }
1143
1144 if ( sPriv->drm_version.minor >= 31 ) {
1145 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1146 if (ret)
1147 screen->num_z_pipes = 2;
1148 else
1149 screen->num_z_pipes = temp;
1150 } else
1151 screen->num_z_pipes = 2;
1152 }
1153
1154 if ( sPriv->drm_version.minor >= 10 ) {
1155 drm_radeon_setparam_t sp;
1156
1157 sp.param = RADEON_SETPARAM_FB_LOCATION;
1158 sp.value = screen->fbLocation;
1159
1160 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
1161 &sp, sizeof( sp ) );
1162 }
1163
1164 screen->frontOffset = dri_priv->frontOffset;
1165 screen->frontPitch = dri_priv->frontPitch;
1166 screen->backOffset = dri_priv->backOffset;
1167 screen->backPitch = dri_priv->backPitch;
1168 screen->depthOffset = dri_priv->depthOffset;
1169 screen->depthPitch = dri_priv->depthPitch;
1170
1171 /* Check if ddx has set up a surface reg to cover depth buffer */
1172 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
1173 /* these chips don't use tiled z without hyperz. So always pretend
1174 we have set up a surface which will cause linear reads/writes */
1175 (IS_R100_CLASS(screen) &&
1176 !(screen->chip_flags & RADEON_CHIPSET_TCL));
1177
1178 if ( dri_priv->textureSize == 0 ) {
1179 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
1180 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
1181 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1182 dri_priv->log2GARTTexGran;
1183 } else {
1184 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
1185 + screen->fbLocation;
1186 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
1187 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1188 dri_priv->log2TexGran;
1189 }
1190
1191 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
1192 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1193 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
1194 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
1195 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
1196 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
1197 } else {
1198 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
1199 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
1200 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
1201 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
1202 dri_priv->log2GARTTexGran;
1203 }
1204
1205 i = 0;
1206 screen->extensions[i++] = &driCopySubBufferExtension.base;
1207 screen->extensions[i++] = &driFrameTrackingExtension.base;
1208 screen->extensions[i++] = &driReadDrawableExtension;
1209
1210 if ( screen->irq != 0 ) {
1211 screen->extensions[i++] = &driSwapControlExtension.base;
1212 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1213 }
1214
1215 #if defined(RADEON_R100)
1216 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1217 #endif
1218
1219 #if defined(RADEON_R200)
1220 if (IS_R200_CLASS(screen))
1221 screen->extensions[i++] = &r200AllocateExtension.base;
1222
1223 screen->extensions[i++] = &r200texOffsetExtension.base;
1224 #endif
1225
1226 #if defined(RADEON_R300)
1227 screen->extensions[i++] = &r300texOffsetExtension.base;
1228 #endif
1229
1230 #if defined(RADEON_R600)
1231 screen->extensions[i++] = &r600texOffsetExtension.base;
1232 #endif
1233
1234 screen->extensions[i++] = NULL;
1235 sPriv->extensions = screen->extensions;
1236
1237 screen->driScreen = sPriv;
1238 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1239 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1240 screen->sarea_priv_offset);
1241
1242 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1243 if (screen->bom == NULL) {
1244 free(screen);
1245 return NULL;
1246 }
1247
1248 return screen;
1249 }
1250
1251 static radeonScreenPtr
1252 radeonCreateScreen2(__DRIscreen *sPriv)
1253 {
1254 radeonScreenPtr screen;
1255 int i;
1256 int ret;
1257 uint32_t device_id = 0;
1258 uint32_t temp = 0;
1259
1260 /* Allocate the private area */
1261 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1262 if ( !screen ) {
1263 __driUtilMessage("%s: Could not allocate memory for screen structure",
1264 __FUNCTION__);
1265 fprintf(stderr, "leaving here\n");
1266 return NULL;
1267 }
1268
1269 radeon_init_debug();
1270
1271 /* parse information in __driConfigOptions */
1272 driParseOptionInfo (&screen->optionCache,
1273 __driConfigOptions, __driNConfigOptions);
1274
1275 screen->kernel_mm = 1;
1276 screen->chip_flags = 0;
1277
1278 /* if we have kms we can support all of these */
1279 screen->drmSupportsCubeMapsR200 = 1;
1280 screen->drmSupportsBlendColor = 1;
1281 screen->drmSupportsTriPerf = 1;
1282 screen->drmSupportsFragShader = 1;
1283 screen->drmSupportsPointSprites = 1;
1284 screen->drmSupportsCubeMapsR100 = 1;
1285 screen->drmSupportsVertexProgram = 1;
1286 screen->drmSupportsOcclusionQueries = 1;
1287 screen->irq = 1;
1288
1289 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1290 if (ret) {
1291 FREE( screen );
1292 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1293 return NULL;
1294 }
1295
1296 ret = radeon_set_screen_flags(screen, device_id);
1297 if (ret == -1)
1298 return NULL;
1299
1300 if (getenv("R300_NO_TCL"))
1301 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1302
1303 if (screen->chip_family <= CHIP_FAMILY_RS200)
1304 screen->chip_flags |= RADEON_CLASS_R100;
1305 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1306 screen->chip_flags |= RADEON_CLASS_R200;
1307 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1308 screen->chip_flags |= RADEON_CLASS_R300;
1309 else
1310 screen->chip_flags |= RADEON_CLASS_R600;
1311
1312 if (IS_R300_CLASS(screen)) {
1313 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1314 if (ret) {
1315 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1316 switch (screen->chip_family) {
1317 case CHIP_FAMILY_R300:
1318 case CHIP_FAMILY_R350:
1319 screen->num_gb_pipes = 2;
1320 break;
1321 case CHIP_FAMILY_R420:
1322 case CHIP_FAMILY_R520:
1323 case CHIP_FAMILY_R580:
1324 case CHIP_FAMILY_RV560:
1325 case CHIP_FAMILY_RV570:
1326 screen->num_gb_pipes = 4;
1327 break;
1328 case CHIP_FAMILY_RV350:
1329 case CHIP_FAMILY_RV515:
1330 case CHIP_FAMILY_RV530:
1331 case CHIP_FAMILY_RV410:
1332 default:
1333 screen->num_gb_pipes = 1;
1334 break;
1335 }
1336 } else {
1337 screen->num_gb_pipes = temp;
1338 }
1339
1340 /* pipe overrides */
1341 switch (device_id) {
1342 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1343 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1344 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1345 screen->num_gb_pipes = 1;
1346 break;
1347 default:
1348 break;
1349 }
1350
1351 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1352 if (ret)
1353 screen->num_z_pipes = 2;
1354 else
1355 screen->num_z_pipes = temp;
1356
1357 }
1358
1359 i = 0;
1360 screen->extensions[i++] = &driCopySubBufferExtension.base;
1361 screen->extensions[i++] = &driFrameTrackingExtension.base;
1362 screen->extensions[i++] = &driReadDrawableExtension;
1363
1364 if ( screen->irq != 0 ) {
1365 screen->extensions[i++] = &driSwapControlExtension.base;
1366 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1367 }
1368
1369 #if defined(RADEON_R100)
1370 screen->extensions[i++] = &radeonTexBufferExtension.base;
1371 #endif
1372
1373 #if defined(RADEON_R200)
1374 if (IS_R200_CLASS(screen))
1375 screen->extensions[i++] = &r200AllocateExtension.base;
1376
1377 screen->extensions[i++] = &r200TexBufferExtension.base;
1378 #endif
1379
1380 #if defined(RADEON_R300)
1381 screen->extensions[i++] = &r300TexBufferExtension.base;
1382 #endif
1383
1384 #if defined(RADEON_R600)
1385 screen->extensions[i++] = &r600TexBufferExtension.base;
1386 #endif
1387
1388 screen->extensions[i++] = NULL;
1389 sPriv->extensions = screen->extensions;
1390
1391 screen->driScreen = sPriv;
1392 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1393 if (screen->bom == NULL) {
1394 free(screen);
1395 return NULL;
1396 }
1397 return screen;
1398 }
1399
1400 /* Destroy the device specific screen private data struct.
1401 */
1402 static void
1403 radeonDestroyScreen( __DRIscreen *sPriv )
1404 {
1405 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1406
1407 if (!screen)
1408 return;
1409
1410 if (screen->kernel_mm) {
1411 #ifdef RADEON_BO_TRACK
1412 radeon_tracker_print(&screen->bom->tracker, stderr);
1413 #endif
1414 radeon_bo_manager_gem_dtor(screen->bom);
1415 } else {
1416 radeon_bo_manager_legacy_dtor(screen->bom);
1417
1418 if ( screen->gartTextures.map ) {
1419 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1420 }
1421 drmUnmapBufs( screen->buffers );
1422 drmUnmap( screen->status.map, screen->status.size );
1423 drmUnmap( screen->mmio.map, screen->mmio.size );
1424 }
1425
1426 /* free all option information */
1427 driDestroyOptionInfo (&screen->optionCache);
1428
1429 FREE( screen );
1430 sPriv->private = NULL;
1431 }
1432
1433
1434 /* Initialize the driver specific screen private data.
1435 */
1436 static GLboolean
1437 radeonInitDriver( __DRIscreen *sPriv )
1438 {
1439 if (sPriv->dri2.enabled) {
1440 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1441 } else {
1442 sPriv->private = (void *) radeonCreateScreen( sPriv );
1443 }
1444 if ( !sPriv->private ) {
1445 radeonDestroyScreen( sPriv );
1446 return GL_FALSE;
1447 }
1448
1449 return GL_TRUE;
1450 }
1451
1452
1453
1454 /**
1455 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1456 *
1457 * \todo This function (and its interface) will need to be updated to support
1458 * pbuffers.
1459 */
1460 static GLboolean
1461 radeonCreateBuffer( __DRIscreen *driScrnPriv,
1462 __DRIdrawable *driDrawPriv,
1463 const __GLcontextModes *mesaVis,
1464 GLboolean isPixmap )
1465 {
1466 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1467
1468 const GLboolean swDepth = GL_FALSE;
1469 const GLboolean swAlpha = GL_FALSE;
1470 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1471 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1472 mesaVis->depthBits != 24;
1473 gl_format rgbFormat;
1474 struct radeon_framebuffer *rfb;
1475
1476 if (isPixmap)
1477 return GL_FALSE; /* not implemented */
1478
1479 rfb = CALLOC_STRUCT(radeon_framebuffer);
1480 if (!rfb)
1481 return GL_FALSE;
1482
1483 _mesa_initialize_window_framebuffer(&rfb->base, mesaVis);
1484
1485 if (mesaVis->redBits == 5)
1486 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV;
1487 else if (mesaVis->alphaBits == 0)
1488 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV;
1489 else
1490 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV;
1491
1492 /* front color renderbuffer */
1493 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1494 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1495 rfb->color_rb[0]->has_surface = 1;
1496
1497 /* back color renderbuffer */
1498 if (mesaVis->doubleBufferMode) {
1499 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1500 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1501 rfb->color_rb[1]->has_surface = 1;
1502 }
1503
1504 if (mesaVis->depthBits == 24) {
1505 if (mesaVis->stencilBits == 8) {
1506 struct radeon_renderbuffer *depthStencilRb =
1507 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv);
1508 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1509 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1510 depthStencilRb->has_surface = screen->depthHasSurface;
1511 } else {
1512 /* depth renderbuffer */
1513 struct radeon_renderbuffer *depth =
1514 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv);
1515 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1516 depth->has_surface = screen->depthHasSurface;
1517 }
1518 } else if (mesaVis->depthBits == 16) {
1519 /* just 16-bit depth buffer, no hw stencil */
1520 struct radeon_renderbuffer *depth =
1521 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv);
1522 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1523 depth->has_surface = screen->depthHasSurface;
1524 }
1525
1526 _mesa_add_soft_renderbuffers(&rfb->base,
1527 GL_FALSE, /* color */
1528 swDepth,
1529 swStencil,
1530 swAccum,
1531 swAlpha,
1532 GL_FALSE /* aux */);
1533 driDrawPriv->driverPrivate = (void *) rfb;
1534
1535 return (driDrawPriv->driverPrivate != NULL);
1536 }
1537
1538
1539 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1540 {
1541 struct radeon_renderbuffer *rb;
1542
1543 rb = rfb->color_rb[0];
1544 if (rb && rb->bo) {
1545 radeon_bo_unref(rb->bo);
1546 rb->bo = NULL;
1547 }
1548 rb = rfb->color_rb[1];
1549 if (rb && rb->bo) {
1550 radeon_bo_unref(rb->bo);
1551 rb->bo = NULL;
1552 }
1553 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1554 if (rb && rb->bo) {
1555 radeon_bo_unref(rb->bo);
1556 rb->bo = NULL;
1557 }
1558 }
1559
1560 void
1561 radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
1562 {
1563 struct radeon_framebuffer *rfb;
1564 if (!driDrawPriv)
1565 return;
1566
1567 rfb = (void*)driDrawPriv->driverPrivate;
1568 if (!rfb)
1569 return;
1570 radeon_cleanup_renderbuffers(rfb);
1571 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1572 }
1573
1574
1575 /**
1576 * This is the driver specific part of the createNewScreen entry point.
1577 *
1578 * \todo maybe fold this into intelInitDriver
1579 *
1580 * \return the __GLcontextModes supported by this driver
1581 */
1582 static const __DRIconfig **
1583 radeonInitScreen(__DRIscreen *psp)
1584 {
1585 #if defined(RADEON_R100)
1586 static const char *driver_name = "Radeon";
1587 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1588 static const __DRIversion dri_expected = { 4, 0, 0 };
1589 static const __DRIversion drm_expected = { 1, 6, 0 };
1590 #elif defined(RADEON_R200)
1591 static const char *driver_name = "R200";
1592 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1593 static const __DRIversion dri_expected = { 4, 0, 0 };
1594 static const __DRIversion drm_expected = { 1, 6, 0 };
1595 #elif defined(RADEON_R300)
1596 static const char *driver_name = "R300";
1597 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1598 static const __DRIversion dri_expected = { 4, 0, 0 };
1599 static const __DRIversion drm_expected = { 1, 24, 0 };
1600 #elif defined(RADEON_R600)
1601 static const char *driver_name = "R600";
1602 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1603 static const __DRIversion dri_expected = { 4, 0, 0 };
1604 static const __DRIversion drm_expected = { 1, 24, 0 };
1605 #endif
1606 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1607
1608 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1609 &psp->dri_version, & dri_expected,
1610 &psp->ddx_version, & ddx_expected,
1611 &psp->drm_version, & drm_expected ) ) {
1612 return NULL;
1613 }
1614
1615 if (!radeonInitDriver(psp))
1616 return NULL;
1617
1618 /* for now fill in all modes */
1619 return radeonFillInModes( psp,
1620 dri_priv->bpp,
1621 (dri_priv->bpp == 16) ? 16 : 24,
1622 (dri_priv->bpp == 16) ? 0 : 8, 1);
1623 }
1624 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1625
1626 /**
1627 * This is the driver specific part of the createNewScreen entry point.
1628 * Called when using DRI2.
1629 *
1630 * \return the __GLcontextModes supported by this driver
1631 */
1632 static const
1633 __DRIconfig **radeonInitScreen2(__DRIscreen *psp)
1634 {
1635 GLenum fb_format[3];
1636 GLenum fb_type[3];
1637 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1638 * support pageflipping at all.
1639 */
1640 static const GLenum back_buffer_modes[] = {
1641 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1642 };
1643 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1644 int color;
1645 __DRIconfig **configs = NULL;
1646
1647 if (!radeonInitDriver(psp)) {
1648 return NULL;
1649 }
1650 depth_bits[0] = 0;
1651 stencil_bits[0] = 0;
1652 depth_bits[1] = 16;
1653 stencil_bits[1] = 0;
1654 depth_bits[2] = 24;
1655 stencil_bits[2] = 0;
1656 depth_bits[3] = 24;
1657 stencil_bits[3] = 8;
1658
1659 msaa_samples_array[0] = 0;
1660
1661 fb_format[0] = GL_RGB;
1662 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1663
1664 fb_format[1] = GL_BGR;
1665 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1666
1667 fb_format[2] = GL_BGRA;
1668 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1669
1670 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1671 __DRIconfig **new_configs;
1672
1673 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1674 depth_bits,
1675 stencil_bits,
1676 ARRAY_SIZE(depth_bits),
1677 back_buffer_modes,
1678 ARRAY_SIZE(back_buffer_modes),
1679 msaa_samples_array,
1680 ARRAY_SIZE(msaa_samples_array),
1681 GL_TRUE);
1682 if (configs == NULL)
1683 configs = new_configs;
1684 else
1685 configs = driConcatConfigs(configs, new_configs);
1686 }
1687
1688 if (configs == NULL) {
1689 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1690 __LINE__);
1691 return NULL;
1692 }
1693
1694 return (const __DRIconfig **)configs;
1695 }
1696
1697 /**
1698 * Get information about previous buffer swaps.
1699 */
1700 static int
1701 getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo )
1702 {
1703 struct radeon_framebuffer *rfb;
1704
1705 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1706 || (dPriv->driContextPriv->driverPrivate == NULL)
1707 || (sInfo == NULL) ) {
1708 return -1;
1709 }
1710
1711 rfb = dPriv->driverPrivate;
1712 sInfo->swap_count = rfb->swap_count;
1713 sInfo->swap_ust = rfb->swap_ust;
1714 sInfo->swap_missed_count = rfb->swap_missed_count;
1715
1716 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1717 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
1718 : 0.0;
1719
1720 return 0;
1721 }
1722
1723 const struct __DriverAPIRec driDriverAPI = {
1724 .InitScreen = radeonInitScreen,
1725 .DestroyScreen = radeonDestroyScreen,
1726 #if defined(RADEON_R200)
1727 .CreateContext = r200CreateContext,
1728 .DestroyContext = r200DestroyContext,
1729 #elif defined(RADEON_R600)
1730 .CreateContext = r600CreateContext,
1731 .DestroyContext = radeonDestroyContext,
1732 #elif defined(RADEON_R300)
1733 .CreateContext = r300CreateContext,
1734 .DestroyContext = radeonDestroyContext,
1735 #else
1736 .CreateContext = r100CreateContext,
1737 .DestroyContext = radeonDestroyContext,
1738 #endif
1739 .CreateBuffer = radeonCreateBuffer,
1740 .DestroyBuffer = radeonDestroyBuffer,
1741 .SwapBuffers = radeonSwapBuffers,
1742 .MakeCurrent = radeonMakeCurrent,
1743 .UnbindContext = radeonUnbindContext,
1744 .GetSwapInfo = getSwapInfo,
1745 .GetDrawableMSC = driDrawableGetMSC32,
1746 .WaitForMSC = driWaitForMSC32,
1747 .WaitForSBC = NULL,
1748 .SwapBuffersMSC = NULL,
1749 .CopySubBuffer = radeonCopySubBuffer,
1750 /* DRI2 */
1751 .InitScreen2 = radeonInitScreen2,
1752 };
1753
1754 /* This is the table of extensions that the loader will dlsym() for. */
1755 PUBLIC const __DRIextension *__driDriverExtensions[] = {
1756 &driCoreExtension.base,
1757 &driLegacyExtension.base,
1758 &driDRI2Extension.base,
1759 NULL
1760 };