src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41 #include "main/simple_list.h"
  42
  43 #include "math/m_xform.h"
  44
  45 #include "swrast_setup/swrast_setup.h"
  46
  47 #include "tnl/tnl.h"
  48 #include "tnl/t_context.h"
  49 #include "tnl/t_pipeline.h"
  50
  51 #include "radeon_context.h"
  52 #include "radeon_ioctl.h"
  53 #include "radeon_state.h"
  54 #include "radeon_swtcl.h"
  55 #include "radeon_tcl.h"
  56 #include "radeon_debug.h"
  57
  58
  59 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  60 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  61 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  62
  63 /***********************************************************************
  64  *                         Initialization
  65  ***********************************************************************/
  66
  67 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  68 do {                                                                    \
  69    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);     \
  70    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);    \
  71    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  72    fmt_0 |= F0;                                                         \
  73 } while (0)
  74
  75 #define EMIT_PAD( N )                                                   \
  76 do {                                                                    \
  77    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;          \
  78    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;   \
  79    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);                \
  80    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  81 } while (0)
  82
  83 static GLuint radeon_cp_vc_frmts[3][2] =
  84 {
  85    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  86    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  87    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  88 };
  89
  90 static void radeonSetVertexFormat( struct gl_context *ctx )
  91 {
  92    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  93    TNLcontext *tnl = TNL_CONTEXT(ctx);
  94    struct vertex_buffer *VB = &tnl->vb;
  95    DECLARE_RENDERINPUTS(index_bitset);
  96    int fmt_0 = 0;
  97    int offset = 0;
  98
  99    RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
 100
 101    /* Important:
 102     */
 103    if ( VB->NdcPtr != NULL ) {
 104       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 105    }
 106    else {
 107       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 108    }
 109
 110    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 111    rmesa->radeon.swtcl.vertex_attr_count = 0;
 112
 113    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 114     * build up a hardware vertex.
 115     */
 116    if ( !rmesa->swtcl.needproj ||
 117         RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {       /* for projtex */
 118       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 119                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 120       offset = 4;
 121    }
 122    else {
 123       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 124                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 125       offset = 3;
 126    }
 127
 128    rmesa->swtcl.coloroffset = offset;
 129 #if MESA_LITTLE_ENDIAN
 130    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 131               RADEON_CP_VC_FRMT_PKCOLOR );
 132 #else
 133    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 134               RADEON_CP_VC_FRMT_PKCOLOR );
 135 #endif
 136    offset += 1;
 137
 138    rmesa->swtcl.specoffset = 0;
 139    if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
 140        RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 141
 142 #if MESA_LITTLE_ENDIAN
 143       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 144          rmesa->swtcl.specoffset = offset;
 145          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 146                     RADEON_CP_VC_FRMT_PKSPEC );
 147       }
 148       else {
 149          EMIT_PAD( 3 );
 150       }
 151
 152       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 153          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 154                     RADEON_CP_VC_FRMT_PKSPEC );
 155       }
 156       else {
 157          EMIT_PAD( 1 );
 158       }
 159 #else
 160       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 161          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 162                     RADEON_CP_VC_FRMT_PKSPEC );
 163       }
 164       else {
 165          EMIT_PAD( 1 );
 166       }
 167
 168       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 169          rmesa->swtcl.specoffset = offset;
 170          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 171                     RADEON_CP_VC_FRMT_PKSPEC );
 172       }
 173       else {
 174          EMIT_PAD( 3 );
 175       }
 176 #endif
 177    }
 178
 179    if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
 180       int i;
 181
 182       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 183          if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
 184             GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
 185
 186             switch (sz) {
 187             case 1:
 188             case 2:
 189                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 190                           radeon_cp_vc_frmts[i][0] );
 191                break;
 192             case 3:
 193             case 4:
 194                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 195                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 196                              radeon_cp_vc_frmts[i][1] );
 197                } else {
 198                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 199                              radeon_cp_vc_frmts[i][1] );
 200                }
 201                break;
 202             default:
 203                continue;
 204             };
 205          }
 206       }
 207    }
 208
 209    if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
 210         fmt_0 != rmesa->swtcl.vertex_format) {
 211       RADEON_NEWPRIM(rmesa);
 212       rmesa->swtcl.vertex_format = fmt_0;
 213       rmesa->radeon.swtcl.vertex_size =
 214           _tnl_install_attrs( ctx,
 215                               rmesa->radeon.swtcl.vertex_attrs,
 216                               rmesa->radeon.swtcl.vertex_attr_count,
 217                               NULL, 0 );
 218       rmesa->radeon.swtcl.vertex_size /= 4;
 219       RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
 220       radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
 221           "%s: vertex_size= %d floats\n",  __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
 222    }
 223 }
 224
 225 static void radeon_predict_emit_size( r100ContextPtr rmesa )
 226 {
 227
 228     if (!rmesa->radeon.swtcl.emit_prediction) {
 229         const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
 230         const int scissor_size = 8;
 231         const int prims_size = 8;
 232         const int vertex_size = 7;
 233
 234         if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
 235                     state_size +
 236                     (scissor_size + prims_size + vertex_size),
 237                     __FUNCTION__))
 238             rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
 239         else
 240             rmesa->radeon.swtcl.emit_prediction = state_size;
 241         rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
 242             + rmesa->radeon.cmdbuf.cs->cdw;
 243     }
 244 }
 245
 246 static void radeonRenderStart( struct gl_context *ctx )
 247 {
 248     r100ContextPtr rmesa = R100_CONTEXT( ctx );
 249
 250     radeonSetVertexFormat( ctx );
 251
 252     if (rmesa->radeon.dma.flush != 0 &&
 253             rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
 254         rmesa->radeon.dma.flush( ctx );
 255 }
 256
 257
 258 /**
 259  * Set vertex state for SW TCL.  The primary purpose of this function is to
 260  * determine in advance whether or not the hardware can / should do the
 261  * projection divide or Mesa should do it.
 262  */
 263 void radeonChooseVertexState( struct gl_context *ctx )
 264 {
 265    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 266    TNLcontext *tnl = TNL_CONTEXT(ctx);
 267
 268    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 269
 270    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 271                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 272                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 273
 274    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 275     * rasterization fallback.  As this function will be called again when we
 276     * leave a rasterization fallback, we can just skip it for now.
 277     */
 278    if (rmesa->radeon.Fallback != 0)
 279       return;
 280
 281    /* HW perspective divide is a win, but tiny vertex formats are a
 282     * bigger one.
 283     */
 284
 285    if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) &&
 286        !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
 287        || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
 288       rmesa->swtcl.needproj = GL_TRUE;
 289       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 290                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 291    }
 292    else {
 293       rmesa->swtcl.needproj = GL_FALSE;
 294       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 295    }
 296
 297    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 298
 299    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 300       RADEON_STATECHANGE( rmesa, set );
 301       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 302    }
 303 }
 304
 305 void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
 306 {
 307    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 308
 309
 310
 311    radeonEmitState(&rmesa->radeon);
 312    radeonEmitVertexAOS( rmesa,
 313                         rmesa->radeon.swtcl.vertex_size,
 314                         rmesa->radeon.swtcl.bo,
 315                         current_offset);
 316
 317
 318    radeonEmitVbufPrim( rmesa,
 319                        rmesa->swtcl.vertex_format,
 320                        rmesa->radeon.swtcl.hw_primitive,
 321                        rmesa->radeon.swtcl.numverts);
 322    if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
 323      WARN_ONCE("Rendering was %d commands larger than predicted size."
 324          " We might overflow  command buffer.\n",
 325          rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
 326
 327
 328    rmesa->radeon.swtcl.emit_prediction = 0;
 329
 330 }
 331
 332 /*
 333  * Render unclipped vertex buffers by emitting vertices directly to
 334  * dma buffers.  Use strip/fan hardware primitives where possible.
 335  * Try to simulate missing primitives with indexed vertices.
 336  */
 337 #define HAVE_POINTS      1
 338 #define HAVE_LINES       1
 339 #define HAVE_LINE_STRIPS 1
 340 #define HAVE_TRIANGLES   1
 341 #define HAVE_TRI_STRIPS  1
 342 #define HAVE_TRI_STRIP_1 0
 343 #define HAVE_TRI_FANS    1
 344 #define HAVE_QUADS       0
 345 #define HAVE_QUAD_STRIPS 0
 346 #define HAVE_POLYGONS    0
 347 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 348 #define HAVE_ELTS        0
 349
 350 static const GLuint hw_prim[GL_POLYGON+1] = {
 351    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 352    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 353    0,
 354    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 355    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 356    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 357    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 358    0,
 359    0,
 360    0
 361 };
 362
 363 static INLINE void
 364 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 365 {
 366    RADEON_NEWPRIM( rmesa );
 367    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
 368    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
 369 }
 370
 371 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
 372 {
 373    void *rv;
 374    do {
 375      radeon_predict_emit_size( rmesa );
 376      rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
 377    } while (!rv);
 378    return rv;
 379 }
 380
 381 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 382 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 383 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 384 #define GET_CURRENT_VB_MAX_VERTS()                                      10\
 385 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
 386 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 387   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
 388 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
 389 #define EMIT_VERTS( ctx, j, nr, buf ) \
 390   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 391
 392 #define TAG(x) radeon_dma_##x
 393 #include "tnl_dd/t_dd_dmatmp.h"
 394
 395
 396 /**********************************************************************/
 397 /*                          Render pipeline stage                     */
 398 /**********************************************************************/
 399
 400
 401 static GLboolean radeon_run_render( struct gl_context *ctx,
 402                                     struct tnl_pipeline_stage *stage )
 403 {
 404    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 405    TNLcontext *tnl = TNL_CONTEXT(ctx);
 406    struct vertex_buffer *VB = &tnl->vb;
 407    tnl_render_func *tab = TAG(render_tab_verts);
 408    GLuint i;
 409
 410    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
 411        !radeon_dma_validate_render( ctx, VB ))
 412       return GL_TRUE;
 413
 414    radeon_prepare_render(&rmesa->radeon);
 415    if (rmesa->radeon.NewGLState)
 416       radeonValidateState( ctx );
 417
 418    tnl->Driver.Render.Start( ctx );
 419
 420    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 421    {
 422       GLuint prim = VB->Primitive[i].mode;
 423       GLuint start = VB->Primitive[i].start;
 424       GLuint length = VB->Primitive[i].count;
 425
 426       if (!length)
 427          continue;
 428
 429       radeon_print(RADEON_SWRENDER, RADEON_NORMAL,
 430           "radeon_render.c: prim %s %d..%d\n",
 431                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 432                  start, start+length);
 433
 434       if (length)
 435          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 436    }
 437
 438    tnl->Driver.Render.Finish( ctx );
 439
 440    return GL_FALSE;             /* finished the pipe */
 441 }
 442
 443
 444
 445 const struct tnl_pipeline_stage _radeon_render_stage =
 446 {
 447    "radeon render",
 448    NULL,
 449    NULL,
 450    NULL,
 451    NULL,
 452    radeon_run_render            /* run */
 453 };
 454
 455
 456 /**************************************************************************/
 457
 458
 459 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 460    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 461    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 462    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 463    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 464    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 465    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 466    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 467    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 468    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 469    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 470 };
 471
 472 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim );
 473 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim );
 474 static void radeonResetLineStipple( struct gl_context *ctx );
 475
 476
 477 /***********************************************************************
 478  *                    Emit primitives as inline vertices               *
 479  ***********************************************************************/
 480
 481 #undef LOCAL_VARS
 482 #undef ALLOC_VERTS
 483 #define CTX_ARG r100ContextPtr rmesa
 484 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
 485 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
 486 #undef LOCAL_VARS
 487 #define LOCAL_VARS                                              \
 488    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 489    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
 490 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 491 #define VERTEX radeonVertex
 492 #undef TAG
 493 #define TAG(x) radeon_##x
 494 #include "tnl_dd/t_dd_triemit.h"
 495
 496
 497 /***********************************************************************
 498  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 499  ***********************************************************************/
 500
 501 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 502 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 503 #define LINE( a, b )       radeon_line( rmesa, a, b )
 504 #define POINT( a )         radeon_point( rmesa, a )
 505
 506 /***********************************************************************
 507  *              Build render functions from dd templates               *
 508  ***********************************************************************/
 509
 510 #define RADEON_TWOSIDE_BIT      0x01
 511 #define RADEON_UNFILLED_BIT     0x02
 512 #define RADEON_MAX_TRIFUNC      0x04
 513
 514
 515 static struct {
 516    tnl_points_func              points;
 517    tnl_line_func                line;
 518    tnl_triangle_func    triangle;
 519    tnl_quad_func                quad;
 520 } rast_tab[RADEON_MAX_TRIFUNC];
 521
 522
 523 #define DO_FALLBACK  0
 524 #define DO_OFFSET    0
 525 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 526 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 527 #define DO_FLAT      0
 528 #define DO_TRI       1
 529 #define DO_QUAD      1
 530 #define DO_LINE      1
 531 #define DO_POINTS    1
 532 #define DO_FULL_QUAD 1
 533
 534 #define HAVE_SPEC   1
 535 #define HAVE_BACK_COLORS  0
 536 #define HAVE_HW_FLATSHADE 1
 537 #define TAB rast_tab
 538
 539 #define DEPTH_SCALE 1.0
 540 #define UNFILLED_TRI unfilled_tri
 541 #define UNFILLED_QUAD unfilled_quad
 542 #define VERT_X(_v) _v->v.x
 543 #define VERT_Y(_v) _v->v.y
 544 #define VERT_Z(_v) _v->v.z
 545 #define AREA_IS_CCW( a ) (a < 0)
 546 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
 547
 548 #define VERT_SET_RGBA( v, c )                                   \
 549 do {                                                            \
 550    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 551    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 552    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 553    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 554    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 555 } while (0)
 556
 557 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 558
 559 #define VERT_SET_SPEC( v, c )                                   \
 560 do {                                                            \
 561    if (specoffset) {                                            \
 562       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 563       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 564       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 565       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 566    }                                                            \
 567 } while (0)
 568 #define VERT_COPY_SPEC( v0, v1 )                        \
 569 do {                                                    \
 570    if (specoffset) {                                    \
 571       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 572       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 573       spec0->red   = spec1->red;        \
 574       spec0->green = spec1->green;      \
 575       spec0->blue  = spec1->blue;       \
 576    }                                                    \
 577 } while (0)
 578
 579 /* These don't need LE32_TO_CPU() as they used to save and restore
 580  * colors which are already in the correct format.
 581  */
 582 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 583 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 584 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 585 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 586
 587 #undef LOCAL_VARS
 588 #undef TAG
 589 #undef INIT
 590
 591 #define LOCAL_VARS(n)                                                   \
 592    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 593    GLuint color[n] = {0}, spec[n] = {0};                                                \
 594    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 595    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 596    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 597
 598 /***********************************************************************
 599  *                Helpers for rendering unfilled primitives            *
 600  ***********************************************************************/
 601
 602 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 603 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
 604 #undef TAG
 605 #define TAG(x) x
 606 #include "tnl_dd/t_dd_unfilled.h"
 607 #undef IND
 608
 609
 610 /***********************************************************************
 611  *                      Generate GL render functions                   *
 612  ***********************************************************************/
 613
 614
 615 #define IND (0)
 616 #define TAG(x) x
 617 #include "tnl_dd/t_dd_tritmp.h"
 618
 619 #define IND (RADEON_TWOSIDE_BIT)
 620 #define TAG(x) x##_twoside
 621 #include "tnl_dd/t_dd_tritmp.h"
 622
 623 #define IND (RADEON_UNFILLED_BIT)
 624 #define TAG(x) x##_unfilled
 625 #include "tnl_dd/t_dd_tritmp.h"
 626
 627 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 628 #define TAG(x) x##_twoside_unfilled
 629 #include "tnl_dd/t_dd_tritmp.h"
 630
 631
 632 static void init_rast_tab( void )
 633 {
 634    init();
 635    init_twoside();
 636    init_unfilled();
 637    init_twoside_unfilled();
 638 }
 639
 640 /**********************************************************************/
 641 /*               Render unclipped begin/end objects                   */
 642 /**********************************************************************/
 643
 644 #define RENDER_POINTS( start, count )           \
 645    for ( ; start < count ; start++)             \
 646       radeon_point( rmesa, VERT(start) )
 647 #define RENDER_LINE( v0, v1 ) \
 648    radeon_line( rmesa, VERT(v0), VERT(v1) )
 649 #define RENDER_TRI( v0, v1, v2 )  \
 650    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 651 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 652    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 653 #undef INIT
 654 #define INIT(x) do {                                    \
 655    radeonRenderPrimitive( ctx, x );                     \
 656 } while (0)
 657 #undef LOCAL_VARS
 658 #define LOCAL_VARS                                              \
 659    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 660    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;             \
 661    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;         \
 662    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 663    const GLboolean stipple = ctx->Line.StippleFlag;             \
 664    (void) elt; (void) stipple;
 665 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 666 #define RESET_OCCLUSION
 667 #define PRESERVE_VB_DEFS
 668 #define ELT(x) (x)
 669 #define TAG(x) radeon_##x##_verts
 670 #include "tnl/t_vb_rendertmp.h"
 671 #undef ELT
 672 #undef TAG
 673 #define TAG(x) radeon_##x##_elts
 674 #define ELT(x) elt[x]
 675 #include "tnl/t_vb_rendertmp.h"
 676
 677
 678
 679 /**********************************************************************/
 680 /*                    Choose render functions                         */
 681 /**********************************************************************/
 682
 683 void radeonChooseRenderState( struct gl_context *ctx )
 684 {
 685    TNLcontext *tnl = TNL_CONTEXT(ctx);
 686    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 687    GLuint index = 0;
 688    GLuint flags = ctx->_TriangleCaps;
 689
 690    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 691       return;
 692
 693    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
 694    if (flags & DD_TRI_UNFILLED)      index |= RADEON_UNFILLED_BIT;
 695
 696    if (index != rmesa->radeon.swtcl.RenderIndex) {
 697       tnl->Driver.Render.Points = rast_tab[index].points;
 698       tnl->Driver.Render.Line = rast_tab[index].line;
 699       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 700       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 701       tnl->Driver.Render.Quad = rast_tab[index].quad;
 702
 703       if (index == 0) {
 704          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 705          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 706          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 707       } else {
 708          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 709          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 710          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 711       }
 712
 713       rmesa->radeon.swtcl.RenderIndex = index;
 714    }
 715 }
 716
 717
 718 /**********************************************************************/
 719 /*                 High level hooks for t_vb_render.c                 */
 720 /**********************************************************************/
 721
 722
 723 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim )
 724 {
 725    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 726
 727    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
 728       RADEON_NEWPRIM( rmesa );
 729       rmesa->radeon.swtcl.hw_primitive = hwprim;
 730    }
 731 }
 732
 733 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim )
 734 {
 735    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 736    rmesa->radeon.swtcl.render_primitive = prim;
 737    if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
 738       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 739 }
 740
 741 static void radeonRenderFinish( struct gl_context *ctx )
 742 {
 743 }
 744
 745 static void radeonResetLineStipple( struct gl_context *ctx )
 746 {
 747    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 748    RADEON_STATECHANGE( rmesa, lin );
 749 }
 750
 751
 752 /**********************************************************************/
 753 /*           Transition to/from hardware rasterization.               */
 754 /**********************************************************************/
 755
 756 static const char * const fallbackStrings[] = {
 757    "Texture mode",
 758    "glDrawBuffer(GL_FRONT_AND_BACK)",
 759    "glEnable(GL_STENCIL) without hw stencil buffer",
 760    "glRenderMode(selection or feedback)",
 761    "glBlendEquation",
 762    "glBlendFunc",
 763    "RADEON_NO_RAST",
 764    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 765 };
 766
 767
 768 static const char *getFallbackString(GLuint bit)
 769 {
 770    int i = 0;
 771    while (bit > 1) {
 772       i++;
 773       bit >>= 1;
 774    }
 775    return fallbackStrings[i];
 776 }
 777
 778
 779 void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode )
 780 {
 781    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 782    TNLcontext *tnl = TNL_CONTEXT(ctx);
 783    GLuint oldfallback = rmesa->radeon.Fallback;
 784
 785    if (mode) {
 786       rmesa->radeon.Fallback |= bit;
 787       if (oldfallback == 0) {
 788          radeon_firevertices(&rmesa->radeon);
 789          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 790          _swsetup_Wakeup( ctx );
 791          rmesa->radeon.swtcl.RenderIndex = ~0;
 792          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 793             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 794                     bit, getFallbackString(bit));
 795          }
 796       }
 797    }
 798    else {
 799       rmesa->radeon.Fallback &= ~bit;
 800       if (oldfallback == bit) {
 801          _swrast_flush( ctx );
 802          tnl->Driver.Render.Start = radeonRenderStart;
 803          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 804          tnl->Driver.Render.Finish = radeonRenderFinish;
 805
 806          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 807          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 808          tnl->Driver.Render.Interp = _tnl_interp;
 809
 810          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 811          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 812          if (rmesa->radeon.TclFallback) {
 813             /* These are already done if rmesa->radeon.TclFallback goes to
 814              * zero above. But not if it doesn't (RADEON_NO_TCL for
 815              * example?)
 816              */
 817             _tnl_invalidate_vertex_state( ctx, ~0 );
 818             _tnl_invalidate_vertices( ctx, ~0 );
 819             RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
 820             radeonChooseVertexState( ctx );
 821             radeonChooseRenderState( ctx );
 822          }
 823          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 824             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 825                     bit, getFallbackString(bit));
 826          }
 827       }
 828    }
 829 }
 830
 831
 832 /**********************************************************************/
 833 /*                            Initialization.                         */
 834 /**********************************************************************/
 835
 836 void radeonInitSwtcl( struct gl_context *ctx )
 837 {
 838    TNLcontext *tnl = TNL_CONTEXT(ctx);
 839    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 840    static int firsttime = 1;
 841
 842    if (firsttime) {
 843       init_rast_tab();
 844       firsttime = 0;
 845    }
 846    rmesa->radeon.swtcl.emit_prediction = 0;
 847
 848    tnl->Driver.Render.Start = radeonRenderStart;
 849    tnl->Driver.Render.Finish = radeonRenderFinish;
 850    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 851    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 852    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 853    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 854    tnl->Driver.Render.Interp = _tnl_interp;
 855
 856    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 857                        RADEON_MAX_TNL_VERTEX_SIZE);
 858
 859    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 860    rmesa->radeon.swtcl.RenderIndex = ~0;
 861    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
 862    rmesa->radeon.swtcl.hw_primitive = 0;
 863 }
 864