src/mesa/drivers/dri/radeon/radeon_tex.c

   1 /*
   2 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   3                      VA Linux Systems Inc., Fremont, California.
   4
   5 All Rights Reserved.
   6
   7 Permission is hereby granted, free of charge, to any person obtaining
   8 a copy of this software and associated documentation files (the
   9 "Software"), to deal in the Software without restriction, including
  10 without limitation the rights to use, copy, modify, merge, publish,
  11 distribute, sublicense, and/or sell copies of the Software, and to
  12 permit persons to whom the Software is furnished to do so, subject to
  13 the following conditions:
  14
  15 The above copyright notice and this permission notice (including the
  16 next paragraph) shall be included in all copies or substantial
  17 portions of the Software.
  18
  19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26 */
  27
  28 /*
  29  * Authors:
  30  *    Gareth Hughes <gareth@valinux.com>
  31  *    Brian Paul <brianp@valinux.com>
  32  */
  33
  34 #include "main/glheader.h"
  35 #include "main/imports.h"
  36 #include "main/colormac.h"
  37 #include "main/context.h"
  38 #include "main/enums.h"
  39 #include "main/image.h"
  40 #include "main/simple_list.h"
  41 #include "main/texstore.h"
  42 #include "main/teximage.h"
  43 #include "main/texobj.h"
  44
  45 #include "radeon_context.h"
  46 #include "radeon_mipmap_tree.h"
  47 #include "radeon_ioctl.h"
  48 #include "radeon_tex.h"
  49
  50 #include "xmlpool.h"
  51
  52
  53
  54 /**
  55  * Set the texture wrap modes.
  56  *
  57  * \param t Texture object whose wrap modes are to be set
  58  * \param swrap Wrap mode for the \a s texture coordinate
  59  * \param twrap Wrap mode for the \a t texture coordinate
  60  */
  61
  62 static void radeonSetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap )
  63 {
  64    GLboolean  is_clamp = GL_FALSE;
  65    GLboolean  is_clamp_to_border = GL_FALSE;
  66
  67    t->pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK | RADEON_BORDER_MODE_D3D);
  68
  69    switch ( swrap ) {
  70    case GL_REPEAT:
  71       t->pp_txfilter |= RADEON_CLAMP_S_WRAP;
  72       break;
  73    case GL_CLAMP:
  74       t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL;
  75       is_clamp = GL_TRUE;
  76       break;
  77    case GL_CLAMP_TO_EDGE:
  78       t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_LAST;
  79       break;
  80    case GL_CLAMP_TO_BORDER:
  81       t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL;
  82       is_clamp_to_border = GL_TRUE;
  83       break;
  84    case GL_MIRRORED_REPEAT:
  85       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR;
  86       break;
  87    case GL_MIRROR_CLAMP_EXT:
  88       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL;
  89       is_clamp = GL_TRUE;
  90       break;
  91    case GL_MIRROR_CLAMP_TO_EDGE_EXT:
  92       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_LAST;
  93       break;
  94    case GL_MIRROR_CLAMP_TO_BORDER_EXT:
  95       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL;
  96       is_clamp_to_border = GL_TRUE;
  97       break;
  98    default:
  99       _mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__);
 100    }
 101
 102    switch ( twrap ) {
 103    case GL_REPEAT:
 104       t->pp_txfilter |= RADEON_CLAMP_T_WRAP;
 105       break;
 106    case GL_CLAMP:
 107       t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL;
 108       is_clamp = GL_TRUE;
 109       break;
 110    case GL_CLAMP_TO_EDGE:
 111       t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_LAST;
 112       break;
 113    case GL_CLAMP_TO_BORDER:
 114       t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL;
 115       is_clamp_to_border = GL_TRUE;
 116       break;
 117    case GL_MIRRORED_REPEAT:
 118       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR;
 119       break;
 120    case GL_MIRROR_CLAMP_EXT:
 121       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL;
 122       is_clamp = GL_TRUE;
 123       break;
 124    case GL_MIRROR_CLAMP_TO_EDGE_EXT:
 125       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_LAST;
 126       break;
 127    case GL_MIRROR_CLAMP_TO_BORDER_EXT:
 128       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL;
 129       is_clamp_to_border = GL_TRUE;
 130       break;
 131    default:
 132       _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__);
 133    }
 134
 135    if ( is_clamp_to_border ) {
 136       t->pp_txfilter |= RADEON_BORDER_MODE_D3D;
 137    }
 138
 139    t->border_fallback = (is_clamp && is_clamp_to_border);
 140 }
 141
 142 static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max )
 143 {
 144    t->pp_txfilter &= ~RADEON_MAX_ANISO_MASK;
 145
 146    if ( max == 1.0 ) {
 147       t->pp_txfilter |= RADEON_MAX_ANISO_1_TO_1;
 148    } else if ( max <= 2.0 ) {
 149       t->pp_txfilter |= RADEON_MAX_ANISO_2_TO_1;
 150    } else if ( max <= 4.0 ) {
 151       t->pp_txfilter |= RADEON_MAX_ANISO_4_TO_1;
 152    } else if ( max <= 8.0 ) {
 153       t->pp_txfilter |= RADEON_MAX_ANISO_8_TO_1;
 154    } else {
 155       t->pp_txfilter |= RADEON_MAX_ANISO_16_TO_1;
 156    }
 157 }
 158
 159 /**
 160  * Set the texture magnification and minification modes.
 161  *
 162  * \param t Texture whose filter modes are to be set
 163  * \param minf Texture minification mode
 164  * \param magf Texture magnification mode
 165  */
 166
 167 static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf )
 168 {
 169    GLuint anisotropy = (t->pp_txfilter & RADEON_MAX_ANISO_MASK);
 170
 171    /* Force revalidation to account for switches from/to mipmapping. */
 172    t->validated = GL_FALSE;
 173
 174    t->pp_txfilter &= ~(RADEON_MIN_FILTER_MASK | RADEON_MAG_FILTER_MASK);
 175
 176    /* r100 chips can't handle mipmaps/aniso for cubemap/volume textures */
 177    if ( t->base.Target == GL_TEXTURE_CUBE_MAP ) {
 178       switch ( minf ) {
 179       case GL_NEAREST:
 180       case GL_NEAREST_MIPMAP_NEAREST:
 181       case GL_NEAREST_MIPMAP_LINEAR:
 182          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST;
 183          break;
 184       case GL_LINEAR:
 185       case GL_LINEAR_MIPMAP_NEAREST:
 186       case GL_LINEAR_MIPMAP_LINEAR:
 187          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR;
 188          break;
 189       default:
 190          break;
 191       }
 192    }
 193    else if ( anisotropy == RADEON_MAX_ANISO_1_TO_1 ) {
 194       switch ( minf ) {
 195       case GL_NEAREST:
 196          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST;
 197          break;
 198       case GL_LINEAR:
 199          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR;
 200          break;
 201       case GL_NEAREST_MIPMAP_NEAREST:
 202          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_NEAREST;
 203          break;
 204       case GL_NEAREST_MIPMAP_LINEAR:
 205          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_NEAREST;
 206          break;
 207       case GL_LINEAR_MIPMAP_NEAREST:
 208          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_LINEAR;
 209          break;
 210       case GL_LINEAR_MIPMAP_LINEAR:
 211          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_LINEAR;
 212          break;
 213       }
 214    } else {
 215       switch ( minf ) {
 216       case GL_NEAREST:
 217          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST;
 218          break;
 219       case GL_LINEAR:
 220          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_LINEAR;
 221          break;
 222       case GL_NEAREST_MIPMAP_NEAREST:
 223       case GL_LINEAR_MIPMAP_NEAREST:
 224          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST;
 225          break;
 226       case GL_NEAREST_MIPMAP_LINEAR:
 227       case GL_LINEAR_MIPMAP_LINEAR:
 228          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR;
 229          break;
 230       }
 231    }
 232
 233    switch ( magf ) {
 234    case GL_NEAREST:
 235       t->pp_txfilter |= RADEON_MAG_FILTER_NEAREST;
 236       break;
 237    case GL_LINEAR:
 238       t->pp_txfilter |= RADEON_MAG_FILTER_LINEAR;
 239       break;
 240    }
 241 }
 242
 243 static void radeonSetTexBorderColor( radeonTexObjPtr t, const GLfloat color[4] )
 244 {
 245    GLubyte c[4];
 246    CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]);
 247    CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
 248    CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
 249    CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
 250    t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
 251 }
 252
 253 #define SCALED_FLOAT_TO_BYTE( x, scale ) \
 254                 (((GLuint)((255.0F / scale) * (x))) / 2)
 255
 256 static void radeonTexEnv( struct gl_context *ctx, GLenum target,
 257                           GLenum pname, const GLfloat *param )
 258 {
 259    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 260    GLuint unit = ctx->Texture.CurrentUnit;
 261    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
 262
 263    if ( RADEON_DEBUG & RADEON_STATE ) {
 264       fprintf( stderr, "%s( %s )\n",
 265                __FUNCTION__, _mesa_lookup_enum_by_nr( pname ) );
 266    }
 267
 268    switch ( pname ) {
 269    case GL_TEXTURE_ENV_COLOR: {
 270       GLubyte c[4];
 271       GLuint envColor;
 272       UNCLAMPED_FLOAT_TO_RGBA_CHAN( c, texUnit->EnvColor );
 273       envColor = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
 274       if ( rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] != envColor ) {
 275          RADEON_STATECHANGE( rmesa, tex[unit] );
 276          rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] = envColor;
 277       }
 278       break;
 279    }
 280
 281    case GL_TEXTURE_LOD_BIAS_EXT: {
 282       GLfloat bias, min;
 283       GLuint b;
 284
 285       /* The Radeon's LOD bias is a signed 2's complement value with a
 286        * range of -1.0 <= bias < 4.0.  We break this into two linear
 287        * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping
 288        * [0.0,4.0] to [0,127].
 289        */
 290       min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ?
 291           0.0 : -1.0;
 292       bias = CLAMP( *param, min, 4.0 );
 293       if ( bias == 0 ) {
 294          b = 0;
 295       } else if ( bias > 0 ) {
 296          b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 4.0 )) << RADEON_LOD_BIAS_SHIFT;
 297       } else {
 298          b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 1.0 )) << RADEON_LOD_BIAS_SHIFT;
 299       }
 300       if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] & RADEON_LOD_BIAS_MASK) != b ) {
 301          RADEON_STATECHANGE( rmesa, tex[unit] );
 302          rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] &= ~RADEON_LOD_BIAS_MASK;
 303          rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] |= (b & RADEON_LOD_BIAS_MASK);
 304       }
 305       break;
 306    }
 307
 308    default:
 309       return;
 310    }
 311 }
 312
 313
 314 /**
 315  * Changes variables and flags for a state update, which will happen at the
 316  * next UpdateTextureState
 317  */
 318
 319 static void radeonTexParameter( struct gl_context *ctx, GLenum target,
 320                                 struct gl_texture_object *texObj,
 321                                 GLenum pname, const GLfloat *params )
 322 {
 323    radeonTexObj* t = radeon_tex_obj(texObj);
 324
 325    radeon_print(RADEON_TEXTURE, RADEON_VERBOSE, "%s( %s )\n", __FUNCTION__,
 326                _mesa_lookup_enum_by_nr( pname ) );
 327
 328    switch ( pname ) {
 329    case GL_TEXTURE_MIN_FILTER:
 330    case GL_TEXTURE_MAG_FILTER:
 331    case GL_TEXTURE_MAX_ANISOTROPY_EXT:
 332       radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
 333       radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
 334       break;
 335
 336    case GL_TEXTURE_WRAP_S:
 337    case GL_TEXTURE_WRAP_T:
 338       radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT );
 339       break;
 340
 341    case GL_TEXTURE_BORDER_COLOR:
 342       radeonSetTexBorderColor( t, texObj->BorderColor.f );
 343       break;
 344
 345    case GL_TEXTURE_BASE_LEVEL:
 346    case GL_TEXTURE_MAX_LEVEL:
 347    case GL_TEXTURE_MIN_LOD:
 348    case GL_TEXTURE_MAX_LOD:
 349       t->validated = GL_FALSE;
 350       break;
 351
 352    default:
 353       return;
 354    }
 355 }
 356
 357 static void radeonDeleteTexture( struct gl_context *ctx,
 358                                  struct gl_texture_object *texObj )
 359 {
 360    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 361    radeonTexObj* t = radeon_tex_obj(texObj);
 362    int i;
 363
 364    radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
 365          "%s( %p (target = %s) )\n", __FUNCTION__, (void *)texObj,
 366                _mesa_lookup_enum_by_nr( texObj->Target ) );
 367
 368    if ( rmesa ) {
 369      radeon_firevertices(&rmesa->radeon);
 370      for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) {
 371        if ( t == rmesa->state.texture.unit[i].texobj ) {
 372          rmesa->state.texture.unit[i].texobj = NULL;
 373          rmesa->hw.tex[i].dirty = GL_FALSE;
 374          rmesa->hw.cube[i].dirty = GL_FALSE;
 375        }
 376      }
 377    }
 378
 379    radeon_miptree_unreference(&t->mt);
 380
 381    /* Free mipmap images and the texture object itself */
 382    _mesa_delete_texture_object(ctx, texObj);
 383 }
 384
 385 /* Need:
 386  *  - Same GEN_MODE for all active bits
 387  *  - Same EyePlane/ObjPlane for all active bits when using Eye/Obj
 388  *  - STRQ presumably all supported (matrix means incoming R values
 389  *    can end up in STQ, this has implications for vertex support,
 390  *    presumably ok if maos is used, though?)
 391  *
 392  * Basically impossible to do this on the fly - just collect some
 393  * basic info & do the checks from ValidateState().
 394  */
 395 static void radeonTexGen( struct gl_context *ctx,
 396                           GLenum coord,
 397                           GLenum pname,
 398                           const GLfloat *params )
 399 {
 400    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 401    GLuint unit = ctx->Texture.CurrentUnit;
 402    rmesa->recheck_texgen[unit] = GL_TRUE;
 403 }
 404
 405 /**
 406  * Allocate a new texture object.
 407  * Called via ctx->Driver.NewTextureObject.
 408  * Note: we could use containment here to 'derive' the driver-specific
 409  * texture object from the core mesa gl_texture_object.  Not done at this time.
 410  */
 411 static struct gl_texture_object *
 412 radeonNewTextureObject( struct gl_context *ctx, GLuint name, GLenum target )
 413 {
 414    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 415    radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
 416
 417    _mesa_initialize_texture_object(&t->base, name, target);
 418    t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
 419
 420    t->border_fallback = GL_FALSE;
 421
 422    t->pp_txfilter = RADEON_BORDER_MODE_OGL;
 423    t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
 424                      RADEON_TXFORMAT_PERSPECTIVE_ENABLE);
 425
 426    radeonSetTexWrap( t, t->base.WrapS, t->base.WrapT );
 427    radeonSetTexMaxAnisotropy( t, t->base.MaxAnisotropy );
 428    radeonSetTexFilter( t, t->base.MinFilter, t->base.MagFilter );
 429    radeonSetTexBorderColor( t, t->base.BorderColor.f );
 430    return &t->base;
 431 }
 432
 433
 434
 435 void radeonInitTextureFuncs( radeonContextPtr radeon, struct dd_function_table *functions )
 436 {
 437    functions->ChooseTextureFormat       = radeonChooseTextureFormat_mesa;
 438    functions->TexImage1D                = radeonTexImage1D;
 439    functions->TexImage2D                = radeonTexImage2D;
 440    functions->TexSubImage1D             = radeonTexSubImage1D;
 441    functions->TexSubImage2D             = radeonTexSubImage2D;
 442    functions->GetTexImage               = radeonGetTexImage;
 443    functions->GetCompressedTexImage     = radeonGetCompressedTexImage;
 444
 445    functions->NewTextureObject          = radeonNewTextureObject;
 446    //   functions->BindTexture          = radeonBindTexture;
 447    functions->DeleteTexture             = radeonDeleteTexture;
 448
 449    functions->TexEnv                    = radeonTexEnv;
 450    functions->TexParameter              = radeonTexParameter;
 451    functions->TexGen                    = radeonTexGen;
 452
 453    functions->CompressedTexImage2D      = radeonCompressedTexImage2D;
 454    functions->CompressedTexSubImage2D   = radeonCompressedTexSubImage2D;
 455
 456    if (radeon->radeonScreen->kernel_mm) {
 457       functions->CopyTexImage2D = radeonCopyTexImage2D;
 458       functions->CopyTexSubImage2D = radeonCopyTexSubImage2D;
 459    }
 460
 461    functions->GenerateMipmap = radeonGenerateMipmap;
 462
 463    functions->NewTextureImage = radeonNewTextureImage;
 464    functions->FreeTexImageData = radeonFreeTexImageData;
 465    functions->MapTexture = radeonMapTexture;
 466    functions->UnmapTexture = radeonUnmapTexture;
 467
 468 #if FEATURE_OES_EGL_image
 469    functions->EGLImageTargetTexture2D = radeon_image_target_texture_2d;
 470 #endif
 471
 472    driInitTextureFormats();
 473 }