1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
36 #include "main/glheader.h"
37 #include "util/imports.h"
38 #include "main/context.h"
39 #include "main/macros.h"
40 #include "main/teximage.h"
41 #include "main/texstate.h"
42 #include "main/texobj.h"
43 #include "main/enums.h"
44 #include "main/samplerobj.h"
46 #include "radeon_context.h"
47 #include "radeon_mipmap_tree.h"
48 #include "radeon_state.h"
49 #include "radeon_ioctl.h"
50 #include "radeon_swtcl.h"
51 #include "radeon_tex.h"
52 #include "radeon_tcl.h"
55 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
56 && (tx_table[f].format != 0xffffffff) )
58 /* ================================================================
59 * Texture combine functions
62 /* GL_ARB_texture_env_combine support
65 /* The color tables have combine functions for GL_SRC_COLOR,
66 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
68 static GLuint radeon_texture_color
[][RADEON_MAX_TEXTURE_UNITS
] =
71 RADEON_COLOR_ARG_A_T0_COLOR
,
72 RADEON_COLOR_ARG_A_T1_COLOR
,
73 RADEON_COLOR_ARG_A_T2_COLOR
76 RADEON_COLOR_ARG_A_T0_COLOR
| RADEON_COMP_ARG_A
,
77 RADEON_COLOR_ARG_A_T1_COLOR
| RADEON_COMP_ARG_A
,
78 RADEON_COLOR_ARG_A_T2_COLOR
| RADEON_COMP_ARG_A
81 RADEON_COLOR_ARG_A_T0_ALPHA
,
82 RADEON_COLOR_ARG_A_T1_ALPHA
,
83 RADEON_COLOR_ARG_A_T2_ALPHA
86 RADEON_COLOR_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
87 RADEON_COLOR_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
88 RADEON_COLOR_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
92 static GLuint radeon_tfactor_color
[] =
94 RADEON_COLOR_ARG_A_TFACTOR_COLOR
,
95 RADEON_COLOR_ARG_A_TFACTOR_COLOR
| RADEON_COMP_ARG_A
,
96 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
,
97 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
100 static GLuint radeon_primary_color
[] =
102 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
,
103 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
| RADEON_COMP_ARG_A
,
104 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
,
105 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
108 static GLuint radeon_previous_color
[] =
110 RADEON_COLOR_ARG_A_CURRENT_COLOR
,
111 RADEON_COLOR_ARG_A_CURRENT_COLOR
| RADEON_COMP_ARG_A
,
112 RADEON_COLOR_ARG_A_CURRENT_ALPHA
,
113 RADEON_COLOR_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
116 /* GL_ZERO table - indices 0-3
117 * GL_ONE table - indices 1-4
119 static GLuint radeon_zero_color
[] =
121 RADEON_COLOR_ARG_A_ZERO
,
122 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
123 RADEON_COLOR_ARG_A_ZERO
,
124 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
125 RADEON_COLOR_ARG_A_ZERO
129 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
131 static GLuint radeon_texture_alpha
[][RADEON_MAX_TEXTURE_UNITS
] =
134 RADEON_ALPHA_ARG_A_T0_ALPHA
,
135 RADEON_ALPHA_ARG_A_T1_ALPHA
,
136 RADEON_ALPHA_ARG_A_T2_ALPHA
139 RADEON_ALPHA_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
140 RADEON_ALPHA_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
141 RADEON_ALPHA_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
145 static GLuint radeon_tfactor_alpha
[] =
147 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
,
148 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
151 static GLuint radeon_primary_alpha
[] =
153 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
,
154 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
157 static GLuint radeon_previous_alpha
[] =
159 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
,
160 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
163 /* GL_ZERO table - indices 0-1
164 * GL_ONE table - indices 1-2
166 static GLuint radeon_zero_alpha
[] =
168 RADEON_ALPHA_ARG_A_ZERO
,
169 RADEON_ALPHA_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
170 RADEON_ALPHA_ARG_A_ZERO
174 /* Extract the arg from slot A, shift it into the correct argument slot
175 * and set the corresponding complement bit.
177 #define RADEON_COLOR_ARG( n, arg ) \
180 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
181 << RADEON_COLOR_ARG_##arg##_SHIFT); \
183 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
184 << RADEON_COMP_ARG_##arg##_SHIFT); \
187 #define RADEON_ALPHA_ARG( n, arg ) \
190 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
191 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
193 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
194 << RADEON_COMP_ARG_##arg##_SHIFT); \
198 /* ================================================================
199 * Texture unit state management
203 texture_base_format(const struct gl_texture_object
*t
)
205 return t
->Image
[0][t
->BaseLevel
]->_BaseFormat
;
208 static GLboolean
radeonUpdateTextureEnv( struct gl_context
*ctx
, int unit
)
210 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
211 const struct gl_texture_unit
*rtexUnit
= &ctx
->Texture
.Unit
[unit
];
212 const struct gl_fixedfunc_texture_unit
*texUnit
=
213 &ctx
->Texture
.FixedFuncUnit
[unit
];
214 GLuint color_combine
, alpha_combine
;
215 const GLuint color_combine0
= RADEON_COLOR_ARG_A_ZERO
| RADEON_COLOR_ARG_B_ZERO
216 | RADEON_COLOR_ARG_C_CURRENT_COLOR
| RADEON_BLEND_CTL_ADD
217 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
218 const GLuint alpha_combine0
= RADEON_ALPHA_ARG_A_ZERO
| RADEON_ALPHA_ARG_B_ZERO
219 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA
| RADEON_BLEND_CTL_ADD
220 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
223 if ( RADEON_DEBUG
& RADEON_TEXTURE
) {
224 fprintf( stderr
, "%s( %p, %d )\n", __func__
, (void *)ctx
, unit
);
227 /* Set the texture environment state. Isn't this nice and clean?
228 * The chip will automagically set the texture alpha to 0xff when
229 * the texture format does not include an alpha component. This
230 * reduces the amount of special-casing we have to do, alpha-only
231 * textures being a notable exception. Doesn't work for luminance
232 * textures realized with I8 and ALPHA_IN_MAP not set neither (on r100).
234 /* Don't cache these results.
236 rmesa
->state
.texture
.unit
[unit
].format
= 0;
237 rmesa
->state
.texture
.unit
[unit
].envMode
= 0;
239 if ( !rtexUnit
->_Current
) {
240 color_combine
= color_combine0
;
241 alpha_combine
= alpha_combine0
;
244 GLuint color_arg
[3], alpha_arg
[3];
246 const GLuint numColorArgs
= texUnit
->_CurrentCombine
->_NumArgsRGB
;
247 const GLuint numAlphaArgs
= texUnit
->_CurrentCombine
->_NumArgsA
;
248 GLuint RGBshift
= texUnit
->_CurrentCombine
->ScaleShiftRGB
;
249 GLuint Ashift
= texUnit
->_CurrentCombine
->ScaleShiftA
;
253 * Extract the color and alpha combine function arguments.
255 for ( i
= 0 ; i
< numColorArgs
; i
++ ) {
256 const GLint op
= texUnit
->_CurrentCombine
->OperandRGB
[i
] - GL_SRC_COLOR
;
257 const GLuint srcRGBi
= texUnit
->_CurrentCombine
->SourceRGB
[i
];
262 if (texture_base_format(rtexUnit
->_Current
) == GL_ALPHA
)
263 color_arg
[i
] = radeon_zero_color
[op
];
265 color_arg
[i
] = radeon_texture_color
[op
][unit
];
268 color_arg
[i
] = radeon_tfactor_color
[op
];
270 case GL_PRIMARY_COLOR
:
271 color_arg
[i
] = radeon_primary_color
[op
];
274 color_arg
[i
] = radeon_previous_color
[op
];
277 color_arg
[i
] = radeon_zero_color
[op
];
280 color_arg
[i
] = radeon_zero_color
[op
+1];
285 GLuint txunit
= srcRGBi
- GL_TEXTURE0
;
286 if (texture_base_format(ctx
->Texture
.Unit
[txunit
]._Current
) == GL_ALPHA
)
287 color_arg
[i
] = radeon_zero_color
[op
];
289 /* implement ogl 1.4/1.5 core spec here, not specification of
290 * GL_ARB_texture_env_crossbar (which would require disabling blending
291 * instead of undefined results when referencing not enabled texunit) */
292 color_arg
[i
] = radeon_texture_color
[op
][txunit
];
300 for ( i
= 0 ; i
< numAlphaArgs
; i
++ ) {
301 const GLint op
= texUnit
->_CurrentCombine
->OperandA
[i
] - GL_SRC_ALPHA
;
302 const GLuint srcAi
= texUnit
->_CurrentCombine
->SourceA
[i
];
307 if (texture_base_format(rtexUnit
->_Current
) == GL_LUMINANCE
)
308 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
310 alpha_arg
[i
] = radeon_texture_alpha
[op
][unit
];
313 alpha_arg
[i
] = radeon_tfactor_alpha
[op
];
315 case GL_PRIMARY_COLOR
:
316 alpha_arg
[i
] = radeon_primary_alpha
[op
];
319 alpha_arg
[i
] = radeon_previous_alpha
[op
];
322 alpha_arg
[i
] = radeon_zero_alpha
[op
];
325 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
330 GLuint txunit
= srcAi
- GL_TEXTURE0
;
331 if (texture_base_format(ctx
->Texture
.Unit
[txunit
]._Current
) == GL_LUMINANCE
)
332 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
334 alpha_arg
[i
] = radeon_texture_alpha
[op
][txunit
];
343 * Build up the color and alpha combine functions.
345 switch ( texUnit
->_CurrentCombine
->ModeRGB
) {
347 color_combine
= (RADEON_COLOR_ARG_A_ZERO
|
348 RADEON_COLOR_ARG_B_ZERO
|
349 RADEON_BLEND_CTL_ADD
|
351 RADEON_COLOR_ARG( 0, C
);
354 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
355 RADEON_BLEND_CTL_ADD
|
357 RADEON_COLOR_ARG( 0, A
);
358 RADEON_COLOR_ARG( 1, B
);
361 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
363 RADEON_BLEND_CTL_ADD
|
365 RADEON_COLOR_ARG( 0, A
);
366 RADEON_COLOR_ARG( 1, C
);
369 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
371 RADEON_BLEND_CTL_ADDSIGNED
|
373 RADEON_COLOR_ARG( 0, A
);
374 RADEON_COLOR_ARG( 1, C
);
377 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
379 RADEON_BLEND_CTL_SUBTRACT
|
381 RADEON_COLOR_ARG( 0, A
);
382 RADEON_COLOR_ARG( 1, C
);
385 color_combine
= (RADEON_BLEND_CTL_BLEND
|
387 RADEON_COLOR_ARG( 0, B
);
388 RADEON_COLOR_ARG( 1, A
);
389 RADEON_COLOR_ARG( 2, C
);
392 case GL_DOT3_RGB_EXT
:
393 case GL_DOT3_RGBA_EXT
:
394 /* The EXT version of the DOT3 extension does not support the
395 * scale factor, but the ARB version (and the version in OpenGL
403 /* The R100 / RV200 only support a 1X multiplier in hardware
406 if ( RGBshift
!= (RADEON_SCALE_1X
>> RADEON_SCALE_SHIFT
) ) {
411 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA_EXT
)
412 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA
) ) {
413 /* is it necessary to set this or will it be ignored anyway? */
417 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
418 RADEON_BLEND_CTL_DOT3
|
420 RADEON_COLOR_ARG( 0, A
);
421 RADEON_COLOR_ARG( 1, B
);
424 case GL_MODULATE_ADD_ATI
:
425 color_combine
= (RADEON_BLEND_CTL_ADD
|
427 RADEON_COLOR_ARG( 0, A
);
428 RADEON_COLOR_ARG( 1, C
);
429 RADEON_COLOR_ARG( 2, B
);
431 case GL_MODULATE_SIGNED_ADD_ATI
:
432 color_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
434 RADEON_COLOR_ARG( 0, A
);
435 RADEON_COLOR_ARG( 1, C
);
436 RADEON_COLOR_ARG( 2, B
);
438 case GL_MODULATE_SUBTRACT_ATI
:
439 color_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
441 RADEON_COLOR_ARG( 0, A
);
442 RADEON_COLOR_ARG( 1, C
);
443 RADEON_COLOR_ARG( 2, B
);
449 switch ( texUnit
->_CurrentCombine
->ModeA
) {
451 alpha_combine
= (RADEON_ALPHA_ARG_A_ZERO
|
452 RADEON_ALPHA_ARG_B_ZERO
|
453 RADEON_BLEND_CTL_ADD
|
455 RADEON_ALPHA_ARG( 0, C
);
458 alpha_combine
= (RADEON_ALPHA_ARG_C_ZERO
|
459 RADEON_BLEND_CTL_ADD
|
461 RADEON_ALPHA_ARG( 0, A
);
462 RADEON_ALPHA_ARG( 1, B
);
465 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
467 RADEON_BLEND_CTL_ADD
|
469 RADEON_ALPHA_ARG( 0, A
);
470 RADEON_ALPHA_ARG( 1, C
);
473 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
475 RADEON_BLEND_CTL_ADDSIGNED
|
477 RADEON_ALPHA_ARG( 0, A
);
478 RADEON_ALPHA_ARG( 1, C
);
481 alpha_combine
= (RADEON_COLOR_ARG_B_ZERO
|
483 RADEON_BLEND_CTL_SUBTRACT
|
485 RADEON_ALPHA_ARG( 0, A
);
486 RADEON_ALPHA_ARG( 1, C
);
489 alpha_combine
= (RADEON_BLEND_CTL_BLEND
|
491 RADEON_ALPHA_ARG( 0, B
);
492 RADEON_ALPHA_ARG( 1, A
);
493 RADEON_ALPHA_ARG( 2, C
);
496 case GL_MODULATE_ADD_ATI
:
497 alpha_combine
= (RADEON_BLEND_CTL_ADD
|
499 RADEON_ALPHA_ARG( 0, A
);
500 RADEON_ALPHA_ARG( 1, C
);
501 RADEON_ALPHA_ARG( 2, B
);
503 case GL_MODULATE_SIGNED_ADD_ATI
:
504 alpha_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
506 RADEON_ALPHA_ARG( 0, A
);
507 RADEON_ALPHA_ARG( 1, C
);
508 RADEON_ALPHA_ARG( 2, B
);
510 case GL_MODULATE_SUBTRACT_ATI
:
511 alpha_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
513 RADEON_ALPHA_ARG( 0, A
);
514 RADEON_ALPHA_ARG( 1, C
);
515 RADEON_ALPHA_ARG( 2, B
);
521 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB_EXT
)
522 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB
) ) {
523 alpha_combine
|= RADEON_DOT_ALPHA_DONT_REPLICATE
;
527 * Apply the scale factor.
529 color_combine
|= (RGBshift
<< RADEON_SCALE_SHIFT
);
530 alpha_combine
|= (Ashift
<< RADEON_SCALE_SHIFT
);
536 if ( rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] != color_combine
||
537 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] != alpha_combine
) {
538 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
539 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] = color_combine
;
540 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] = alpha_combine
;
546 void radeonSetTexBuffer2(__DRIcontext
*pDRICtx
, GLint target
, GLint texture_format
,
547 __DRIdrawable
*dPriv
)
549 struct gl_texture_object
*texObj
;
550 struct gl_texture_image
*texImage
;
551 struct radeon_renderbuffer
*rb
;
552 radeon_texture_image
*rImage
;
553 radeonContextPtr radeon
;
554 struct radeon_framebuffer
*rfb
;
557 mesa_format texFormat
;
559 radeon
= pDRICtx
->driverPrivate
;
561 rfb
= dPriv
->driverPrivate
;
562 texObj
= _mesa_get_current_tex_object(&radeon
->glCtx
, target
);
563 texImage
= _mesa_get_tex_image(&radeon
->glCtx
, texObj
, target
, 0);
565 rImage
= get_radeon_texture_image(texImage
);
566 t
= radeon_tex_obj(texObj
);
571 radeon_update_renderbuffers(pDRICtx
, dPriv
, GL_TRUE
);
572 rb
= rfb
->color_rb
[0];
573 if (rb
->bo
== NULL
) {
574 /* Failed to BO for the buffer */
578 _mesa_lock_texture(&radeon
->glCtx
, texObj
);
580 radeon_bo_unref(t
->bo
);
584 radeon_bo_unref(rImage
->bo
);
588 radeon_miptree_unreference(&t
->mt
);
589 radeon_miptree_unreference(&rImage
->mt
);
592 radeon_bo_ref(rImage
->bo
);
594 radeon_bo_ref(t
->bo
);
596 t
->image_override
= GL_TRUE
;
597 t
->override_offset
= 0;
600 if (texture_format
== __DRI_TEXTURE_FORMAT_RGB
)
601 texFormat
= MESA_FORMAT_BGR_UNORM8
;
603 texFormat
= MESA_FORMAT_B8G8R8A8_UNORM
;
607 texFormat
= MESA_FORMAT_BGR_UNORM8
;
610 texFormat
= MESA_FORMAT_B5G6R5_UNORM
;
614 t
->pp_txformat
= tx_table
[texFormat
].format
;
615 t
->pp_txfilter
|= tx_table
[texFormat
].filter
;
617 _mesa_init_teximage_fields(&radeon
->glCtx
, texImage
,
618 rb
->base
.Base
.Width
, rb
->base
.Base
.Height
,
621 rImage
->base
.RowStride
= rb
->pitch
/ rb
->cpp
;
623 t
->pp_txpitch
&= (1 << 13) -1;
624 pitch_val
= rb
->pitch
;
626 t
->pp_txsize
= ((rb
->base
.Base
.Width
- 1) << RADEON_TEX_USIZE_SHIFT
)
627 | ((rb
->base
.Base
.Height
- 1) << RADEON_TEX_VSIZE_SHIFT
);
628 if (target
== GL_TEXTURE_RECTANGLE_NV
) {
629 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
630 t
->pp_txpitch
= pitch_val
;
633 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
634 RADEON_TXFORMAT_HEIGHT_MASK
|
635 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
636 RADEON_TXFORMAT_F5_WIDTH_MASK
|
637 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
638 t
->pp_txformat
|= ((texImage
->WidthLog2
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
639 (texImage
->HeightLog2
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
641 t
->validated
= GL_TRUE
;
642 _mesa_unlock_texture(&radeon
->glCtx
, texObj
);
647 void radeonSetTexBuffer(__DRIcontext
*pDRICtx
, GLint target
, __DRIdrawable
*dPriv
)
649 radeonSetTexBuffer2(pDRICtx
, target
, __DRI_TEXTURE_FORMAT_RGBA
, dPriv
);
653 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
654 RADEON_MIN_FILTER_MASK | \
655 RADEON_MAG_FILTER_MASK | \
656 RADEON_MAX_ANISO_MASK | \
657 RADEON_YUV_TO_RGB | \
658 RADEON_YUV_TEMPERATURE_MASK | \
659 RADEON_CLAMP_S_MASK | \
660 RADEON_CLAMP_T_MASK | \
661 RADEON_BORDER_MODE_D3D )
663 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
664 RADEON_TXFORMAT_HEIGHT_MASK | \
665 RADEON_TXFORMAT_FORMAT_MASK | \
666 RADEON_TXFORMAT_F5_WIDTH_MASK | \
667 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
668 RADEON_TXFORMAT_ALPHA_IN_MAP | \
669 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
670 RADEON_TXFORMAT_NON_POWER2)
673 static void disable_tex_obj_state( r100ContextPtr rmesa
,
676 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
678 RADEON_STATECHANGE( rmesa
, tcl
);
679 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~(RADEON_ST_BIT(unit
) |
682 if (rmesa
->radeon
.TclFallback
& (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
)) {
683 TCL_FALLBACK( &rmesa
->radeon
.glCtx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), GL_FALSE
);
684 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
687 if (rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE
) {
688 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
689 cubic_map bit on unit 2 when the unit is disabled, otherwise every
690 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other
691 units, better be safe than sorry though).*/
692 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
693 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE
;
697 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
698 GLuint tmp
= rmesa
->TexGenEnabled
;
700 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<<unit
);
701 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<<unit
);
702 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<<inputshift
);
703 rmesa
->TexGenNeedNormals
[unit
] = 0;
704 rmesa
->TexGenEnabled
|=
705 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+unit
) << inputshift
;
707 if (tmp
!= rmesa
->TexGenEnabled
) {
708 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
709 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
714 static void import_tex_obj_state( r100ContextPtr rmesa
,
716 radeonTexObjPtr texobj
)
718 /* do not use RADEON_DB_STATE to avoid stale texture caches */
719 uint32_t *cmd
= &rmesa
->hw
.tex
[unit
].cmd
[TEX_CMD_0
];
720 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
722 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
724 cmd
[TEX_PP_TXFILTER
] &= ~TEXOBJ_TXFILTER_MASK
;
725 cmd
[TEX_PP_TXFILTER
] |= texobj
->pp_txfilter
& TEXOBJ_TXFILTER_MASK
;
726 cmd
[TEX_PP_TXFORMAT
] &= ~TEXOBJ_TXFORMAT_MASK
;
727 cmd
[TEX_PP_TXFORMAT
] |= texobj
->pp_txformat
& TEXOBJ_TXFORMAT_MASK
;
728 cmd
[TEX_PP_BORDER_COLOR
] = texobj
->pp_border_color
;
730 if (texobj
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
) {
731 uint32_t *txr_cmd
= &rmesa
->hw
.txr
[unit
].cmd
[TXR_CMD_0
];
732 txr_cmd
[TXR_PP_TEX_SIZE
] = texobj
->pp_txsize
; /* NPOT only! */
733 txr_cmd
[TXR_PP_TEX_PITCH
] = texobj
->pp_txpitch
; /* NPOT only! */
734 RADEON_STATECHANGE( rmesa
, txr
[unit
] );
737 if (texobj
->base
.Target
== GL_TEXTURE_RECTANGLE_NV
) {
738 se_coord_fmt
|= RADEON_VTX_ST0_NONPARAMETRIC
<< unit
;
741 se_coord_fmt
&= ~(RADEON_VTX_ST0_NONPARAMETRIC
<< unit
);
743 if (texobj
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
744 uint32_t *cube_cmd
= &rmesa
->hw
.cube
[unit
].cmd
[CUBE_CMD_0
];
746 RADEON_STATECHANGE( rmesa
, cube
[unit
] );
747 cube_cmd
[CUBE_PP_CUBIC_FACES
] = texobj
->pp_cubic_faces
;
748 /* state filled out in the cube_emit */
752 if (se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
]) {
753 RADEON_STATECHANGE( rmesa
, set
);
754 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
757 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
761 static void set_texgen_matrix( r100ContextPtr rmesa
,
763 const GLfloat
*s_plane
,
764 const GLfloat
*t_plane
,
765 const GLfloat
*r_plane
,
766 const GLfloat
*q_plane
)
768 rmesa
->TexGenMatrix
[unit
].m
[0] = s_plane
[0];
769 rmesa
->TexGenMatrix
[unit
].m
[4] = s_plane
[1];
770 rmesa
->TexGenMatrix
[unit
].m
[8] = s_plane
[2];
771 rmesa
->TexGenMatrix
[unit
].m
[12] = s_plane
[3];
773 rmesa
->TexGenMatrix
[unit
].m
[1] = t_plane
[0];
774 rmesa
->TexGenMatrix
[unit
].m
[5] = t_plane
[1];
775 rmesa
->TexGenMatrix
[unit
].m
[9] = t_plane
[2];
776 rmesa
->TexGenMatrix
[unit
].m
[13] = t_plane
[3];
778 rmesa
->TexGenMatrix
[unit
].m
[2] = r_plane
[0];
779 rmesa
->TexGenMatrix
[unit
].m
[6] = r_plane
[1];
780 rmesa
->TexGenMatrix
[unit
].m
[10] = r_plane
[2];
781 rmesa
->TexGenMatrix
[unit
].m
[14] = r_plane
[3];
783 rmesa
->TexGenMatrix
[unit
].m
[3] = q_plane
[0];
784 rmesa
->TexGenMatrix
[unit
].m
[7] = q_plane
[1];
785 rmesa
->TexGenMatrix
[unit
].m
[11] = q_plane
[2];
786 rmesa
->TexGenMatrix
[unit
].m
[15] = q_plane
[3];
788 rmesa
->TexGenEnabled
|= RADEON_TEXMAT_0_ENABLE
<< unit
;
789 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
792 /* Returns GL_FALSE if fallback required.
794 static GLboolean
radeon_validate_texgen( struct gl_context
*ctx
, GLuint unit
)
796 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
797 struct gl_fixedfunc_texture_unit
*texUnit
=
798 &ctx
->Texture
.FixedFuncUnit
[unit
];
799 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
800 GLuint tmp
= rmesa
->TexGenEnabled
;
801 static const GLfloat reflect
[16] = {
807 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
);
808 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<< unit
);
809 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<< inputshift
);
810 rmesa
->TexGenNeedNormals
[unit
] = 0;
812 if ((texUnit
->TexGenEnabled
& (S_BIT
|T_BIT
|R_BIT
|Q_BIT
)) == 0) {
813 /* Disabled, no fallback:
815 rmesa
->TexGenEnabled
|=
816 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+ unit
) << inputshift
;
819 /* the r100 cannot do texgen for some coords and not for others
820 * we do not detect such cases (certainly can't do it here) and just
821 * ASSUME that when S and T are texgen enabled we do not need other
822 * non-texgen enabled coords, no matter if the R and Q bits are texgen
823 * enabled. Still check for mixed mode texgen for all coords.
825 else if ( (texUnit
->TexGenEnabled
& S_BIT
) &&
826 (texUnit
->TexGenEnabled
& T_BIT
) &&
827 (texUnit
->GenS
.Mode
== texUnit
->GenT
.Mode
) ) {
828 if ( ((texUnit
->TexGenEnabled
& R_BIT
) &&
829 (texUnit
->GenS
.Mode
!= texUnit
->GenR
.Mode
)) ||
830 ((texUnit
->TexGenEnabled
& Q_BIT
) &&
831 (texUnit
->GenS
.Mode
!= texUnit
->GenQ
.Mode
)) ) {
832 /* Mixed modes, fallback:
834 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
835 fprintf(stderr
, "fallback mixed texgen\n");
838 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
;
841 /* some texgen mode not including both S and T bits */
842 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
843 fprintf(stderr
, "fallback mixed texgen/nontexgen\n");
847 if ((texUnit
->TexGenEnabled
& (R_BIT
| Q_BIT
)) != 0) {
848 /* need this here for vtxfmt presumably. Argh we need to set
849 this from way too many places, would be much easier if we could leave
850 tcl q coord always enabled as on r200) */
851 RADEON_STATECHANGE( rmesa
, tcl
);
852 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_Q_BIT(unit
);
855 switch (texUnit
->GenS
.Mode
) {
856 case GL_OBJECT_LINEAR
:
857 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_OBJ
<< inputshift
;
858 set_texgen_matrix( rmesa
, unit
,
859 texUnit
->GenS
.ObjectPlane
,
860 texUnit
->GenT
.ObjectPlane
,
861 texUnit
->GenR
.ObjectPlane
,
862 texUnit
->GenQ
.ObjectPlane
);
866 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE
<< inputshift
;
867 set_texgen_matrix( rmesa
, unit
,
868 texUnit
->GenS
.EyePlane
,
869 texUnit
->GenT
.EyePlane
,
870 texUnit
->GenR
.EyePlane
,
871 texUnit
->GenQ
.EyePlane
);
874 case GL_REFLECTION_MAP_NV
:
875 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
876 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_REFLECT
<< inputshift
;
877 /* TODO: unknown if this is needed/correct */
878 set_texgen_matrix( rmesa
, unit
, reflect
, reflect
+ 4,
879 reflect
+ 8, reflect
+ 12 );
882 case GL_NORMAL_MAP_NV
:
883 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
884 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_NORMAL
<< inputshift
;
888 /* the mode which everyone uses :-( */
890 /* Unsupported mode, fallback:
892 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
893 fprintf(stderr
, "fallback GL_SPHERE_MAP\n");
897 if (tmp
!= rmesa
->TexGenEnabled
) {
898 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
905 * Compute the cached hardware register values for the given texture object.
907 * \param rmesa Context pointer
908 * \param t the r300 texture object
910 static GLboolean
setup_hardware_state(r100ContextPtr rmesa
, radeonTexObj
*t
, int unit
)
912 const struct gl_texture_image
*firstImage
;
913 GLint log2Width
, log2Height
, texelBytes
;
919 firstImage
= t
->base
.Image
[0][t
->minLod
];
921 log2Width
= firstImage
->WidthLog2
;
922 log2Height
= firstImage
->HeightLog2
;
923 texelBytes
= _mesa_get_format_bytes(firstImage
->TexFormat
);
925 if (!t
->image_override
) {
926 if (VALID_FORMAT(firstImage
->TexFormat
)) {
927 const struct tx_table
*table
= tx_table
;
929 t
->pp_txformat
&= ~(RADEON_TXFORMAT_FORMAT_MASK
|
930 RADEON_TXFORMAT_ALPHA_IN_MAP
);
931 t
->pp_txfilter
&= ~RADEON_YUV_TO_RGB
;
933 t
->pp_txformat
|= table
[ firstImage
->TexFormat
].format
;
934 t
->pp_txfilter
|= table
[ firstImage
->TexFormat
].filter
;
936 _mesa_problem(NULL
, "unexpected texture format in %s",
942 t
->pp_txfilter
&= ~RADEON_MAX_MIP_LEVEL_MASK
;
943 t
->pp_txfilter
|= (t
->maxLod
- t
->minLod
) << RADEON_MAX_MIP_LEVEL_SHIFT
;
945 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
946 RADEON_TXFORMAT_HEIGHT_MASK
|
947 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
948 RADEON_TXFORMAT_F5_WIDTH_MASK
|
949 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
950 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
951 (log2Height
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
955 if (t
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
956 assert(log2Width
== log2Height
);
957 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_F5_WIDTH_SHIFT
) |
958 (log2Height
<< RADEON_TXFORMAT_F5_HEIGHT_SHIFT
) |
959 /* don't think we need this bit, if it exists at all - fglrx does not set it */
960 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE
));
961 t
->pp_cubic_faces
= ((log2Width
<< RADEON_FACE_WIDTH_1_SHIFT
) |
962 (log2Height
<< RADEON_FACE_HEIGHT_1_SHIFT
) |
963 (log2Width
<< RADEON_FACE_WIDTH_2_SHIFT
) |
964 (log2Height
<< RADEON_FACE_HEIGHT_2_SHIFT
) |
965 (log2Width
<< RADEON_FACE_WIDTH_3_SHIFT
) |
966 (log2Height
<< RADEON_FACE_HEIGHT_3_SHIFT
) |
967 (log2Width
<< RADEON_FACE_WIDTH_4_SHIFT
) |
968 (log2Height
<< RADEON_FACE_HEIGHT_4_SHIFT
));
971 t
->pp_txsize
= (((firstImage
->Width
- 1) << RADEON_TEX_USIZE_SHIFT
)
972 | ((firstImage
->Height
- 1) << RADEON_TEX_VSIZE_SHIFT
));
974 if ( !t
->image_override
) {
975 if (_mesa_is_format_compressed(firstImage
->TexFormat
))
976 t
->pp_txpitch
= (firstImage
->Width
+ 63) & ~(63);
978 t
->pp_txpitch
= ((firstImage
->Width
* texelBytes
) + 63) & ~(63);
982 if (t
->base
.Target
== GL_TEXTURE_RECTANGLE_NV
) {
983 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
989 static GLboolean
radeon_validate_texture(struct gl_context
*ctx
, struct gl_texture_object
*texObj
, int unit
)
991 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
992 radeonTexObj
*t
= radeon_tex_obj(texObj
);
995 if (!radeon_validate_texture_miptree(ctx
, _mesa_get_samplerobj(ctx
, unit
), texObj
))
998 ret
= setup_hardware_state(rmesa
, t
, unit
);
1002 /* yuv conversion only works in first unit */
1003 if (unit
!= 0 && (t
->pp_txfilter
& RADEON_YUV_TO_RGB
))
1006 RADEON_STATECHANGE( rmesa
, ctx
);
1007 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |=
1008 (RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
;
1009 RADEON_STATECHANGE( rmesa
, tcl
);
1010 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_ST_BIT(unit
);
1012 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1014 radeonTexUpdateParameters(ctx
, unit
);
1015 import_tex_obj_state( rmesa
, unit
, t
);
1017 if (rmesa
->recheck_texgen
[unit
]) {
1018 GLboolean fallback
= !radeon_validate_texgen( ctx
, unit
);
1019 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), fallback
);
1020 rmesa
->recheck_texgen
[unit
] = 0;
1021 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
1024 if ( ! radeonUpdateTextureEnv( ctx
, unit
) ) {
1027 FALLBACK( rmesa
, RADEON_FALLBACK_BORDER_MODE
, t
->border_fallback
);
1029 t
->validated
= GL_TRUE
;
1030 return !t
->border_fallback
;
1033 static GLboolean
radeonUpdateTextureUnit( struct gl_context
*ctx
, int unit
)
1035 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1037 if (ctx
->Texture
.Unit
[unit
]._Current
&&
1038 ctx
->Texture
.Unit
[unit
]._Current
->Target
== GL_TEXTURE_3D
) {
1039 disable_tex_obj_state(rmesa
, unit
);
1040 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1044 if (!ctx
->Texture
.Unit
[unit
]._Current
) {
1045 /* disable the unit */
1046 disable_tex_obj_state(rmesa
, unit
);
1047 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1051 if (!radeon_validate_texture(ctx
, ctx
->Texture
.Unit
[unit
]._Current
, unit
)) {
1053 "failed to validate texture for unit %d.\n",
1055 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1058 rmesa
->state
.texture
.unit
[unit
].texobj
= radeon_tex_obj(ctx
->Texture
.Unit
[unit
]._Current
);
1062 void radeonUpdateTextureState( struct gl_context
*ctx
)
1064 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1067 /* set the ctx all textures off */
1068 RADEON_STATECHANGE( rmesa
, ctx
);
1069 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~((RADEON_TEX_ENABLE_MASK
) | (RADEON_TEX_BLEND_ENABLE_MASK
));
1071 ok
= (radeonUpdateTextureUnit( ctx
, 0 ) &&
1072 radeonUpdateTextureUnit( ctx
, 1 ) &&
1073 radeonUpdateTextureUnit( ctx
, 2 ));
1075 FALLBACK( rmesa
, RADEON_FALLBACK_TEXTURE
, !ok
);
1077 if (rmesa
->radeon
.TclFallback
)
1078 radeonChooseVertexState( ctx
);